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authorCyril Jourdan2012-08-08 11:12:36 +0200
committerCyril Jourdan2012-09-20 09:42:56 +0200
commite701858bceda0cb76d58f947b0fe68cb6323c96e (patch)
tree3247cb17c4283a2ec88b30bb45997c225f22542f
parent0b7839300e7022376c9237d2edab4e4f0ee5ec61 (diff)
{cleo/u-boot, common}: use common/include/asm/arch/ips, refs #3119
-rw-r--r--cleopatre/Makefile7
-rw-r--r--cleopatre/u-boot-1.1.6/Makefile5
-rw-r--r--cleopatre/u-boot-1.1.6/board/sdk300/sdk300.c7
-rw-r--r--cleopatre/u-boot-1.1.6/cpincludes.mk7
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/dsp.S26
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/eth_init.S90
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/pll_init.S78
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/reset.S4
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/sdram.S6
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/serial.c1
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/start.S50
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/wdt.c2
-rw-r--r--cleopatre/u-boot-1.1.6/drivers/netspcmac_eth.c33
-rw-r--r--cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/.gitignore32
-rw-r--r--cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_apb.h52
-rw-r--r--cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_gpio.h138
-rw-r--r--cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_ictl.h588
-rw-r--r--cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_timer1.h134
-rw-r--r--cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_timer2.h134
-rw-r--r--cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_uart1.h169
-rw-r--r--cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_uart2.h160
-rw-r--r--cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_wdt.h128
-rw-r--r--cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/boot_arm_hard.h102
-rw-r--r--cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/bus_sys.h54
-rw-r--r--cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/dsp.h28
-rw-r--r--cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/ethernet_ctrl.h748
-rw-r--r--cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/gpdma.h135
-rw-r--r--cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/hardware.h5
-rw-r--r--cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/i2s.h48
-rw-r--r--cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/pcm.h49
-rw-r--r--cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/pkg_maria_regbank.h256
-rw-r--r--cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/sdk300.h62
-rw-r--r--cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/sdram.h933
-rw-r--r--cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/spi.h48
-rw-r--r--cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/sys_apb.h42
-rw-r--r--cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/wdt.h66
-rw-r--r--common/include/asm/arch/ips/gic.h4
-rw-r--r--common/include/asm/arch/ips/gpio.h3
-rw-r--r--common/include/asm/arch/ips/hardware/bus_sys.h9
-rw-r--r--common/include/asm/arch/ips/hardware/dsp.h31
-rw-r--r--common/include/asm/arch/ips/hardware/ethernet_ctrl.h14
-rw-r--r--common/include/asm/arch/ips/hardware/gpdma.h1
-rw-r--r--common/include/asm/arch/ips/hardware/miu.h (renamed from cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/miu.h)21
-rw-r--r--common/include/asm/arch/ips/hardware/mpeg_ts.h (renamed from cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/mpeg_ts.h)23
-rw-r--r--common/include/asm/arch/ips/hardware/pcm.h2
-rw-r--r--common/include/asm/arch/ips/hardware/pkg_maria_regbank.h21
-rw-r--r--common/include/asm/arch/ips/hardware/sdram.h4
-rw-r--r--common/include/asm/arch/ips/hardware/sys_apb.h1
-rw-r--r--common/include/asm/arch/ips/ips_access.h9
-rw-r--r--common/include/asm/arch/ips/regbank.h2
-rw-r--r--common/include/asm/arch/ips/spi.h2
-rw-r--r--common/include/asm/arch/ips/timer.h2
-rw-r--r--common/include/asm/arch/ips/wdt.h6
53 files changed, 325 insertions, 4257 deletions
diff --git a/cleopatre/Makefile b/cleopatre/Makefile
index 2dbed00699..cdaddd95c9 100644
--- a/cleopatre/Makefile
+++ b/cleopatre/Makefile
@@ -149,9 +149,16 @@ bundle-clean-standalone:
prepare-includes:
+# We have to remove gitignore files here because, in our git repository, those includes are based in the common/
+# directory and the ones in linux and u-boot are just copies we must ignore. But, once copied in the bundle, linux
+# and u-boot are their actual base locations and they must not be ignored anymore.
+# Moreover, gitignore files are not usually removed, that is why we have to handle them individually.
$(Q)$(BUNDLE_PATH)/linux-$(LINUX_VERSION)-spc300/scripts/cpincludes $(BUNDLE_PATH)/linux-$(LINUX_VERSION)-spc300
$(Q)rm -f $(BUNDLE_PATH)/linux-$(LINUX_VERSION)-spc300/scripts/cpincludes
$(Q)rm -f $(BUNDLE_PATH)/linux-$(LINUX_VERSION)-spc300/include/asm-arm/arch-spc300/.gitignore
+ $(Q)$(MAKE) -C $(UBOOT_PATH) cpincludes
+ $(Q)rm -f $(UBOOT_PATH)/cpincludes.mk
+ $(Q)rm -f $(UBOOT_PATH)/include/asm-arm/arch-spc300/.gitignore
cesar-plc-debug:
$(Q)$(MAKE) -C $(CESAR_PRJ_PATH)/plc clean
diff --git a/cleopatre/u-boot-1.1.6/Makefile b/cleopatre/u-boot-1.1.6/Makefile
index 4dc819713c..1e97c88218 100644
--- a/cleopatre/u-boot-1.1.6/Makefile
+++ b/cleopatre/u-boot-1.1.6/Makefile
@@ -299,6 +299,9 @@ env:
$(MAKE) -C tools/env all || exit 1
depend dep:
+ifeq (found, $(shell [ -f $(SRCTREE)/cpincludes.mk ] && echo found))
+ $(MAKE) cpincludes
+endif
for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir _depend ; done
tags ctags:
@@ -330,6 +333,8 @@ dep tags ctags etags $(obj)System.map:
@ exit 1
endif
+-include cpincludes.mk
+
.PHONY : CHANGELOG
CHANGELOG:
git log --no-merges U-Boot-1_1_5.. | \
diff --git a/cleopatre/u-boot-1.1.6/board/sdk300/sdk300.c b/cleopatre/u-boot-1.1.6/board/sdk300/sdk300.c
index 201ff99d56..1ddd0af416 100644
--- a/cleopatre/u-boot-1.1.6/board/sdk300/sdk300.c
+++ b/cleopatre/u-boot-1.1.6/board/sdk300/sdk300.c
@@ -23,7 +23,6 @@
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/nvram.h>
-#include <asm/arch/pkg_maria_regbank.h>
extern void enable_mmu(void);
@@ -150,14 +149,14 @@ int board_init (void)
#ifdef CONFIG_CHIP_FEATURE_DINI_UART_SELECT
/* Select UART. */
- writel(RB_DINI_UART_SELECT_ARM, MARIA_REGBANK_BASE + (RB_DINI_UART_SELECT));
+ writel(RB_DINI_UART_SELECT_ARM, RB_DINI_UART_SELECT);
#endif
#ifdef CONFIG_CHIP_FEATURE_SYNOP3504_PHY_RX_CLOCK_INVERT
/* Invert RX Ethernet clock. */
- writel(readl (MARIA_REGBANK_BASE + RB_DINI_SPARE_1)
+ writel(readl (RB_DINI_SPARE_1)
| RB_DINI_SPARE_1_ETH_RX_CLOCK_INVERT,
- MARIA_REGBANK_BASE + RB_DINI_SPARE_1);
+ RB_DINI_SPARE_1);
#endif
/* Enable Ctrlc */
diff --git a/cleopatre/u-boot-1.1.6/cpincludes.mk b/cleopatre/u-boot-1.1.6/cpincludes.mk
new file mode 100644
index 0000000000..28ca59ab1a
--- /dev/null
+++ b/cleopatre/u-boot-1.1.6/cpincludes.mk
@@ -0,0 +1,7 @@
+UBOOT_INC=$(SRCTREE)/include/asm-arm/arch-spc300
+COMMON_INC=$(SRCTREE)/../../common/include/asm/arch
+
+cpincludes:
+ rm -rf $(UBOOT_INC)/ips
+ cp -r $(COMMON_INC)/ips $(UBOOT_INC)
+
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/dsp.S b/cleopatre/u-boot-1.1.6/cpu/spc300/dsp.S
index f5141b4276..bc3a16fe71 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/dsp.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/dsp.S
@@ -34,7 +34,7 @@
.type dsp_init, %function
-/* WARNING : Assume that for macros r0=REGBANK_BASE and r1 is not used. */
+/* WARNING : Assume that for macros r0=MARIA_REGBANK_BASE and r1 is not used. */
.macro cmdoff, offset
ldr r1, =CLK_CMD_OFF
str r1, [r0, #\offset]
@@ -69,7 +69,7 @@
.endm
dsp_init:
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
/* Set PHY CPU start instructions */
@@ -77,7 +77,7 @@ dsp_init:
* its start code in sdram, so we need to prepare it first. */
/* Change PHY processeur start address to SDRAM base addr */
- setreg RB_LEON_ADD_START, 0x00000000
+ setreg RB_LEON_ADD_START_OFFSET, 0x00000000
/* Set SDRAM with NOP instruction for PHY CPU */
ldr r2, =PHYS_SDRAM /* Physical address of PCPU for booting at 0 */
@@ -94,24 +94,24 @@ dsp_init:
/* End Set PHY CPU start instructions */
/* Assert DSP reset, Normally already done. */
- setbit RB_RST_GROUP, RST_DSP
+ setbit RB_RST_GROUP_OFFSET, RST_DSP
/* Disable DSP clock, Normally already done. */
- cmdoff RB_CLK_CMD_DSP
- checkreg RB_CLK_STAT_DSP, CLK_IS_OFF
+ cmdoff RB_CLK_CMD_DSP_OFFSET
+ checkreg RB_CLK_STAT_DSP_OFFSET, CLK_IS_OFF
/* Disable AFE clock, Normally already done. */
- cmdoff RB_CLK_CMD_AFE
- checkreg RB_CLK_STAT_AFE, CLK_IS_OFF
+ cmdoff RB_CLK_CMD_AFE_OFFSET
+ checkreg RB_CLK_STAT_AFE_OFFSET, CLK_IS_OFF
/* Enable AFE clock. */
- cmdon RB_CLK_CMD_AFE
- checkreg RB_CLK_STAT_AFE, CLK_IS_ON
+ cmdon RB_CLK_CMD_AFE_OFFSET
+ checkreg RB_CLK_STAT_AFE_OFFSET, CLK_IS_ON
/* Prepare register addresses needed during synchronisation process. */
- ldr r7, =(DSP_PRATIC_BASE+DSP_PRATIC_STA_LOCAL_TIMER)
- ldr r6, =(REGBANK_BASE+RB_CLK_CMD_DSP)
- ldr r5, =(REGBANK_BASE+RB_RST_GROUP)
+ ldr r7, =DSP_PRATIC_STA_LOCAL_TIMER
+ ldr r6, =(MARIA_REGBANK_BASE+RB_CLK_CMD_DSP_OFFSET)
+ ldr r5, =(MARIA_REGBANK_BASE+RB_RST_GROUP_OFFSET)
/* Save RB_RST_GROUP register before changing LEONSS and DSP resets. */
ldr r4, [r5]
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/eth_init.S b/cleopatre/u-boot-1.1.6/cpu/spc300/eth_init.S
index 043db6acce..a337174206 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/eth_init.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/eth_init.S
@@ -35,7 +35,7 @@
.type ethernet_config, %function
-/* WARNING : Assusme that for macros r0=REGBANK_BASE and r1 is not used */
+/* WARNING : Assusme that for macros r0=MARIA_REGBANK_BASE and r1 is not used */
.macro cmdoff, offset
ldr r1, =CLK_CMD_OFF
str r1, [r0, #\offset]
@@ -58,33 +58,33 @@
.endm
ethernet_config:
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
/*
* Switch off all Ethernet clock commands
*/
- cmdoff RB_CLK_CMD_ETH_TX_125
- checkreg RB_CLK_STAT_ETH_TX_125, CLK_IS_OFF
+ cmdoff RB_CLK_CMD_ETH_TX_125_OFFSET
+ checkreg RB_CLK_STAT_ETH_TX_125_OFFSET, CLK_IS_OFF
- cmdoff RB_CLK_CMD_ETH_TX_EXT
- checkreg RB_CLK_STAT_ETH_TX_EXT, CLK_IS_OFF
+ cmdoff RB_CLK_CMD_ETH_TX_EXT_OFFSET
+ checkreg RB_CLK_STAT_ETH_TX_EXT_OFFSET, CLK_IS_OFF
- cmdoff RB_CLK_CMD_ETH_RX_EXT
- checkreg RB_CLK_STAT_ETH_RX_EXT, CLK_IS_OFF
+ cmdoff RB_CLK_CMD_ETH_RX_EXT_OFFSET
+ checkreg RB_CLK_STAT_ETH_RX_EXT_OFFSET, CLK_IS_OFF
- cmdoff RB_CLK_CMD_ETH_RMII
- checkreg RB_CLK_STAT_ETH_RMII, CLK_IS_OFF
+ cmdoff RB_CLK_CMD_ETH_RMII_OFFSET
+ checkreg RB_CLK_STAT_ETH_RMII_OFFSET, CLK_IS_OFF
/*
* Enable PHY Clock
*/
/* release EXT reset for ETH PHY clock */
- ldr r1, [r0, #RB_RST_MODULE]
+ ldr r1, [r0, #RB_RST_MODULE_OFFSET]
bic r1, r1, #RST_EXT /* clear bit 12 of RB_RST_MODULE, sw_rst_ext -> 0 */
- str r1, [r0, #RB_RST_MODULE]
+ str r1, [r0, #RB_RST_MODULE_OFFSET]
/* Enable PHY Clock */
- cmdon RB_CLK_CMD_OUT25
- checkreg RB_CLK_STAT_OUT25, CLK_IS_ON
+ cmdon RB_CLK_CMD_OUT25_OFFSET
+ checkreg RB_CLK_STAT_OUT25_OFFSET, CLK_IS_ON
/*
@@ -104,24 +104,24 @@ ethernet_config:
* GMII mode
*/
/* Ethernet Config for GMII mode */
- setreg RB_ETH_CONFIG, 0
+ setreg RB_ETH_CONFIG_OFFSET, 0
/* Enable TX 125MHz clock */
- setreg RB_CLK_SEL_ETH_MAC, CLK_SEL_ETH_MAC_125
- checkreg RB_CLK_SEL_STAT_ETH_MAC, CLK_SEL_ETH_MAC_125
+ setreg RB_CLK_SEL_ETH_MAC_OFFSET, CLK_SEL_ETH_MAC_125
+ checkreg RB_CLK_SEL_STAT_ETH_MAC_OFFSET, CLK_SEL_ETH_MAC_125
- setreg RB_CLK_SEL_ETH_TX, CLK_SEL_ETH_TX_125
- checkreg RB_CLK_SEL_STAT_ETH_TX, CLK_SEL_ETH_TX_125
+ setreg RB_CLK_SEL_ETH_TX_OFFSET, CLK_SEL_ETH_TX_125
+ checkreg RB_CLK_SEL_STAT_ETH_TX_OFFSET, CLK_SEL_ETH_TX_125
- cmdon RB_CLK_CMD_ETH_TX_125
- checkreg RB_CLK_STAT_ETH_TX_125, CLK_IS_ON
+ cmdon RB_CLK_CMD_ETH_TX_125_OFFSET
+ checkreg RB_CLK_STAT_ETH_TX_125_OFFSET, CLK_IS_ON
/* Enable RX ext clock */
- setreg RB_CLK_SEL_ETH_RX, CLK_SEL_ETH_RX_EXT
- checkreg RB_CLK_SEL_STAT_ETH_RX, CLK_SEL_ETH_RX_EXT
+ setreg RB_CLK_SEL_ETH_RX_OFFSET, CLK_SEL_ETH_RX_EXT
+ checkreg RB_CLK_SEL_STAT_ETH_RX_OFFSET, CLK_SEL_ETH_RX_EXT
- cmdon RB_CLK_CMD_ETH_RX_EXT
- checkreg RB_CLK_STAT_ETH_RX_EXT, CLK_IS_ON
+ cmdon RB_CLK_CMD_ETH_RX_EXT_OFFSET
+ checkreg RB_CLK_STAT_ETH_RX_EXT_OFFSET, CLK_IS_ON
bal 100f
@@ -130,21 +130,21 @@ ethernet_config:
*/
10:
/* Ethernet Config for MII mode */
- setreg RB_ETH_CONFIG, 0
+ setreg RB_ETH_CONFIG_OFFSET, 0
/* Enable TX_ext clock */
- setreg RB_CLK_SEL_ETH_TX, CLK_SEL_ETH_TX_EXT
- checkreg RB_CLK_SEL_STAT_ETH_TX, CLK_SEL_ETH_TX_EXT
+ setreg RB_CLK_SEL_ETH_TX_OFFSET, CLK_SEL_ETH_TX_EXT
+ checkreg RB_CLK_SEL_STAT_ETH_TX_OFFSET, CLK_SEL_ETH_TX_EXT
- cmdon RB_CLK_CMD_ETH_TX_EXT
- checkreg RB_CLK_STAT_ETH_TX_EXT, CLK_IS_ON
+ cmdon RB_CLK_CMD_ETH_TX_EXT_OFFSET
+ checkreg RB_CLK_STAT_ETH_TX_EXT_OFFSET, CLK_IS_ON
/* Enable RX_ext clock */
- setreg RB_CLK_SEL_ETH_RX, CLK_SEL_ETH_RX_EXT
- checkreg RB_CLK_SEL_STAT_ETH_RX, CLK_SEL_ETH_RX_EXT
+ setreg RB_CLK_SEL_ETH_RX_OFFSET, CLK_SEL_ETH_RX_EXT
+ checkreg RB_CLK_SEL_STAT_ETH_RX_OFFSET, CLK_SEL_ETH_RX_EXT
- cmdon RB_CLK_CMD_ETH_RX_EXT
- checkreg RB_CLK_STAT_ETH_RX_EXT, CLK_IS_ON
+ cmdon RB_CLK_CMD_ETH_RX_EXT_OFFSET
+ checkreg RB_CLK_STAT_ETH_RX_EXT_OFFSET, CLK_IS_ON
bal 100f
@@ -154,26 +154,26 @@ ethernet_config:
*/
20:
/* Ethernet Config for RMII mode */
- setreg RB_ETH_CONFIG, (ETH_CFG_RMII|ETH_CFG_RMII_100)
+ setreg RB_ETH_CONFIG_OFFSET, (ETH_CFG_RMII|ETH_CFG_RMII_100)
/* Enable TX 25MHz clock */
- setreg RB_CLK_SEL_ETH_TX, CLK_SEL_ETH_TX_25
- checkreg RB_CLK_SEL_STAT_ETH_TX, CLK_SEL_ETH_TX_25
+ setreg RB_CLK_SEL_ETH_TX_OFFSET, CLK_SEL_ETH_TX_25
+ checkreg RB_CLK_SEL_STAT_ETH_TX_OFFSET, CLK_SEL_ETH_TX_25
/* Enable RX 25MHz clock */
- setreg RB_CLK_SEL_ETH_RX, CLK_SEL_ETH_RX_25
- checkreg RB_CLK_SEL_STAT_ETH_RX, CLK_SEL_ETH_RX_25
+ setreg RB_CLK_SEL_ETH_RX_OFFSET, CLK_SEL_ETH_RX_25
+ checkreg RB_CLK_SEL_STAT_ETH_RX_OFFSET, CLK_SEL_ETH_RX_25
/* Put RMII clock to 50MHz we assume that RMII is always 100Mbits */
- setreg RB_CLK_DIV_ETH_25, CLK_DIV_ETH_25_2
- checkreg RB_CLK_DIV_STAT_ETH_25, CLK_DIV_ETH_25_2
+ setreg RB_CLK_DIV_ETH_25_OFFSET, CLK_DIV_ETH_25_2
+ checkreg RB_CLK_DIV_STAT_ETH_25_OFFSET, CLK_DIV_ETH_25_2
- setreg RB_CLK_SEL_ETH_MAC, CLK_SEL_ETH_MAC_RMII
- checkreg RB_CLK_SEL_STAT_ETH_MAC, CLK_SEL_ETH_MAC_RMII
+ setreg RB_CLK_SEL_ETH_MAC_OFFSET, CLK_SEL_ETH_MAC_RMII
+ checkreg RB_CLK_SEL_STAT_ETH_MAC_OFFSET, CLK_SEL_ETH_MAC_RMII
/* Enable RMII */
- cmdon RB_CLK_CMD_ETH_RMII
- checkreg RB_CLK_STAT_ETH_RMII, CLK_IS_ON
+ cmdon RB_CLK_CMD_ETH_RMII_OFFSET
+ checkreg RB_CLK_STAT_ETH_RMII_OFFSET, CLK_IS_ON
100:
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/pll_init.S b/cleopatre/u-boot-1.1.6/cpu/spc300/pll_init.S
index 767b886855..5f52389a99 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/pll_init.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/pll_init.S
@@ -52,19 +52,19 @@ pll_init:
* Switch OFF PLLs (before doing configuration)
*/
/* System PLL */
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
ldr r1, =PLL_CMD_OFF
- str r1, [r0, #RB_SPLL_PD]
+ str r1, [r0, #RB_SPLL_PD_OFFSET]
/* Peripheral PLL */
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
ldr r1, =PLL_CMD_OFF
- str r1, [r0, #RB_PPLL_PD]
+ str r1, [r0, #RB_PPLL_PD_OFFSET]
/* DSP PLL */
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
ldr r1, =PLL_CMD_OFF
- str r1, [r0, #RB_DPLL_PD]
+ str r1, [r0, #RB_DPLL_PD_OFFSET]
/*
* Configure PLLs (while switched off)
@@ -85,85 +85,85 @@ pll_init:
/* System PLL */
/* config : fbdiv, prediv, lbws, sscg_enable, sscg_fcw, sscg_fmw, sscg_mdw */
/* PLL_CLK_600MHz */
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
ldr r1, = 0
- str r1, [r0, #RB_SPLL_EN] /* RB_SPLL_EN = 0 */
+ str r1, [r0, #RB_SPLL_EN_OFFSET] /* RB_SPLL_EN = 0 */
adr r4, .LpoolSYSfbdiv /* r4 points to the begining of the array */
ldr r1, [r4, r3] /* r1 = array[Xclk*16 + Freq*4]; we take the element of the array indexed with Xclk */
- str r1, [r0, #RB_SPLL_FBDIV]
+ str r1, [r0, #RB_SPLL_FBDIV_OFFSET]
adr r4, .LpoolSYSprediv /* r4 points to the begining of the array */
ldr r1, [r4, r3] /* r1 = array[Xclk*16 + Freq*4]; we take the element of the array indexed with Xclk */
- str r1, [r0, #RB_SPLL_PREDIV]
+ str r1, [r0, #RB_SPLL_PREDIV_OFFSET]
ldr r1, = PLL_LBWS_ON
- str r1, [r0, #RB_SPLL_LBWS] /* RB_SPLL_LBWS = 1 */
+ str r1, [r0, #RB_SPLL_LBWS_OFFSET] /* RB_SPLL_LBWS = 1 */
ldr r1, = 1 /* turn on spread spectrum */
- str r1, [r0, #RB_SPLL_EN] /* RB_SPLL_EN = 1 */
+ str r1, [r0, #RB_SPLL_EN_OFFSET] /* RB_SPLL_EN = 1 */
adr r4, .LSpreadSpectrumFCW /* turn on spread spectrum */
ldr r1, [r4, r5]
- str r1, [r0, #RB_SPLL_FCW] /* RB_SPLL_FCW = See table... */
+ str r1, [r0, #RB_SPLL_FCW_OFFSET] /* RB_SPLL_FCW = See table... */
adr r4, .LSpreadSpectrumFMW
ldr r1, [r4, r5]
- str r1, [r0, #RB_SPLL_FMW] /* RB_SPLL_FMW = See table... */
+ str r1, [r0, #RB_SPLL_FMW_OFFSET] /* RB_SPLL_FMW = See table... */
adr r4, .LSpreadSpectrumMDW
ldr r1, [r4, r5]
- str r1, [r0, #RB_SPLL_MDW] /* RB_SPLL_MDW = See table... */
+ str r1, [r0, #RB_SPLL_MDW_OFFSET] /* RB_SPLL_MDW = See table... */
/* Peripheral PLL */
/* config : fbdiv, prediv, lbws, sscg_enable, sscg_fcw, sscg_fmw, sscg_mdw */
/* PLL_CLK_600MHz */
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
adr r4, .LpoolPERIPHfbdiv /* r4 points to the begining of the array */
ldr r1, [r4, r2] /* r1 = array[Xclk*4]; we take the element of the array indexed with Xclk */
- str r1, [r0, #RB_PPLL_FBDIV]
+ str r1, [r0, #RB_PPLL_FBDIV_OFFSET]
adr r4, .LpoolPERIPHprediv /* r4 points to the begining of the array */
ldr r1, [r4, r2] /* r1 = array[Xclk*4]; we take the element of the array indexed with Xclk */
- str r1, [r0, #RB_PPLL_PREDIV]
+ str r1, [r0, #RB_PPLL_PREDIV_OFFSET]
ldr r1, = PLL_LBWS_OFF
- str r1, [r0, #RB_PPLL_LBWS] /* RB_PPLL_LBWS = 0 */
+ str r1, [r0, #RB_PPLL_LBWS_OFFSET] /* RB_PPLL_LBWS = 0 */
/* DSP PLL */
/* config : fbdiv, prediv, lbws, sscg_enable, sscg_fcw, sscg_fmw, sscg_mdw */
/* PLL_CLK_600MHz */
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
adr r4, .LpoolDSPfbdiv /* r4 points to the begining of the array */
ldr r1, [r4, r2] /* r1 = array[Xclk*4]; we take the element of the array indexed with Xclk */
- str r1, [r0, #RB_DPLL_FBDIV]
+ str r1, [r0, #RB_DPLL_FBDIV_OFFSET]
adr r4, .LpoolDSPprediv /* r4 points to the begining of the array */
ldr r1, [r4, r2] /* r1 = array[Xclk*4]; we take the element of the array indexed with Xclk */
- str r1, [r0, #RB_DPLL_PREDIV]
+ str r1, [r0, #RB_DPLL_PREDIV_OFFSET]
ldr r1, = PLL_LBWS_OFF
- str r1, [r0, #RB_DPLL_LBWS] /* RB_DPLL_LBWS = 0 */
+ str r1, [r0, #RB_DPLL_LBWS_OFFSET] /* RB_DPLL_LBWS = 0 */
/* System PLL */
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
/* Release spread spectrum reset */
ldr r1, = 1
- str r1, [r0, #RB_SPLL_SSCGNRST]
+ str r1, [r0, #RB_SPLL_SSCGNRST_OFFSET]
/*
* Switch ON PLLs and wait 200uS (or more)
* until they stabilize
*/
ldr r1, =PLL_CMD_ON
- str r1, [r0, #RB_SPLL_PD]
+ str r1, [r0, #RB_SPLL_PD_OFFSET]
/* Peripheral PLL */
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
ldr r1, =PLL_CMD_ON
- str r1, [r0, #RB_PPLL_PD]
+ str r1, [r0, #RB_PPLL_PD_OFFSET]
/* DSP PLL */
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
ldr r1, =PLL_CMD_ON
- str r1, [r0, #RB_DPLL_PD]
+ str r1, [r0, #RB_DPLL_PD_OFFSET]
/* active wait */
ldr r0, =PLL_WAIT_TIME
@@ -176,29 +176,29 @@ pll_init:
* Switch to PLL clock
*/
/* System PLL */
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
ldr r1, =PLL_CMD_PLL
- str r1, [r0, #RB_SPLL_BYPASS]
+ str r1, [r0, #RB_SPLL_BYPASS_OFFSET]
.LpollSPLLstat:
- ldr r1, [r0, #RB_SPLL_BYPASS_STAT]
+ ldr r1, [r0, #RB_SPLL_BYPASS_STAT_OFFSET]
cmp r1, #PLL_IS_PLL
bne .LpollSPLLstat
/* Peripheral PLL */
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
ldr r1, =PLL_CMD_PLL
- str r1, [r0, #RB_PPLL_BYPASS]
+ str r1, [r0, #RB_PPLL_BYPASS_OFFSET]
.LpollPPLLstat:
- ldr r1, [r0, #RB_PPLL_BYPASS_STAT]
+ ldr r1, [r0, #RB_PPLL_BYPASS_STAT_OFFSET]
cmp r1, #PLL_IS_PLL
bne .LpollPPLLstat
/* DSP PLL */
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
ldr r1, =PLL_CMD_PLL
- str r1, [r0, #RB_DPLL_BYPASS]
+ str r1, [r0, #RB_DPLL_BYPASS_OFFSET]
.LpollDPLLstat:
- ldr r1, [r0, #RB_DPLL_BYPASS_STAT]
+ ldr r1, [r0, #RB_DPLL_BYPASS_STAT_OFFSET]
cmp r1, #PLL_IS_PLL
bne .LpollDPLLstat
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/reset.S b/cleopatre/u-boot-1.1.6/cpu/spc300/reset.S
index afa82b8179..1da52d328c 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/reset.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/reset.S
@@ -25,9 +25,9 @@
.align 5
.globl reset_cpu
reset_cpu:
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
mov r1, #1
- str r1, [r0, #RB_RST_GLOBAL]
+ str r1, [r0, #RB_RST_GLOBAL_OFFSET]
_loop_forever:
b _loop_forever
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/sdram.S b/cleopatre/u-boot-1.1.6/cpu/spc300/sdram.S
index a61bb8fbc0..b4b25f92e2 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/sdram.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/sdram.S
@@ -36,9 +36,9 @@
sdram_init:
/* set up return latency, needed for system clock */
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
mov r1, #0
- str r1, [r0, #RB_SDRAM_RETURN_LAT]
+ str r1, [r0, #RB_SDRAM_RETURN_LAT_OFFSET]
/* do sdram init */
ldr r1, =SDRAM_CTRL_BASE
@@ -74,7 +74,7 @@ sdram_init:
/* Set SDRAM latch when freq > 143MHZ */
ldr r3, =MARIA_REGBANK_BASE
mov r2, #1
- str r2, [r3, #RB_SDRAM_RETURN_LAT]
+ str r2, [r3, #RB_SDRAM_RETURN_LAT_OFFSET]
.NotHighSpeed:
/* reinitialize SDRAM for changes to take effect */
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/serial.c b/cleopatre/u-boot-1.1.6/cpu/spc300/serial.c
index 9d036aafc1..b503c4a611 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/serial.c
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/serial.c
@@ -24,6 +24,7 @@
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/nvram.h>
+#include <asm/arch/ips/uart.h>
#if !defined(CONFIG_USART0)
#error must define CONFIG_USART0
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
index f055819e66..9fc0e52926 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
@@ -255,9 +255,9 @@ clbss_l:
mov pc, r1 /* go to this address in SDRAM (in_sdram label) */
in_sdram:
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
ldr r1, =0x00000001
- str r1, [r0, #RB_BUS_SYS_REMAPPED]
+ str r1, [r0, #RB_BUS_SYS_REMAPPED_OFFSET]
/*
* Check if a correct NVRAM was found
@@ -295,23 +295,23 @@ in_sdram:
* Release the resets
*/
/* ETH reset */
- ldr r0, =REGBANK_BASE
- ldr r1, [r0, #RB_RST_GROUP]
+ ldr r0, =MARIA_REGBANK_BASE
+ ldr r1, [r0, #RB_RST_GROUP_OFFSET]
bic r1, r1, #RST_INTF /* clear bit 1 of RB_RST_GROUP, sw_rst_intf -> 0 */
- str r1, [r0, #RB_RST_GROUP]
+ str r1, [r0, #RB_RST_GROUP_OFFSET]
/*
* Force Reset out for PHY Ethernet during 10ms
*/
- ldr r0, =REGBANK_BASE
- ldr r1, [r0, #RB_RST_MODULE]
+ ldr r0, =MARIA_REGBANK_BASE
+ ldr r1, [r0, #RB_RST_MODULE_OFFSET]
bic r1, r1, #RST_EXT /* clear bit 12 of RB_RST_MODULE, sw_rst_ext -> 0 */
- str r1, [r0, #RB_RST_MODULE]
+ str r1, [r0, #RB_RST_MODULE_OFFSET]
- ldr r0, =REGBANK_BASE
- ldr r1, [r0, #RB_RST_MODULE]
+ ldr r0, =MARIA_REGBANK_BASE
+ ldr r1, [r0, #RB_RST_MODULE_OFFSET]
orr r1, r1, #RST_EXT /* set bit 12 of RB_RST_MODULE, sw_rst_ext -> 1 */
- str r1, [r0, #RB_RST_MODULE]
+ str r1, [r0, #RB_RST_MODULE_OFFSET]
ldr r0, =ETH_PHY_RESET_WAIT_TIME
.Lwaitrst:
@@ -326,11 +326,11 @@ bl_no_nvram:
#ifndef CONFIG_CHIP_FEATURE_NO_RESET
/* EXT reset */
- ldr r0, =REGBANK_BASE
- ldr r1, [r0, #RB_RST_MODULE]
+ ldr r0, =MARIA_REGBANK_BASE
+ ldr r1, [r0, #RB_RST_MODULE_OFFSET]
bic r1, r1, #RST_ETH /* clear bit 8 of RB_RST_MODULE, sw_rst_eth -> 0 */
bic r1, r1, #RST_EXT /* clear bit 12 of RB_RST_MODULE, sw_rst_ext -> 0 */
- str r1, [r0, #RB_RST_MODULE]
+ str r1, [r0, #RB_RST_MODULE_OFFSET]
#endif
@@ -364,13 +364,13 @@ cpu_init_crit:
#ifndef CONFIG_CHIP_FEATURE_FIXED_ARM_CLOCK
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
ldr r1, =CLK_DIV_ARM_2
- str r1, [r0, #RB_CLK_DIV_ARM] /* 0 -> RB_CLK_DIV_ARM CLK_ARM = CLK_AHB * 2*/
+ str r1, [r0, #RB_CLK_DIV_ARM_OFFSET] /* 0 -> RB_CLK_DIV_ARM CLK_ARM = CLK_AHB * 2*/
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
poll_RB_CLK_DIV_STAT_ARM:
- ldr r1, [r0, #RB_CLK_DIV_STAT_ARM]
+ ldr r1, [r0, #RB_CLK_DIV_STAT_ARM_OFFSET]
cmp r1, #CLK_DIV_ARM_2
bne poll_RB_CLK_DIV_STAT_ARM
@@ -429,8 +429,8 @@ gpio_pio_init:
/*
* GPIO init
*/
- ldr r0, =REGBANK_BASE
- add r0, r0, #RB_GPIO_0_CONFIG-4
+ ldr r0, =MARIA_REGBANK_BASE
+ add r0, r0, #RB_GPIO_0_CONFIG_OFFSET-4
mov r2, #0
/* GPIO 0-7*/
@@ -457,13 +457,13 @@ gpio_pio_init:
/*
* PIO init
*/
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
ldr r1, [r10, #NVRAM_PKG_CFG_OFFSET] /* r1 = pkg_cfg; loaded from NVRAM */
lsr r1, r1, #NVRAM_PIO_SHIFT
and r1, #NVRAM_PIO_MASK /* r1 = pio */
- str r1, [r0, #RB_PIO_CONFIG]
+ str r1, [r0, #RB_PIO_CONFIG_OFFSET]
ldr r1, =0x01
- str r1, [r0, #RB_PIO_ENABLE]
+ str r1, [r0, #RB_PIO_ENABLE_OFFSET]
mov pc, lr /* back to my caller */
@@ -488,8 +488,8 @@ timer_clock_config:
moveq r2, #5 /* yes: timer_clk = xclk/(2*(5+1)) = 3.125MHz */
/* store prescaler */
- ldr r0, =REGBANK_BASE
- str r2, [r0, #RB_CLK_DIV_T1]
+ ldr r0, =MARIA_REGBANK_BASE
+ str r2, [r0, #RB_CLK_DIV_T1_OFFSET]
mov pc, lr /* back to my caller */
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/wdt.c b/cleopatre/u-boot-1.1.6/cpu/spc300/wdt.c
index 75b5ee63cc..afaf83691a 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/wdt.c
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/wdt.c
@@ -22,7 +22,7 @@
#include <common.h>
#include <config.h>
#include <asm/arch/hardware.h>
-#include <asm/arch/wdt.h>
+#include <asm/arch/ips/wdt.h>
#include <asm/arch/nvram.h>
/**
diff --git a/cleopatre/u-boot-1.1.6/drivers/netspcmac_eth.c b/cleopatre/u-boot-1.1.6/drivers/netspcmac_eth.c
index 0ed9a99003..0fc8162768 100644
--- a/cleopatre/u-boot-1.1.6/drivers/netspcmac_eth.c
+++ b/cleopatre/u-boot-1.1.6/drivers/netspcmac_eth.c
@@ -35,7 +35,7 @@
#ifdef CONFIG_ARCH_SPC300
#include <asm/arch/nvram.h>
-#include <asm/arch/pkg_maria_regbank.h>
+#include <asm/arch/ips/hardware/pkg_maria_regbank.h>
#endif
#ifdef CONFIG_ARCH_ARIZONA
@@ -666,9 +666,6 @@ static void spcmac_set_rx_mode (void)
#endif
#ifdef CONFIG_ARCH_SPC300
-#define SPCRB_READ(REG) readl(MARIA_REGBANK_BASE+(REG))
-#define SPCRB_WRITE(V, REG) writel(V, MARIA_REGBANK_BASE+(REG))
-
static void spcmac_set_rb_mii_cap (unsigned int speed)
{
unsigned int timeout;
@@ -683,27 +680,27 @@ static void spcmac_set_rb_mii_cap (unsigned int speed)
if(speed == 1000)
{
/* 1G was negotiate switch to GMII mode */
- SPCRB_WRITE(CLK_IS_OFF, RB_CLK_CMD_ETH_TX_EXT);
- for(timeout=0xF ; (SPCRB_READ(RB_CLK_STAT_ETH_TX_EXT) != CLK_IS_OFF) && timeout ; timeout--);
- SPCRB_WRITE(CLK_SEL_ETH_TX_125, RB_CLK_SEL_ETH_TX);
- SPCRB_WRITE(CLK_IS_ON, RB_CLK_CMD_ETH_TX_125);
- for(timeout=0xF ; (SPCRB_READ(RB_CLK_STAT_ETH_TX_125) != CLK_IS_ON) && timeout ; timeout--);
+ writel(CLK_IS_OFF, RB_CLK_CMD_ETH_TX_EXT);
+ for(timeout=0xF ; (readl(RB_CLK_STAT_ETH_TX_EXT) != CLK_IS_OFF) && timeout ; timeout--);
+ writel(CLK_SEL_ETH_TX_125, RB_CLK_SEL_ETH_TX);
+ writel(CLK_IS_ON, RB_CLK_CMD_ETH_TX_125);
+ for(timeout=0xF ; (readl(RB_CLK_STAT_ETH_TX_125) != CLK_IS_ON) && timeout ; timeout--);
}
else
{
/* 1G wasn't negotiate swith to MII mode */
- SPCRB_WRITE(CLK_IS_OFF, RB_CLK_CMD_ETH_TX_125);
- for(timeout=0xF ; (SPCRB_READ(RB_CLK_STAT_ETH_TX_125) != CLK_IS_OFF) && timeout ; timeout--);
- SPCRB_WRITE(CLK_SEL_ETH_TX_EXT, RB_CLK_SEL_ETH_TX);
- SPCRB_WRITE(CLK_IS_ON, RB_CLK_CMD_ETH_TX_EXT);
- for(timeout=0xF ; (SPCRB_READ(RB_CLK_STAT_ETH_TX_EXT) != CLK_IS_ON) && timeout ; timeout--);
+ writel(CLK_IS_OFF, RB_CLK_CMD_ETH_TX_125);
+ for(timeout=0xF ; (readl(RB_CLK_STAT_ETH_TX_125) != CLK_IS_OFF) && timeout ; timeout--);
+ writel(CLK_SEL_ETH_TX_EXT, RB_CLK_SEL_ETH_TX);
+ writel(CLK_IS_ON, RB_CLK_CMD_ETH_TX_EXT);
+ for(timeout=0xF ; (readl(RB_CLK_STAT_ETH_TX_EXT) != CLK_IS_ON) && timeout ; timeout--);
}
}
if(mode == NVRAM_ETH_MODE_RMII) /* RMII */
{
- eth_cfg = (unsigned int) SPCRB_READ(RB_ETH_CONFIG);
- rmii_clk = (unsigned int) SPCRB_READ(RB_CLK_DIV_STAT_ETH_25);
+ eth_cfg = (unsigned int) readl(RB_ETH_CONFIG);
+ rmii_clk = (unsigned int) readl(RB_CLK_DIV_STAT_ETH_25);
if(speed == 10)
{
eth_cfg &= ~ETH_CFG_RMII_100;
@@ -714,8 +711,8 @@ static void spcmac_set_rb_mii_cap (unsigned int speed)
eth_cfg |= ETH_CFG_RMII_100;
rmii_clk |= CLK_DIV_ETH_25_2;
}
- SPCRB_WRITE(eth_cfg, RB_ETH_CONFIG);
- SPCRB_WRITE(rmii_clk, RB_CLK_DIV_ETH_25);
+ writel(eth_cfg, RB_ETH_CONFIG);
+ writel(rmii_clk, RB_CLK_DIV_ETH_25);
}
}
#endif
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/.gitignore b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/.gitignore
new file mode 100644
index 0000000000..4119d58772
--- /dev/null
+++ b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/.gitignore
@@ -0,0 +1,32 @@
+ips/arizona.h
+ips/gic.h
+ips/gpio.h
+ips/ips_access.h
+ips/regbank.h
+ips/spi.h
+ips/timer.h
+ips/uart.h
+ips/wdt.h
+
+ips/hardware/arm_apb.h
+ips/hardware/arm_gpio.h
+ips/hardware/arm_ictl.h
+ips/hardware/arm_timer1.h
+ips/hardware/arm_timer2.h
+ips/hardware/arm_uart1.h
+ips/hardware/arm_uart2.h
+ips/hardware/arm_wdt.h
+ips/hardware/boot_arm_hard.h
+ips/hardware/bus_sys.h
+ips/hardware/dsp.h
+ips/hardware/ethernet_ctrl.h
+ips/hardware/gpdma.h
+ips/hardware/i2s.h
+ips/hardware/miu.h
+ips/hardware/mpeg_ts.h
+ips/hardware/pcm.h
+ips/hardware/pkg_maria_regbank.h
+ips/hardware/sdram.h
+ips/hardware/spi.h
+ips/hardware/sys_apb.h
+
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_apb.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_apb.h
deleted file mode 100644
index 8698a0e185..0000000000
--- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_apb.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * include/asm-arm/arch-spc300/arm_apb.h
- *
- * Copyright (C) 2009 SPiDCOM Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_ARM_APB_H
-#define __ASM_ARCH_ARM_APB_H
-
-
-#ifndef ARM_APB_BASE
- #error "ARM_APB_BASE macro needs to be defined before including file arm_apb.h"
-#endif
-
-#define ARM_TIMER1_BASE (ARM_APB_BASE+0)
-#include "arm_timer1.h"
-
-#define ARM_TIMER2_BASE (ARM_APB_BASE+0x10000)
-#include "arm_timer2.h"
-
-#define ARM_WDT_BASE (ARM_APB_BASE+0x20000)
-#include "arm_wdt.h"
-
-#define ARM_ICTL_BASE (ARM_APB_BASE+0x30000)
-#include "arm_ictl.h"
-
-#define ARM_UART1_BASE (ARM_APB_BASE+0x40000)
-#include "arm_uart1.h"
-
-#define ARM_UART2_BASE (ARM_APB_BASE+0x50000)
-#include "arm_uart2.h"
-
-#define ARM_GPIO_BASE (ARM_APB_BASE+0x60000)
-#include "arm_gpio.h"
-
-#endif /* __ASM_ARCH_ARM_APB_H */
-
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_gpio.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_gpio.h
deleted file mode 100644
index 6270c3ae17..0000000000
--- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_gpio.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * include/asm-arm/arch-spc300/arm_gpio.h
- *
- * Copyright (C) 2009 SPiDCOM Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_ARM_GPIO_H
-#define __ASM_ARCH_ARM_GPIO_H
-
-#ifndef ARM_GPIO_BASE
- #error "ARM_GPIO_BASE macro needs to be defined before including file arm_gpio.h"
-#endif
-
-#define GPIO_SWPORTA_DR_OFFSET 0x00
-#define GPIO_SWPORTA_DDR_OFFSET 0x04
-#define GPIO_SWPORTA_CTL_OFFSET 0x08
-#define GPIO_SWPORTB_DR_OFFSET 0x0C
-#define GPIO_SWPORTB_DDR_OFFSET 0x10
-#define GPIO_SWPORTB_CTL_OFFSET 0x14
-#define GPIO_SWPORTC_DR_OFFSET 0x18
-#define GPIO_SWPORTC_DDR_OFFSET 0x1C
-#define GPIO_SWPORTC_CTL_OFFSET 0x20
-#define GPIO_SWPORTD_DR_OFFSET 0x24
-#define GPIO_SWPORTD_DDR_OFFSET 0x28
-#define GPIO_SWPORTD_CTL_OFFSET 0x2C
-#define GPIO_INTEN_OFFSET 0x30
-#define GPIO_INTMASK_OFFSET 0x34
-#define GPIO_INTTYPE_LEVEL_OFFSET 0x38
-#define GPIO_INT_POLARITY_OFFSET 0x3C
-#define GPIO_INTSTATUS_OFFSET 0x40
-#define GPIO_RAW_INTSTATUS_OFFSET 0x44
-#define GPIO_DEBOUNCE_OFFSET 0x48
-#define GPIO_PORTA_EOI_OFFSET 0x4C
-#define GPIO_EXT_PORTA_OFFSET 0x50
-#define GPIO_EXT_PORTB_OFFSET 0x54
-#define GPIO_EXT_PORTC_OFFSET 0x58
-#define GPIO_EXT_PORTD_OFFSET 0x5C
-#define GPIO_LS_SYNC_OFFSET 0x60
-#define GPIO_ID_CODE_OFFSET 0x64
-#define GPIO_VER_ID_CODE_OFFSET 0x6C
-
-#define GPIO_CONFIGID_REG2_OFFSET 0x70
-
-#define GPIO_CONFIGID_REG1_OFFSET 0x74
-
-#define GPIO_SWPORTA_DR (ARM_GPIO_BASE + GPIO_SWPORTA_DR_OFFSET)
-#define GPIO_SWPORTA_DDR (ARM_GPIO_BASE + GPIO_SWPORTA_DDR_OFFSET)
-#define GPIO_SWPORTA_CTL (ARM_GPIO_BASE + GPIO_SWPORTA_CTL_OFFSET)
-#define GPIO_SWPORTB_DR (ARM_GPIO_BASE + GPIO_SWPORTB_DR_OFFSET)
-#define GPIO_SWPORTB_DDR (ARM_GPIO_BASE + GPIO_SWPORTB_DDR_OFFSET)
-#define GPIO_SWPORTB_CTL (ARM_GPIO_BASE + GPIO_SWPORTB_CTL_OFFSET)
-#define GPIO_SWPORTC_DR (ARM_GPIO_BASE + GPIO_SWPORTC_DR_OFFSET)
-#define GPIO_SWPORTC_DDR (ARM_GPIO_BASE + GPIO_SWPORTC_DDR_OFFSET)
-#define GPIO_SWPORTC_CTL (ARM_GPIO_BASE + GPIO_SWPORTC_CTL_OFFSET)
-#define GPIO_SWPORTD_DR (ARM_GPIO_BASE + GPIO_SWPORTD_DR_OFFSET)
-#define GPIO_SWPORTD_DDR (ARM_GPIO_BASE + GPIO_SWPORTD_DDR_OFFSET)
-#define GPIO_SWPORTD_CTL (ARM_GPIO_BASE + GPIO_SWPORTD_CTL_OFFSET)
-#define GPIO_INTEN (ARM_GPIO_BASE + GPIO_INTEN_OFFSET)
-#define GPIO_INTMASK (ARM_GPIO_BASE + GPIO_INTMASK_OFFSET)
-#define GPIO_INTTYPE_LEVEL (ARM_GPIO_BASE + GPIO_INTTYPE_LEVEL_OFFSET)
-#define GPIO_INT_POLARITY (ARM_GPIO_BASE + GPIO_INT_POLARITY_OFFSET)
-#define GPIO_INTSTATUS (ARM_GPIO_BASE + GPIO_INTSTATUS_OFFSET)
-#define GPIO_RAW_INTSTATUS (ARM_GPIO_BASE + GPIO_RAW_INTSTATUS_OFFSET)
-#define GPIO_DEBOUNCE (ARM_GPIO_BASE + GPIO_DEBOUNCE_OFFSET)
-#define GPIO_PORTA_EOI (ARM_GPIO_BASE + GPIO_PORTA_EOI_OFFSET)
-#define GPIO_EXT_PORTA (ARM_GPIO_BASE + GPIO_EXT_PORTA_OFFSET)
-#define GPIO_EXT_PORTB (ARM_GPIO_BASE + GPIO_EXT_PORTB_OFFSET)
-#define GPIO_EXT_PORTC (ARM_GPIO_BASE + GPIO_EXT_PORTC_OFFSET)
-#define GPIO_EXT_PORTD (ARM_GPIO_BASE + GPIO_EXT_PORTD_OFFSET)
-#define GPIO_LS_SYNC (ARM_GPIO_BASE + GPIO_LS_SYNC_OFFSET)
-#define GPIO_ID_CODE (ARM_GPIO_BASE + GPIO_ID_CODE_OFFSET)
-#define GPIO_VER_ID_CODE (ARM_GPIO_BASE + GPIO_VER_ID_CODE_OFFSET)
-
-#define GPIO_CONFIGID_REG2 (ARM_GPIO_BASE + GPIO_CONFIGID_REG2_OFFSET)
-
-#define GPIO_CONFIGID_REG1 (ARM_GPIO_BASE + GPIO_CONFIGID_REG1_OFFSET)
-
-#define GPIOPING_1BIT_WR (GPIO_SWPORTA_DR)
-
-#define CC_GPIO_ADD_ENCODED_PARAM 0x1
-#define CC_GPIO_APB_DATA_WIDTH 32
-#define CC_GPIO_NUM_PORTS 1
-#define CC_GPIO_ID 0
-#define CC_GPIO_DEBOUNCE 1
-#define CC_GPIO_ID_WIDTH 32
-#define CC_GPIO_ID_NUM 0x0
-#define CC_GPIO_REV_ID 0
-#define CC_GPIO_REV_ID_WIDTH 32
-#define CC_GPIO_REV_ID_NUM 0x0
-#define CC_GPIO_PWIDTH_A 16
-#define CC_GPIO_PORTA_SINGLE_CTL 1
-#define CC_GPIO_SWPORTA_RESET 0x0
-#define CC_GPIO_HW_PORTA 0
-#define CC_GPIO_DFLT_DIR_A 0
-#define CC_GPIO_DFLT_SRC_A 0
-#define CC_GPIO_PORTA_INTR 1
-#define CC_GPIO_INT_POL 1
-#define CC_GPIO_INTR_IO 1
-#define CC_GPIO_PA_SYNC_EXT_DATA 1
-#define CC_GPIO_PA_SYNC_INTERRUPTS 1
-#define CC_GPIO_PWIDTH_B 8
-#define CC_GPIO_PORTB_SINGLE_CTL 1
-#define CC_GPIO_SWPORTB_RESET 0x0
-#define CC_GPIO_HW_PORTB 0
-#define CC_GPIO_DFLT_DIR_B 0
-#define CC_GPIO_DFLT_SRC_B 0
-#define CC_GPIO_PB_SYNC_EXT_DATA 0
-#define CC_GPIO_PWIDTH_C 8
-#define CC_GPIO_PORTC_SINGLE_CTL 1
-#define CC_GPIO_SWPORTC_RESET 0x0
-#define CC_GPIO_HW_PORTC 0
-#define CC_GPIO_DFLT_DIR_C 0
-#define CC_GPIO_DFLT_SRC_C 0
-#define CC_GPIO_PC_SYNC_EXT_DATA 0
-#define CC_GPIO_PWIDTH_D 8
-#define CC_GPIO_PORTD_SINGLE_CTL 1
-#define CC_GPIO_SWPORTD_RESET 0x0
-#define CC_GPIO_HW_PORTD 0
-#define CC_GPIO_DFLT_DIR_D 0
-#define CC_GPIO_DFLT_SRC_D 0
-#define CC_GPIO_PD_SYNC_EXT_DATA 0
-
-#endif /* __ASM_ARCH_ARM_GPIO_H */
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_ictl.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_ictl.h
deleted file mode 100644
index 570f7a1969..0000000000
--- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_ictl.h
+++ /dev/null
@@ -1,588 +0,0 @@
-/*
- * include/asm-arm/arch-spc300/arm_ictl.h
- *
- * Copyright (C) 2009 SPiDCOM Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_ARM_ICTL_H
-#define __ASM_ARCH_ARM_ICTL_H
-
-#ifndef ARM_ICTL_BASE
- #error "ARM_ICTL_BASE macro needs to be defined before including file arm_ictl.h"
-#endif
-
-
-#define IRQ_INTEN_OFFSET 0x000
-#define IRQ_INTEN_OFFSET_L 0x000
-#define IRQ_INTEN_OFFSET_H 0x004
-#define IRQ_INTMASK_OFFSET 0x008
-#define IRQ_INTMASK_OFFSET_L 0x008
-#define IRQ_INTMASK_OFFSET_H 0x00c
-#define IRQ_INTFORCE_OFFSET 0x010
-#define IRQ_INTFORCE_OFFSET_L 0x010
-#define IRQ_INTFORCE_OFFSET_H 0x014
-#define IRQ_RAWSTATUS_OFFSET 0x018
-#define IRQ_RAWSTATUS_OFFSET_L 0x018
-#define IRQ_RAWSTATUS_OFFSET_H 0x01c
-#define IRQ_STATUS_OFFSET 0x020
-#define IRQ_STATUS_OFFSET_L 0x020
-#define IRQ_STATUS_OFFSET_H 0x024
-#define IRQ_MASKSTATUS_OFFSET 0x028
-#define IRQ_MASKSTATUS_OFFSET_L 0x028
-#define IRQ_MASKSTATUS_OFFSET_H 0x02c
-#define IRQ_FINALSTATUS_OFFSET 0x030
-#define IRQ_FINALSTATUS_OFFSET_L 0x030
-#define IRQ_FINALSTATUS_OFFSET_H 0x034
-#define IRQ_VECTOR_OFFSET 0x038
-#define IRQ_VECTOR_OFFSET_L 0x038
-#define IRQ_VECTOR_OFFSET_H 0x03c
-#define IRQ_VECTOR_OFFSET_0 0x040
-#define IRQ_VECTOR_OFFSET_0_L 0x040
-#define IRQ_VECTOR_OFFSET_0_H 0x044
-#define IRQ_VECTOR_OFFSET_1 0x048
-#define IRQ_VECTOR_OFFSET_1_L 0x048
-#define IRQ_VECTOR_OFFSET_1_H 0x04c
-#define IRQ_VECTOR_OFFSET_2 0x050
-#define IRQ_VECTOR_OFFSET_2_L 0x050
-#define IRQ_VECTOR_OFFSET_2_H 0x054
-#define IRQ_VECTOR_OFFSET_3 0x058
-#define IRQ_VECTOR_OFFSET_3_L 0x058
-#define IRQ_VECTOR_OFFSET_3_H 0x05c
-#define IRQ_VECTOR_OFFSET_4 0x060
-#define IRQ_VECTOR_OFFSET_4_L 0x060
-#define IRQ_VECTOR_OFFSET_4_H 0x064
-#define IRQ_VECTOR_OFFSET_5 0x068
-#define IRQ_VECTOR_OFFSET_5_L 0x068
-#define IRQ_VECTOR_OFFSET_5_H 0x06c
-#define IRQ_VECTOR_OFFSET_6 0x070
-#define IRQ_VECTOR_OFFSET_6_L 0x070
-#define IRQ_VECTOR_OFFSET_6_H 0x074
-#define IRQ_VECTOR_OFFSET_7 0x078
-#define IRQ_VECTOR_OFFSET_7_L 0x078
-#define IRQ_VECTOR_OFFSET_7_H 0x07c
-#define IRQ_VECTOR_OFFSET_8 0x080
-#define IRQ_VECTOR_OFFSET_8_L 0x080
-#define IRQ_VECTOR_OFFSET_8_H 0x084
-#define IRQ_VECTOR_OFFSET_9 0x088
-#define IRQ_VECTOR_OFFSET_9_L 0x088
-#define IRQ_VECTOR_OFFSET_9_H 0x08c
-#define IRQ_VECTOR_OFFSET_10 0x090
-#define IRQ_VECTOR_OFFSET_10_L 0x090
-#define IRQ_VECTOR_OFFSET_10_H 0x094
-#define IRQ_VECTOR_OFFSET_11 0x098
-#define IRQ_VECTOR_OFFSET_11_L 0x098
-#define IRQ_VECTOR_OFFSET_11_H 0x09c
-#define IRQ_VECTOR_OFFSET_12 0x0a0
-#define IRQ_VECTOR_OFFSET_12_L 0x0a0
-#define IRQ_VECTOR_OFFSET_12_H 0x0a4
-#define IRQ_VECTOR_OFFSET_13 0x0a8
-#define IRQ_VECTOR_OFFSET_13_L 0x0a8
-#define IRQ_VECTOR_OFFSET_13_H 0x0ac
-#define IRQ_VECTOR_OFFSET_14 0x0b0
-#define IRQ_VECTOR_OFFSET_14_L 0x0b0
-#define IRQ_VECTOR_OFFSET_14_H 0x0b4
-#define IRQ_VECTOR_OFFSET_15 0x0b8
-#define IRQ_VECTOR_OFFSET_15_L 0x0b8
-#define IRQ_VECTOR_OFFSET_15_H 0x0bc
-#define FIQ_INTEN_OFFSET 0x0c0
-#define FIQ_INTMASK_OFFSET 0x0c4
-#define FIQ_INTFORCE_OFFSET 0x0c8
-#define FIQ_RAWSTATUS_OFFSET 0x0cc
-#define FIQ_STATUS_OFFSET 0x0d0
-#define FIQ_FINALSTATUS_OFFSET 0x0d4
-#define IRQ_PLEVEL_OFFSET 0x0d8
-#define ICTL_VERSION_ID_OFFSET 0x0e0
-#define IRQ_P0_OFFSET 0x0e8
-#define IRQ_P1_OFFSET 0x0ec
-#define IRQ_P2_OFFSET 0x0f0
-#define IRQ_P3_OFFSET 0x0f4
-#define IRQ_P4_OFFSET 0x0f8
-#define IRQ_P5_OFFSET 0x0fc
-#define IRQ_P6_OFFSET 0x100
-#define IRQ_P7_OFFSET 0x104
-#define IRQ_P8_OFFSET 0x108
-#define IRQ_P9_OFFSET 0x10c
-#define IRQ_P10_OFFSET 0x110
-#define IRQ_P11_OFFSET 0x114
-#define IRQ_P12_OFFSET 0x118
-#define IRQ_P13_OFFSET 0x11c
-#define IRQ_P14_OFFSET 0x120
-#define IRQ_P15_OFFSET 0x124
-#define IRQ_P16_OFFSET 0x128
-#define IRQ_P17_OFFSET 0x12c
-#define IRQ_P18_OFFSET 0x130
-#define IRQ_P19_OFFSET 0x134
-#define IRQ_P20_OFFSET 0x138
-#define IRQ_P21_OFFSET 0x13c
-#define IRQ_P22_OFFSET 0x140
-#define IRQ_P23_OFFSET 0x144
-#define IRQ_P24_OFFSET 0x148
-#define IRQ_P25_OFFSET 0x14c
-#define IRQ_P26_OFFSET 0x150
-#define IRQ_P27_OFFSET 0x154
-#define IRQ_P28_OFFSET 0x158
-#define IRQ_P29_OFFSET 0x15c
-#define IRQ_P30_OFFSET 0x160
-#define IRQ_P31_OFFSET 0x164
-#define IRQ_P32_OFFSET 0x168
-#define IRQ_P33_OFFSET 0x16c
-#define IRQ_P34_OFFSET 0x170
-#define IRQ_P35_OFFSET 0x174
-#define IRQ_P36_OFFSET 0x178
-#define IRQ_P37_OFFSET 0x17c
-#define IRQ_P38_OFFSET 0x180
-#define IRQ_P39_OFFSET 0x184
-#define IRQ_P40_OFFSET 0x188
-#define IRQ_P41_OFFSET 0x18c
-#define IRQ_P42_OFFSET 0x190
-#define IRQ_P43_OFFSET 0x194
-#define IRQ_P44_OFFSET 0x198
-#define IRQ_P45_OFFSET 0x19c
-#define IRQ_P46_OFFSET 0x1a0
-#define IRQ_P47_OFFSET 0x1a4
-#define IRQ_P48_OFFSET 0x1a8
-#define IRQ_P49_OFFSET 0x1ac
-#define IRQ_P50_OFFSET 0x1b0
-#define IRQ_P51_OFFSET 0x1b4
-#define IRQ_P52_OFFSET 0x1b8
-#define IRQ_P53_OFFSET 0x1bc
-#define IRQ_P54_OFFSET 0x1c0
-#define IRQ_P55_OFFSET 0x1c4
-#define IRQ_P56_OFFSET 0x1c8
-#define IRQ_P57_OFFSET 0x1cc
-#define IRQ_P58_OFFSET 0x1d0
-#define IRQ_P59_OFFSET 0x1d4
-#define IRQ_P60_OFFSET 0x1d8
-#define IRQ_P61_OFFSET 0x1dc
-#define IRQ_P62_OFFSET 0x1e0
-#define IRQ_P63_OFFSET 0x1e4
-
-#define IRQ_PLEVEL_WIDTH 4
-#define ICTL_VERSION_ID_WIDTH 32
-
-//#ifdef QUICKSTART_APB_ICTL
-#define IRQ_INTEN (ARM_ICTL_BASE + IRQ_INTEN_OFFSET)
-#define IRQ_INTEN_L (ARM_ICTL_BASE + IRQ_INTEN_OFFSET_L)
-#define IRQ_INTEN_H (ARM_ICTL_BASE + IRQ_INTEN_OFFSET_H)
-#define IRQ_INTMASK (ARM_ICTL_BASE + IRQ_INTMASK_OFFSET)
-#define IRQ_INTMASK_L (ARM_ICTL_BASE + IRQ_INTMASK_OFFSET_L)
-#define IRQ_INTMASK_H (ARM_ICTL_BASE + IRQ_INTMASK_OFFSET_H)
-#define IRQ_INTFORCE (ARM_ICTL_BASE + IRQ_INTFORCE_OFFSET)
-#define IRQ_INTFORCE_L (ARM_ICTL_BASE + IRQ_INTFORCE_OFFSET_L)
-#define IRQ_INTFORCE_H (ARM_ICTL_BASE + IRQ_INTFORCE_OFFSET_H)
-#define IRQ_RAWSTATUS (ARM_ICTL_BASE + IRQ_RAWSTATUS_OFFSET)
-#define IRQ_RAWSTATUS_L (ARM_ICTL_BASE + IRQ_RAWSTATUS_OFFSET_L)
-#define IRQ_RAWSTATUS_H (ARM_ICTL_BASE + IRQ_RAWSTATUS_OFFSET_H)
-#define IRQ_STATUS (ARM_ICTL_BASE + IRQ_STATUS_OFFSET)
-#define IRQ_STATUS_L (ARM_ICTL_BASE + IRQ_STATUS_OFFSET_L)
-#define IRQ_STATUS_H (ARM_ICTL_BASE + IRQ_STATUS_OFFSET_H)
-#define IRQ_MASKSTATUS (ARM_ICTL_BASE + IRQ_MASKSTATUS_OFFSET)
-#define IRQ_MASKSTATUS_L (ARM_ICTL_BASE + IRQ_MASKSTATUS_OFFSET_L)
-#define IRQ_MASKSTATUS_H (ARM_ICTL_BASE + IRQ_MASKSTATUS_OFFSET_H)
-#define IRQ_FINALSTATUS (ARM_ICTL_BASE + IRQ_FINALSTATUS_OFFSET)
-#define IRQ_FINALSTATUS_L (ARM_ICTL_BASE + IRQ_FINALSTATUS_OFFSET_L)
-#define IRQ_FINALSTATUS_H (ARM_ICTL_BASE + IRQ_FINALSTATUS_OFFSET_H)
-#define IRQ_VECTOR (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET)
-#define IRQ_VECTOR_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_L)
-#define IRQ_VECTOR_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_H)
-#define IRQ_VECTOR_0 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_0)
-#define IRQ_VECTOR_0_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_0_L)
-#define IRQ_VECTOR_0_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_0_H)
-#define IRQ_VECTOR_1 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_1)
-#define IRQ_VECTOR_1_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_1_L)
-#define IRQ_VECTOR_1_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_1_H)
-#define IRQ_VECTOR_2 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_2)
-#define IRQ_VECTOR_2_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_2_L)
-#define IRQ_VECTOR_2_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_2_H)
-#define IRQ_VECTOR_3 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_3)
-#define IRQ_VECTOR_3_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_3_L)
-#define IRQ_VECTOR_3_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_3_H)
-#define IRQ_VECTOR_4 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_4)
-#define IRQ_VECTOR_4_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_4_L)
-#define IRQ_VECTOR_4_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_4_H)
-#define IRQ_VECTOR_5 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_5)
-#define IRQ_VECTOR_5_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_5_L)
-#define IRQ_VECTOR_5_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_5_H)
-#define IRQ_VECTOR_6 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_6)
-#define IRQ_VECTOR_6_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_6_L)
-#define IRQ_VECTOR_6_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_6_H)
-#define IRQ_VECTOR_7 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_7)
-#define IRQ_VECTOR_7_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_7_L)
-#define IRQ_VECTOR_7_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_7_H)
-#define IRQ_VECTOR_8 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_8)
-#define IRQ_VECTOR_8_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_8_L)
-#define IRQ_VECTOR_8_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_8_H)
-#define IRQ_VECTOR_9 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_9)
-#define IRQ_VECTOR_9_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_9_L)
-#define IRQ_VECTOR_9_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_9_H)
-#define IRQ_VECTOR_10 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_10)
-#define IRQ_VECTOR_10_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_10_L)
-#define IRQ_VECTOR_10_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_10_H)
-#define IRQ_VECTOR_11 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_11)
-#define IRQ_VECTOR_11_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_11_L)
-#define IRQ_VECTOR_11_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_11_H)
-#define IRQ_VECTOR_12 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_12)
-#define IRQ_VECTOR_12_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_12_L)
-#define IRQ_VECTOR_12_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_12_H)
-#define IRQ_VECTOR_13 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_13)
-#define IRQ_VECTOR_13_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_13_L)
-#define IRQ_VECTOR_13_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_13_H)
-#define IRQ_VECTOR_14 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_14)
-#define IRQ_VECTOR_14_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_14_L)
-#define IRQ_VECTOR_14_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_14_H)
-#define IRQ_VECTOR_15 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_15)
-#define IRQ_VECTOR_15_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_15_L)
-#define IRQ_VECTOR_15_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_15_H)
-#define FIQ_INTEN (ARM_ICTL_BASE + FIQ_INTEN_OFFSET)
-#define FIQ_INTMASK (ARM_ICTL_BASE + FIQ_INTMASK_OFFSET)
-#define FIQ_INTFORCE (ARM_ICTL_BASE + FIQ_INTFORCE_OFFSET)
-#define FIQ_RAWSTATUS (ARM_ICTL_BASE + FIQ_RAWSTATUS_OFFSET)
-#define FIQ_STATUS (ARM_ICTL_BASE + FIQ_STATUS_OFFSET)
-#define FIQ_FINALSTATUS (ARM_ICTL_BASE + FIQ_FINALSTATUS_OFFSET)
-#define IRQ_PLEVEL (ARM_ICTL_BASE + IRQ_PLEVEL_OFFSET)
-#define ICTL_VERSION_ID (ARM_ICTL_BASE + ICTL_VERSION_ID_OFFSET)
-#define IRQ_P0_ADDR (ARM_ICTL_BASE + IRQ_P0_OFFSET)
-#define IRQ_P1_ADDR (ARM_ICTL_BASE + IRQ_P1_OFFSET)
-#define IRQ_P2_ADDR (ARM_ICTL_BASE + IRQ_P2_OFFSET)
-#define IRQ_P3_ADDR (ARM_ICTL_BASE + IRQ_P3_OFFSET)
-#define IRQ_P4_ADDR (ARM_ICTL_BASE + IRQ_P4_OFFSET)
-#define IRQ_P5_ADDR (ARM_ICTL_BASE + IRQ_P5_OFFSET)
-#define IRQ_P6_ADDR (ARM_ICTL_BASE + IRQ_P6_OFFSET)
-#define IRQ_P7_ADDR (ARM_ICTL_BASE + IRQ_P7_OFFSET)
-#define IRQ_P8_ADDR (ARM_ICTL_BASE + IRQ_P8_OFFSET)
-#define IRQ_P9_ADDR (ARM_ICTL_BASE + IRQ_P9_OFFSET)
-#define IRQ_P10_ADDR (ARM_ICTL_BASE + IRQ_P10_OFFSET)
-#define IRQ_P11_ADDR (ARM_ICTL_BASE + IRQ_P11_OFFSET)
-#define IRQ_P12_ADDR (ARM_ICTL_BASE + IRQ_P12_OFFSET)
-#define IRQ_P13_ADDR (ARM_ICTL_BASE + IRQ_P13_OFFSET)
-#define IRQ_P14_ADDR (ARM_ICTL_BASE + IRQ_P14_OFFSET)
-#define IRQ_P15_ADDR (ARM_ICTL_BASE + IRQ_P15_OFFSET)
-#define IRQ_P16_ADDR (ARM_ICTL_BASE + IRQ_P16_OFFSET)
-#define IRQ_P17_ADDR (ARM_ICTL_BASE + IRQ_P17_OFFSET)
-#define IRQ_P18_ADDR (ARM_ICTL_BASE + IRQ_P18_OFFSET)
-#define IRQ_P19_ADDR (ARM_ICTL_BASE + IRQ_P19_OFFSET)
-#define IRQ_P20_ADDR (ARM_ICTL_BASE + IRQ_P20_OFFSET)
-#define IRQ_P21_ADDR (ARM_ICTL_BASE + IRQ_P21_OFFSET)
-#define IRQ_P22_ADDR (ARM_ICTL_BASE + IRQ_P22_OFFSET)
-#define IRQ_P23_ADDR (ARM_ICTL_BASE + IRQ_P23_OFFSET)
-#define IRQ_P24_ADDR (ARM_ICTL_BASE + IRQ_P24_OFFSET)
-#define IRQ_P25_ADDR (ARM_ICTL_BASE + IRQ_P25_OFFSET)
-#define IRQ_P26_ADDR (ARM_ICTL_BASE + IRQ_P26_OFFSET)
-#define IRQ_P27_ADDR (ARM_ICTL_BASE + IRQ_P27_OFFSET)
-#define IRQ_P28_ADDR (ARM_ICTL_BASE + IRQ_P28_OFFSET)
-#define IRQ_P29_ADDR (ARM_ICTL_BASE + IRQ_P29_OFFSET)
-#define IRQ_P29_ADDR (ARM_ICTL_BASE + IRQ_P29_OFFSET)
-#define IRQ_P30_ADDR (ARM_ICTL_BASE + IRQ_P30_OFFSET)
-#define IRQ_P31_ADDR (ARM_ICTL_BASE + IRQ_P31_OFFSET)
-#define IRQ_P32_ADDR (ARM_ICTL_BASE + IRQ_P32_OFFSET)
-#define IRQ_P33_ADDR (ARM_ICTL_BASE + IRQ_P33_OFFSET)
-#define IRQ_P34_ADDR (ARM_ICTL_BASE + IRQ_P34_OFFSET)
-#define IRQ_P35_ADDR (ARM_ICTL_BASE + IRQ_P35_OFFSET)
-#define IRQ_P36_ADDR (ARM_ICTL_BASE + IRQ_P36_OFFSET)
-#define IRQ_P37_ADDR (ARM_ICTL_BASE + IRQ_P37_OFFSET)
-#define IRQ_P38_ADDR (ARM_ICTL_BASE + IRQ_P38_OFFSET)
-#define IRQ_P39_ADDR (ARM_ICTL_BASE + IRQ_P39_OFFSET)
-#define IRQ_P40_ADDR (ARM_ICTL_BASE + IRQ_P40_OFFSET)
-#define IRQ_P41_ADDR (ARM_ICTL_BASE + IRQ_P41_OFFSET)
-#define IRQ_P42_ADDR (ARM_ICTL_BASE + IRQ_P42_OFFSET)
-#define IRQ_P43_ADDR (ARM_ICTL_BASE + IRQ_P43_OFFSET)
-#define IRQ_P44_ADDR (ARM_ICTL_BASE + IRQ_P44_OFFSET)
-#define IRQ_P45_ADDR (ARM_ICTL_BASE + IRQ_P45_OFFSET)
-#define IRQ_P46_ADDR (ARM_ICTL_BASE + IRQ_P46_OFFSET)
-#define IRQ_P47_ADDR (ARM_ICTL_BASE + IRQ_P47_OFFSET)
-#define IRQ_P48_ADDR (ARM_ICTL_BASE + IRQ_P48_OFFSET)
-#define IRQ_P49_ADDR (ARM_ICTL_BASE + IRQ_P49_OFFSET)
-#define IRQ_P50_ADDR (ARM_ICTL_BASE + IRQ_P50_OFFSET)
-#define IRQ_P51_ADDR (ARM_ICTL_BASE + IRQ_P51_OFFSET)
-#define IRQ_P52_ADDR (ARM_ICTL_BASE + IRQ_P52_OFFSET)
-#define IRQ_P53_ADDR (ARM_ICTL_BASE + IRQ_P53_OFFSET)
-#define IRQ_P54_ADDR (ARM_ICTL_BASE + IRQ_P54_OFFSET)
-#define IRQ_P55_ADDR (ARM_ICTL_BASE + IRQ_P55_OFFSET)
-#define IRQ_P56_ADDR (ARM_ICTL_BASE + IRQ_P56_OFFSET)
-#define IRQ_P57_ADDR (ARM_ICTL_BASE + IRQ_P57_OFFSET)
-#define IRQ_P58_ADDR (ARM_ICTL_BASE + IRQ_P58_OFFSET)
-#define IRQ_P59_ADDR (ARM_ICTL_BASE + IRQ_P59_OFFSET)
-#define IRQ_P60_ADDR (ARM_ICTL_BASE + IRQ_P60_OFFSET)
-#define IRQ_P61_ADDR (ARM_ICTL_BASE + IRQ_P61_OFFSET)
-#define IRQ_P62_ADDR (ARM_ICTL_BASE + IRQ_P62_OFFSET)
-#define IRQ_P63_ADDR (ARM_ICTL_BASE + IRQ_P63_OFFSET)
-//#endif
-
-#define APB_ICT_IRQ_INTEN (ARM_ICTL_BASE + IRQ_INTEN_OFFSET)
-#define APB_ICT_IRQ_INTEN_L (ARM_ICTL_BASE + IRQ_INTEN_OFFSET_L)
-#define APB_ICT_IRQ_INTEN_H (ARM_ICTL_BASE + IRQ_INTEN_OFFSET_H)
-#define APB_ICT_IRQ_INTMASK (ARM_ICTL_BASE + IRQ_INTMASK_OFFSET)
-#define APB_ICT_IRQ_INTMASK_L (ARM_ICTL_BASE + IRQ_INTMASK_OFFSET_L)
-#define APB_ICT_IRQ_INTMASK_H (ARM_ICTL_BASE + IRQ_INTMASK_OFFSET_H)
-#define APB_ICT_IRQ_INTFORCE (ARM_ICTL_BASE + IRQ_INTFORCE_OFFSET)
-#define APB_ICT_IRQ_INTFORCE_L (ARM_ICTL_BASE + IRQ_INTFORCE_OFFSET_L)
-#define APB_ICT_IRQ_INTFORCE_H (ARM_ICTL_BASE + IRQ_INTFORCE_OFFSET_H)
-#define APB_ICT_IRQ_RAWSTATUS (ARM_ICTL_BASE + IRQ_RAWSTATUS_OFFSET)
-#define APB_ICT_IRQ_RAWSTATUS_L (ARM_ICTL_BASE + IRQ_RAWSTATUS_OFFSET_L)
-#define APB_ICT_IRQ_RAWSTATUS_H (ARM_ICTL_BASE + IRQ_RAWSTATUS_OFFSET_H)
-#define APB_ICT_IRQ_STATUS (ARM_ICTL_BASE + IRQ_STATUS_OFFSET)
-#define APB_ICT_IRQ_STATUS_L (ARM_ICTL_BASE + IRQ_STATUS_OFFSET_L)
-#define APB_ICT_IRQ_STATUS_H (ARM_ICTL_BASE + IRQ_STATUS_OFFSET_H)
-#define APB_ICT_IRQ_MASKSTATUS (ARM_ICTL_BASE + IRQ_MASKSTATUS_OFFSET)
-#define APB_ICT_IRQ_MASKSTATUS_L (ARM_ICTL_BASE + IRQ_MASKSTATUS_OFFSET_L)
-#define APB_ICT_IRQ_MASKSTATUS_H (ARM_ICTL_BASE + IRQ_MASKSTATUS_OFFSET_H)
-#define APB_ICT_IRQ_FINALSTATUS (ARM_ICTL_BASE + IRQ_FINALSTATUS_OFFSET)
-#define APB_ICT_IRQ_FINALSTATUS_L (ARM_ICTL_BASE + IRQ_FINALSTATUS_OFFSET_L)
-#define APB_ICT_IRQ_FINALSTATUS_H (ARM_ICTL_BASE + IRQ_FINALSTATUS_OFFSET_H)
-#define APB_ICT_IRQ_VECTOR (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET)
-#define APB_ICT_IRQ_VECTOR_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_L)
-#define APB_ICT_IRQ_VECTOR_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_H)
-#define APB_ICT_IRQ_VECTOR_0 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_0)
-#define APB_ICT_IRQ_VECTOR_0_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_0_L)
-#define APB_ICT_IRQ_VECTOR_0_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_0_H)
-#define APB_ICT_IRQ_VECTOR_1 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_1)
-#define APB_ICT_IRQ_VECTOR_1_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_1_L)
-#define APB_ICT_IRQ_VECTOR_1_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_1_H)
-#define APB_ICT_IRQ_VECTOR_2 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_2)
-#define APB_ICT_IRQ_VECTOR_2_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_2_L)
-#define APB_ICT_IRQ_VECTOR_2_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_2_H)
-#define APB_ICT_IRQ_VECTOR_3 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_3)
-#define APB_ICT_IRQ_VECTOR_3_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_3_L)
-#define APB_ICT_IRQ_VECTOR_3_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_3_H)
-#define APB_ICT_IRQ_VECTOR_4 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_4)
-#define APB_ICT_IRQ_VECTOR_4_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_4_L)
-#define APB_ICT_IRQ_VECTOR_4_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_4_H)
-#define APB_ICT_IRQ_VECTOR_5 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_5)
-#define APB_ICT_IRQ_VECTOR_5_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_5_L)
-#define APB_ICT_IRQ_VECTOR_5_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_5_H)
-#define APB_ICT_IRQ_VECTOR_6 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_6)
-#define APB_ICT_IRQ_VECTOR_6_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_6_L)
-#define APB_ICT_IRQ_VECTOR_6_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_6_H)
-#define APB_ICT_IRQ_VECTOR_7 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_7)
-#define APB_ICT_IRQ_VECTOR_7_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_7_L)
-#define APB_ICT_IRQ_VECTOR_7_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_7_H)
-#define APB_ICT_IRQ_VECTOR_8 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_8)
-#define APB_ICT_IRQ_VECTOR_8_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_8_L)
-#define APB_ICT_IRQ_VECTOR_8_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_8_H)
-#define APB_ICT_IRQ_VECTOR_9 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_9)
-#define APB_ICT_IRQ_VECTOR_9_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_9_L)
-#define APB_ICT_IRQ_VECTOR_9_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_9_H)
-#define APB_ICT_IRQ_VECTOR_10 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_10)
-#define APB_ICT_IRQ_VECTOR_10_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_10_L)
-#define APB_ICT_IRQ_VECTOR_10_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_10_H)
-#define APB_ICT_IRQ_VECTOR_11 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_11)
-#define APB_ICT_IRQ_VECTOR_11_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_11_L)
-#define APB_ICT_IRQ_VECTOR_11_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_11_H)
-#define APB_ICT_IRQ_VECTOR_12 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_12)
-#define APB_ICT_IRQ_VECTOR_12_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_12_L)
-#define APB_ICT_IRQ_VECTOR_12_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_12_H)
-#define APB_ICT_IRQ_VECTOR_13 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_13)
-#define APB_ICT_IRQ_VECTOR_13_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_13_L)
-#define APB_ICT_IRQ_VECTOR_13_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_13_H)
-#define APB_ICT_IRQ_VECTOR_14 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_14)
-#define APB_ICT_IRQ_VECTOR_14_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_14_L)
-#define APB_ICT_IRQ_VECTOR_14_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_14_H)
-#define APB_ICT_IRQ_VECTOR_15 (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_15)
-#define APB_ICT_IRQ_VECTOR_15_L (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_15_L)
-#define APB_ICT_IRQ_VECTOR_15_H (ARM_ICTL_BASE + IRQ_VECTOR_OFFSET_15_H)
-#define APB_ICT_FIQ_INTEN (ARM_ICTL_BASE + FIQ_INTEN_OFFSET)
-#define APB_ICT_FIQ_INTMASK (ARM_ICTL_BASE + FIQ_INTMASK_OFFSET)
-#define APB_ICT_FIQ_INTFORCE (ARM_ICTL_BASE + FIQ_INTFORCE_OFFSET)
-#define APB_ICT_FIQ_RAWSTATUS (ARM_ICTL_BASE + FIQ_RAWSTATUS_OFFSET)
-#define APB_ICT_FIQ_STATUS (ARM_ICTL_BASE + FIQ_STATUS_OFFSET)
-#define APB_ICT_FIQ_FINALSTATUS (ARM_ICTL_BASE + FIQ_FINALSTATUS_OFFSET)
-#define APB_ICT_IRQ_PLEVEL (ARM_ICTL_BASE + IRQ_PLEVEL_OFFSET)
-#define APB_ICT_ICTL_VERSION_ID (ARM_ICTL_BASE + ICTL_VERSION_ID_OFFSET)
-#define APB_ICT_IRQ_P0_ADDR (ARM_ICTL_BASE + IRQ_P0_OFFSET)
-#define APB_ICT_IRQ_P1_ADDR (ARM_ICTL_BASE + IRQ_P1_OFFSET)
-#define APB_ICT_IRQ_P2_ADDR (ARM_ICTL_BASE + IRQ_P2_OFFSET)
-#define APB_ICT_IRQ_P3_ADDR (ARM_ICTL_BASE + IRQ_P3_OFFSET)
-#define APB_ICT_IRQ_P4_ADDR (ARM_ICTL_BASE + IRQ_P4_OFFSET)
-#define APB_ICT_IRQ_P5_ADDR (ARM_ICTL_BASE + IRQ_P5_OFFSET)
-#define APB_ICT_IRQ_P6_ADDR (ARM_ICTL_BASE + IRQ_P6_OFFSET)
-#define APB_ICT_IRQ_P7_ADDR (ARM_ICTL_BASE + IRQ_P7_OFFSET)
-#define APB_ICT_IRQ_P8_ADDR (ARM_ICTL_BASE + IRQ_P8_OFFSET)
-#define APB_ICT_IRQ_P9_ADDR (ARM_ICTL_BASE + IRQ_P9_OFFSET)
-#define APB_ICT_IRQ_P10_ADDR (ARM_ICTL_BASE + IRQ_P10_OFFSET)
-#define APB_ICT_IRQ_P11_ADDR (ARM_ICTL_BASE + IRQ_P11_OFFSET)
-#define APB_ICT_IRQ_P12_ADDR (ARM_ICTL_BASE + IRQ_P12_OFFSET)
-#define APB_ICT_IRQ_P13_ADDR (ARM_ICTL_BASE + IRQ_P13_OFFSET)
-#define APB_ICT_IRQ_P14_ADDR (ARM_ICTL_BASE + IRQ_P14_OFFSET)
-#define APB_ICT_IRQ_P15_ADDR (ARM_ICTL_BASE + IRQ_P15_OFFSET)
-#define APB_ICT_IRQ_P16_ADDR (ARM_ICTL_BASE + IRQ_P16_OFFSET)
-#define APB_ICT_IRQ_P17_ADDR (ARM_ICTL_BASE + IRQ_P17_OFFSET)
-#define APB_ICT_IRQ_P18_ADDR (ARM_ICTL_BASE + IRQ_P18_OFFSET)
-#define APB_ICT_IRQ_P19_ADDR (ARM_ICTL_BASE + IRQ_P19_OFFSET)
-#define APB_ICT_IRQ_P20_ADDR (ARM_ICTL_BASE + IRQ_P20_OFFSET)
-#define APB_ICT_IRQ_P21_ADDR (ARM_ICTL_BASE + IRQ_P21_OFFSET)
-#define APB_ICT_IRQ_P22_ADDR (ARM_ICTL_BASE + IRQ_P22_OFFSET)
-#define APB_ICT_IRQ_P23_ADDR (ARM_ICTL_BASE + IRQ_P23_OFFSET)
-#define APB_ICT_IRQ_P24_ADDR (ARM_ICTL_BASE + IRQ_P24_OFFSET)
-#define APB_ICT_IRQ_P25_ADDR (ARM_ICTL_BASE + IRQ_P25_OFFSET)
-#define APB_ICT_IRQ_P26_ADDR (ARM_ICTL_BASE + IRQ_P26_OFFSET)
-#define APB_ICT_IRQ_P27_ADDR (ARM_ICTL_BASE + IRQ_P27_OFFSET)
-#define APB_ICT_IRQ_P28_ADDR (ARM_ICTL_BASE + IRQ_P28_OFFSET)
-#define APB_ICT_IRQ_P29_ADDR (ARM_ICTL_BASE + IRQ_P29_OFFSET)
-#define APB_ICT_IRQ_P29_ADDR (ARM_ICTL_BASE + IRQ_P29_OFFSET)
-#define APB_ICT_IRQ_P30_ADDR (ARM_ICTL_BASE + IRQ_P30_OFFSET)
-#define APB_ICT_IRQ_P31_ADDR (ARM_ICTL_BASE + IRQ_P31_OFFSET)
-#define APB_ICT_IRQ_P32_ADDR (ARM_ICTL_BASE + IRQ_P32_OFFSET)
-#define APB_ICT_IRQ_P33_ADDR (ARM_ICTL_BASE + IRQ_P33_OFFSET)
-#define APB_ICT_IRQ_P34_ADDR (ARM_ICTL_BASE + IRQ_P34_OFFSET)
-#define APB_ICT_IRQ_P35_ADDR (ARM_ICTL_BASE + IRQ_P35_OFFSET)
-#define APB_ICT_IRQ_P36_ADDR (ARM_ICTL_BASE + IRQ_P36_OFFSET)
-#define APB_ICT_IRQ_P37_ADDR (ARM_ICTL_BASE + IRQ_P37_OFFSET)
-#define APB_ICT_IRQ_P38_ADDR (ARM_ICTL_BASE + IRQ_P38_OFFSET)
-#define APB_ICT_IRQ_P39_ADDR (ARM_ICTL_BASE + IRQ_P39_OFFSET)
-#define APB_ICT_IRQ_P40_ADDR (ARM_ICTL_BASE + IRQ_P40_OFFSET)
-#define APB_ICT_IRQ_P41_ADDR (ARM_ICTL_BASE + IRQ_P41_OFFSET)
-#define APB_ICT_IRQ_P42_ADDR (ARM_ICTL_BASE + IRQ_P42_OFFSET)
-#define APB_ICT_IRQ_P43_ADDR (ARM_ICTL_BASE + IRQ_P43_OFFSET)
-#define APB_ICT_IRQ_P44_ADDR (ARM_ICTL_BASE + IRQ_P44_OFFSET)
-#define APB_ICT_IRQ_P45_ADDR (ARM_ICTL_BASE + IRQ_P45_OFFSET)
-#define APB_ICT_IRQ_P46_ADDR (ARM_ICTL_BASE + IRQ_P46_OFFSET)
-#define APB_ICT_IRQ_P47_ADDR (ARM_ICTL_BASE + IRQ_P47_OFFSET)
-#define APB_ICT_IRQ_P48_ADDR (ARM_ICTL_BASE + IRQ_P48_OFFSET)
-#define APB_ICT_IRQ_P49_ADDR (ARM_ICTL_BASE + IRQ_P49_OFFSET)
-#define APB_ICT_IRQ_P50_ADDR (ARM_ICTL_BASE + IRQ_P50_OFFSET)
-#define APB_ICT_IRQ_P51_ADDR (ARM_ICTL_BASE + IRQ_P51_OFFSET)
-#define APB_ICT_IRQ_P52_ADDR (ARM_ICTL_BASE + IRQ_P52_OFFSET)
-#define APB_ICT_IRQ_P53_ADDR (ARM_ICTL_BASE + IRQ_P53_OFFSET)
-#define APB_ICT_IRQ_P54_ADDR (ARM_ICTL_BASE + IRQ_P54_OFFSET)
-#define APB_ICT_IRQ_P55_ADDR (ARM_ICTL_BASE + IRQ_P55_OFFSET)
-#define APB_ICT_IRQ_P56_ADDR (ARM_ICTL_BASE + IRQ_P56_OFFSET)
-#define APB_ICT_IRQ_P57_ADDR (ARM_ICTL_BASE + IRQ_P57_OFFSET)
-#define APB_ICT_IRQ_P58_ADDR (ARM_ICTL_BASE + IRQ_P58_OFFSET)
-#define APB_ICT_IRQ_P59_ADDR (ARM_ICTL_BASE + IRQ_P59_OFFSET)
-#define APB_ICT_IRQ_P60_ADDR (ARM_ICTL_BASE + IRQ_P60_OFFSET)
-#define APB_ICT_IRQ_P61_ADDR (ARM_ICTL_BASE + IRQ_P61_OFFSET)
-#define APB_ICT_IRQ_P62_ADDR (ARM_ICTL_BASE + IRQ_P62_OFFSET)
-#define APB_ICT_IRQ_P63_ADDR (ARM_ICTL_BASE + IRQ_P63_OFFSET)
-
-#define APB_ICT_PING_1BIT_WR (APB_ICT_IRQ_INTEN_L)
-
-#define CC_APB_ICT_APB_DATA_WIDTH 32
-#define CC_APB_ICT_FORCEREG_ACTIVE_HIGH 1
-#define CC_APB_ICT_INT_POL 0
-#define CC_APB_ICT_HAS_PFLT 1
-#define CC_APB_ICT_HAS_VECTOR 1
-#define CC_APB_ICT_HAS_FIQ 0
-#define CC_APB_ICT_FIQ_NUM 4
-#define CC_APB_ICT_IRQ_NUM 32
-#define CC_APB_ICT_IRQSRC_POL_TYPE 0
-#define CC_APB_ICT_FIQSRC_POL_TYPE 0
-#define CC_APB_ICT_IRQ_DFLT_EN 0x0
-#define CC_APB_ICT_FIQ_DFLT_EN 0x0
-#define CC_APB_ICT_IRQ_PLEVEL 0
-#define CC_APB_ICT_READ_PRIORITY 1
-#define CC_APB_ICT_HC_PRIORITIES 0
-#define CC_APB_ICT_ISRC_PLEVEL_0 0
-#define CC_APB_ICT_ISRC_PLEVEL_1 0
-#define CC_APB_ICT_ISRC_PLEVEL_2 0
-#define CC_APB_ICT_ISRC_PLEVEL_3 0
-#define CC_APB_ICT_ISRC_PLEVEL_4 0
-#define CC_APB_ICT_ISRC_PLEVEL_5 0
-#define CC_APB_ICT_ISRC_PLEVEL_6 0
-#define CC_APB_ICT_ISRC_PLEVEL_7 0
-#define CC_APB_ICT_ISRC_PLEVEL_8 0
-#define CC_APB_ICT_ISRC_PLEVEL_9 0
-#define CC_APB_ICT_ISRC_PLEVEL_10 0
-#define CC_APB_ICT_ISRC_PLEVEL_11 0
-#define CC_APB_ICT_ISRC_PLEVEL_12 0
-#define CC_APB_ICT_ISRC_PLEVEL_13 0
-#define CC_APB_ICT_ISRC_PLEVEL_14 0
-#define CC_APB_ICT_ISRC_PLEVEL_15 0
-#define CC_APB_ICT_ISRC_PLEVEL_16 0
-#define CC_APB_ICT_ISRC_PLEVEL_17 0
-#define CC_APB_ICT_ISRC_PLEVEL_18 0
-#define CC_APB_ICT_ISRC_PLEVEL_19 0
-#define CC_APB_ICT_ISRC_PLEVEL_20 0
-#define CC_APB_ICT_ISRC_PLEVEL_21 0
-#define CC_APB_ICT_ISRC_PLEVEL_22 0
-#define CC_APB_ICT_ISRC_PLEVEL_23 0
-#define CC_APB_ICT_ISRC_PLEVEL_24 0
-#define CC_APB_ICT_ISRC_PLEVEL_25 0
-#define CC_APB_ICT_ISRC_PLEVEL_26 0
-#define CC_APB_ICT_ISRC_PLEVEL_27 0
-#define CC_APB_ICT_ISRC_PLEVEL_28 0
-#define CC_APB_ICT_ISRC_PLEVEL_29 0
-#define CC_APB_ICT_ISRC_PLEVEL_30 0
-#define CC_APB_ICT_ISRC_PLEVEL_31 0
-#define CC_APB_ICT_ISRC_PLEVEL_32 0
-#define CC_APB_ICT_ISRC_PLEVEL_33 1
-#define CC_APB_ICT_ISRC_PLEVEL_34 2
-#define CC_APB_ICT_ISRC_PLEVEL_35 3
-#define CC_APB_ICT_ISRC_PLEVEL_36 4
-#define CC_APB_ICT_ISRC_PLEVEL_37 5
-#define CC_APB_ICT_ISRC_PLEVEL_38 6
-#define CC_APB_ICT_ISRC_PLEVEL_39 7
-#define CC_APB_ICT_ISRC_PLEVEL_40 8
-#define CC_APB_ICT_ISRC_PLEVEL_41 9
-#define CC_APB_ICT_ISRC_PLEVEL_42 10
-#define CC_APB_ICT_ISRC_PLEVEL_43 11
-#define CC_APB_ICT_ISRC_PLEVEL_44 12
-#define CC_APB_ICT_ISRC_PLEVEL_45 13
-#define CC_APB_ICT_ISRC_PLEVEL_46 14
-#define CC_APB_ICT_ISRC_PLEVEL_47 15
-#define CC_APB_ICT_ISRC_PLEVEL_48 0
-#define CC_APB_ICT_ISRC_PLEVEL_49 1
-#define CC_APB_ICT_ISRC_PLEVEL_50 2
-#define CC_APB_ICT_ISRC_PLEVEL_51 3
-#define CC_APB_ICT_ISRC_PLEVEL_52 4
-#define CC_APB_ICT_ISRC_PLEVEL_53 5
-#define CC_APB_ICT_ISRC_PLEVEL_54 6
-#define CC_APB_ICT_ISRC_PLEVEL_55 7
-#define CC_APB_ICT_ISRC_PLEVEL_56 8
-#define CC_APB_ICT_ISRC_PLEVEL_57 9
-#define CC_APB_ICT_ISRC_PLEVEL_58 10
-#define CC_APB_ICT_ISRC_PLEVEL_59 11
-#define CC_APB_ICT_ISRC_PLEVEL_60 12
-#define CC_APB_ICT_ISRC_PLEVEL_61 13
-#define CC_APB_ICT_ISRC_PLEVEL_62 14
-#define CC_APB_ICT_ISRC_PLEVEL_63 15
-#define CC_APB_ICT_VECTOR_0 0x0
-#define CC_APB_ICT_VECTOR_1 0x1
-#define CC_APB_ICT_VECTOR_2 0x2
-#define CC_APB_ICT_VECTOR_3 0x3
-#define CC_APB_ICT_VECTOR_4 0x4
-#define CC_APB_ICT_VECTOR_5 0x5
-#define CC_APB_ICT_VECTOR_6 0x6
-#define CC_APB_ICT_VECTOR_7 0x7
-#define CC_APB_ICT_VECTOR_8 0x8
-#define CC_APB_ICT_VECTOR_9 0x9
-#define CC_APB_ICT_VECTOR_10 0xa
-#define CC_APB_ICT_VECTOR_11 0xb
-#define CC_APB_ICT_VECTOR_12 0xc
-#define CC_APB_ICT_VECTOR_13 0xd
-#define CC_APB_ICT_VECTOR_14 0xe
-#define CC_APB_ICT_VECTOR_15 0xf
-#define CC_APB_ICT_HC_VECTOR_0 1
-#define CC_APB_ICT_HC_VECTOR_1 1
-#define CC_APB_ICT_HC_VECTOR_2 1
-#define CC_APB_ICT_HC_VECTOR_3 1
-#define CC_APB_ICT_HC_VECTOR_4 1
-#define CC_APB_ICT_HC_VECTOR_5 1
-#define CC_APB_ICT_HC_VECTOR_6 1
-#define CC_APB_ICT_HC_VECTOR_7 1
-#define CC_APB_ICT_HC_VECTOR_8 1
-#define CC_APB_ICT_HC_VECTOR_9 1
-#define CC_APB_ICT_HC_VECTOR_10 1
-#define CC_APB_ICT_HC_VECTOR_11 1
-#define CC_APB_ICT_HC_VECTOR_12 1
-#define CC_APB_ICT_HC_VECTOR_13 1
-#define CC_APB_ICT_HC_VECTOR_14 1
-#define CC_APB_ICT_HC_VECTOR_15 1
-#define CC_APB_ICT_HC_VECTOR_15 1
-
-#endif /* __ASM_ARCH_ARM_ICTL_H */
-
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_timer1.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_timer1.h
deleted file mode 100644
index ff71417c61..0000000000
--- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_timer1.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * include/asm-arm/arch-spc300/arm_timer1.h
- *
- * Copyright (C) 2009 SPiDCOM Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_ARM_TIMER1_H
-#define __ASM_ARCH_ARM_TIMER1_H
-
-#ifndef ARM_TIMER1_BASE
- #error "ARM_TIMER1_BASE macro needs to be defined before including file arm_timer1.h"
-#endif
-
-#define TIMERLOADCOUNTOFF_1 0x00
-#define TIMERCURRENTVALOFF_1 0x04
-#define TIMERCONTROLREGOFF_1 0x08
-#define TIMEREOIOFF_1 0x0c
-#define TIMERINTSTATOFF_1 0x10
-#define TIMERSINTSTATOFF_1 0xa0
-#define TIMERSEOIOFF_1 0xa4
-#define TIMERSRAWINTSTATOFF_1 0xa8
-#define TIMERVERSIONIDOFF_1 0xac
-
-#define TIMER1BASE_1 (ARM_TIMER1_BASE + TIMERLOADCOUNTOFF_1)
-#define TIMER2BASE_1 (ARM_TIMER1_BASE + 0x14)
-#define TIMER3BASE_1 (ARM_TIMER1_BASE + 0x28)
-#define TIMER4BASE_1 (ARM_TIMER1_BASE + 0x3c)
-#define TIMER5BASE_1 (ARM_TIMER1_BASE + 0x50)
-#define TIMER6BASE_1 (ARM_TIMER1_BASE + 0x64)
-#define TIMER7BASE_1 (ARM_TIMER1_BASE + 0x78)
-#define TIMER8BASE_1 (ARM_TIMER1_BASE + 0x8c )
-#define TIMER1LOADCOUNT_1 (TIMER1BASE_1 + TIMERLOADCOUNTOFF_1)
-#define TIMER1CURRENTVAL_1 (TIMER1BASE_1 + TIMERCURRENTVALOFF_1)
-#define TIMER1CONTROLREG_1 (TIMER1BASE_1 + TIMERCONTROLREGOFF_1)
-#define TIMER1EOI_1 (TIMER1BASE_1 + TIMEREOIOFF_1)
-#define TIMER1INTSTAT_1 (TIMER1BASE_1 + TIMERINTSTATOFF_1)
-#define TIMER2LOADCOUNT_1 (TIMER2BASE_1 + TIMERLOADCOUNTOFF_1)
-#define TIMER2CURRENTVAL_1 (TIMER2BASE_1 + TIMERCURRENTVALOFF_1)
-#define TIMER2CONTROLREG_1 (TIMER2BASE_1 + TIMERCONTROLREGOFF_1)
-#define TIMER2EOI_1 (TIMER2BASE_1 + TIMEREOIOFF_1)
-#define TIMER2INTSTAT_1 (TIMER2BASE_1 + TIMERINTSTATOFF_1)
-#define TIMER3LOADCOUNT_1 (TIMER3BASE_1 + TIMERLOADCOUNTOFF_1)
-#define TIMER3CURRENTVAL_1 (TIMER3BASE_1 + TIMERCURRENTVALOFF_1)
-#define TIMER3CONTROLREG_1 (TIMER3BASE_1 + TIMERCONTROLREGOFF_1)
-#define TIMER3EOI_1 (TIMER3BASE_1 + TIMEREOIOFF_1)
-#define TIMER3INTSTAT_1 (TIMER3BASE_1 + TIMERINTSTATOFF_1)
-#define TIMER4LOADCOUNT_1 (TIMER4BASE_1 + TIMERLOADCOUNTOFF_1)
-#define TIMER4CURRENTVAL_1 (TIMER4BASE_1 + TIMERCURRENTVALOFF_1)
-#define TIMER4CONTROLREG_1 (TIMER4BASE_1 + TIMERCONTROLREGOFF_1)
-#define TIMER4EOI_1 (TIMER4BASE_1 + TIMEREOIOFF_1)
-#define TIMER4INTSTAT_1 (TIMER4BASE_1 + TIMERINTSTATOFF_1)
-#define TIMER5LOADCOUNT_1 (TIMER5BASE_1 + TIMERLOADCOUNTOFF_1)
-#define TIMER5CURRENTVAL_1 (TIMER5BASE_1 + TIMERCURRENTVALOFF_1)
-#define TIMER5CONTROLREG_1 (TIMER5BASE_1 + TIMERCONTROLREGOFF_1)
-#define TIMER5EOI_1 (TIMER5BASE_1 + TIMEREOIOFF_1)
-#define TIMER5INTSTAT_1 (TIMER5BASE_1 + TIMERINTSTATOFF_1)
-#define TIMER6LOADCOUNT_1 (TIMER6BASE_1 + TIMERLOADCOUNTOFF_1)
-#define TIMER6CURRENTVAL_1 (TIMER6BASE_1 + TIMERCURRENTVALOFF_1)
-#define TIMER6CONTROLREG_1 (TIMER6BASE_1 + TIMERCONTROLREGOFF_1)
-#define TIMER6EOI_1 (TIMER6BASE_1 + TIMEREOIOFF_1)
-#define TIMER6INTSTAT_1 (TIMER6BASE_1 + TIMERINTSTATOFF_1)
-#define TIMER7LOADCOUNT_1 (TIMER7BASE_1 + TIMERLOADCOUNTOFF_1)
-#define TIMER7CURRENTVAL_1 (TIMER7BASE_1 + TIMERCURRENTVALOFF_1)
-#define TIMER7CONTROLREG_1 (TIMER7BASE_1 + TIMERCONTROLREGOFF_1)
-#define TIMER7EOI_1 (TIMER7BASE_1 + TIMEREOIOFF_1)
-#define TIMER7INTSTAT_1 (TIMER7BASE_1 + TIMERINTSTATOFF_1)
-#define TIMER8LOADCOUNT_1 (TIMER8BASE_1 + TIMERLOADCOUNTOFF_1)
-#define TIMER8CURRENTVAL_1 (TIMER8BASE_1 + TIMERCURRENTVALOFF_1)
-#define TIMER8CONTROLREG_1 (TIMER8BASE_1 + TIMERCONTROLREGOFF_1)
-#define TIMER8EOI_1 (TIMER8BASE_1 + TIMEREOIOFF_1)
-#define TIMER8INTSTAT_1 (TIMER8BASE_1 + TIMERINTSTATOFF_1)
-#define TIMERSEOI_1 (ARM_TIMER1_BASE + TIMERSEOIOFF_1)
-#define TIMERSINTSTAT_1 (ARM_TIMER1_BASE + TIMERSINTSTATOFF_1)
-#define TIMERSRAWINTSTAT_1 (ARM_TIMER1_BASE + TIMERSRAWINTSTATOFF_1)
-
-#define TIMERPING_1BIT_WR_1 (TIMER1LOADCOUNT_1)
-
-#define CC_TIM_APB_DATA_WIDTH_1 32
-#define CC_NUM_TIMERS_1 4
-#define CC_TIM_INTRPT_PLRITY_1 1
-#define CC_TIM_INTR_IO_1 1
-#define CC_TIMER_WIDTH_2_1 32
-#define CC_TIMER_HAS_TOGGLE_2_1 0
-#define CC_TIM_METASTABLE_2_1 1
-#define CC_TIM_PULSE_EXTD_2_1 0
-#define CC_TIM_COHERENCY_2_1 0
-#define CC_TIMER_WIDTH_3_1 32
-#define CC_TIMER_HAS_TOGGLE_3_1 0
-#define CC_TIM_METASTABLE_3_1 1
-#define CC_TIM_PULSE_EXTD_3_1 0
-#define CC_TIM_COHERENCY_3_1 0
-#define CC_TIMER_WIDTH_4_1 32
-#define CC_TIMER_HAS_TOGGLE_4_1 0
-#define CC_TIM_METASTABLE_4_1 1
-#define CC_TIM_PULSE_EXTD_4_1 0
-#define CC_TIM_COHERENCY_4_1 0
-#define CC_TIMER_WIDTH_5_1 32
-#define CC_TIMER_HAS_TOGGLE_5_1 0
-#define CC_TIM_METASTABLE_5_1 0
-#define CC_TIM_PULSE_EXTD_5_1 0
-#define CC_TIM_COHERENCY_5_1 0
-#define CC_TIMER_WIDTH_6_1 32
-#define CC_TIMER_HAS_TOGGLE_6_1 0
-#define CC_TIM_METASTABLE_6_1 0
-#define CC_TIM_PULSE_EXTD_6_1 0
-#define CC_TIM_COHERENCY_6_1 0
-#define CC_TIMER_WIDTH_7_1 32
-#define CC_TIMER_HAS_TOGGLE_7_1 0
-#define CC_TIM_METASTABLE_7_1 0
-#define CC_TIM_PULSE_EXTD_7_1 0
-#define CC_TIM_COHERENCY_7_1 0
-#define CC_TIMER_WIDTH_8_1 32
-#define CC_TIMER_HAS_TOGGLE_8_1 0
-#define CC_TIM_METASTABLE_8_1 0
-#define CC_TIM_PULSE_EXTD_8_1 0
-#define CC_TIM_COHERENCY_8_1 0
-
-#endif /* __ASM_ARCH_ARM_TIMER1_H */
-
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_timer2.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_timer2.h
deleted file mode 100644
index 7f3517ea19..0000000000
--- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_timer2.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * include/asm-arm/arch-spc300/arm_timer2.h
- *
- * Copyright (C) 2009 SPiDCOM Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_ARM_TIMER2_H
-#define __ASM_ARCH_ARM_TIMER2_H
-
-#ifndef ARM_TIMER2_BASE
- #error "ARM_TIMER2_BASE macro needs to be defined before including file arm_timer2.h"
-#endif
-
-#define TIMERLOADCOUNTOFF_2 0x00
-#define TIMERCURRENTVALOFF_2 0x04
-#define TIMERCONTROLREGOFF_2 0x08
-#define TIMEREOIOFF_2 0x0c
-#define TIMERINTSTATOFF_2 0x10
-#define TIMERSINTSTATOFF_2 0xa0
-#define TIMERSEOIOFF_2 0xa4
-#define TIMERSRAWINTSTATOFF_2 0xa8
-#define TIMERVERSIONIDOFF_2 0xac
-
-#define TIMER1BASE_2 (ARM_TIMER2_BASE + TIMERLOADCOUNTOFF_2)
-#define TIMER2BASE_2 (ARM_TIMER2_BASE + 0x14)
-#define TIMER3BASE_2 (ARM_TIMER2_BASE + 0x28)
-#define TIMER4BASE_2 (ARM_TIMER2_BASE + 0x3c)
-#define TIMER5BASE_2 (ARM_TIMER2_BASE + 0x50)
-#define TIMER6BASE_2 (ARM_TIMER2_BASE + 0x64)
-#define TIMER7BASE_2 (ARM_TIMER2_BASE + 0x78)
-#define TIMER8BASE_2 (ARM_TIMER2_BASE + 0x8c )
-#define TIMER1LOADCOUNT_2 (TIMER1BASE_2 + TIMERLOADCOUNTOFF_2)
-#define TIMER1CURRENTVAL_2 (TIMER1BASE_2 + TIMERCURRENTVALOFF_2)
-#define TIMER1CONTROLREG_2 (TIMER1BASE_2 + TIMERCONTROLREGOFF_2)
-#define TIMER1EOI_2 (TIMER1BASE_2 + TIMEREOIOFF_2)
-#define TIMER1INTSTAT_2 (TIMER1BASE_2 + TIMERINTSTATOFF_2)
-#define TIMER2LOADCOUNT_2 (TIMER2BASE_2 + TIMERLOADCOUNTOFF_2)
-#define TIMER2CURRENTVAL_2 (TIMER2BASE_2 + TIMERCURRENTVALOFF_2)
-#define TIMER2CONTROLREG_2 (TIMER2BASE_2 + TIMERCONTROLREGOFF_2)
-#define TIMER2EOI_2 (TIMER2BASE_2 + TIMEREOIOFF_2)
-#define TIMER2INTSTAT_2 (TIMER2BASE_2 + TIMERINTSTATOFF_2)
-#define TIMER3LOADCOUNT_2 (TIMER3BASE_2 + TIMERLOADCOUNTOFF_2)
-#define TIMER3CURRENTVAL_2 (TIMER3BASE_2 + TIMERCURRENTVALOFF_2)
-#define TIMER3CONTROLREG_2 (TIMER3BASE_2 + TIMERCONTROLREGOFF_2)
-#define TIMER3EOI_2 (TIMER3BASE_2 + TIMEREOIOFF_2)
-#define TIMER3INTSTAT_2 (TIMER3BASE_2 + TIMERINTSTATOFF_2)
-#define TIMER4LOADCOUNT_2 (TIMER4BASE_2 + TIMERLOADCOUNTOFF_2)
-#define TIMER4CURRENTVAL_2 (TIMER4BASE_2 + TIMERCURRENTVALOFF_2)
-#define TIMER4CONTROLREG_2 (TIMER4BASE_2 + TIMERCONTROLREGOFF_2)
-#define TIMER4EOI_2 (TIMER4BASE_2 + TIMEREOIOFF_2)
-#define TIMER4INTSTAT_2 (TIMER4BASE_2 + TIMERINTSTATOFF_2)
-#define TIMER5LOADCOUNT_2 (TIMER5BASE_2 + TIMERLOADCOUNTOFF_2)
-#define TIMER5CURRENTVAL_2 (TIMER5BASE_2 + TIMERCURRENTVALOFF_2)
-#define TIMER5CONTROLREG_2 (TIMER5BASE_2 + TIMERCONTROLREGOFF_2)
-#define TIMER5EOI_2 (TIMER5BASE_2 + TIMEREOIOFF_2)
-#define TIMER5INTSTAT_2 (TIMER5BASE_2 + TIMERINTSTATOFF_2)
-#define TIMER6LOADCOUNT_2 (TIMER6BASE_2 + TIMERLOADCOUNTOFF_2)
-#define TIMER6CURRENTVAL_2 (TIMER6BASE_2 + TIMERCURRENTVALOFF_2)
-#define TIMER6CONTROLREG_2 (TIMER6BASE_2 + TIMERCONTROLREGOFF_2)
-#define TIMER6EOI_2 (TIMER6BASE_2 + TIMEREOIOFF_2)
-#define TIMER6INTSTAT_2 (TIMER6BASE_2 + TIMERINTSTATOFF_2)
-#define TIMER7LOADCOUNT_2 (TIMER7BASE_2 + TIMERLOADCOUNTOFF_2)
-#define TIMER7CURRENTVAL_2 (TIMER7BASE_2 + TIMERCURRENTVALOFF_2)
-#define TIMER7CONTROLREG_2 (TIMER7BASE_2 + TIMERCONTROLREGOFF_2)
-#define TIMER7EOI_2 (TIMER7BASE_2 + TIMEREOIOFF_2)
-#define TIMER7INTSTAT_2 (TIMER7BASE_2 + TIMERINTSTATOFF_2)
-#define TIMER8LOADCOUNT_2 (TIMER8BASE_2 + TIMERLOADCOUNTOFF_2)
-#define TIMER8CURRENTVAL_2 (TIMER8BASE_2 + TIMERCURRENTVALOFF_2)
-#define TIMER8CONTROLREG_2 (TIMER8BASE_2 + TIMERCONTROLREGOFF_2)
-#define TIMER8EOI_2 (TIMER8BASE_2 + TIMEREOIOFF_2)
-#define TIMER8INTSTAT_2 (TIMER8BASE_2 + TIMERINTSTATOFF_2)
-#define TIMERSEOI_2 (ARM_TIMER2_BASE + TIMERSEOIOFF_2)
-#define TIMERSINTSTAT_2 (ARM_TIMER2_BASE + TIMERSINTSTATOFF_2)
-#define TIMERSRAWINTSTAT_2 (ARM_TIMER2_BASE + TIMERSRAWINTSTATOFF_2)
-
-#define TIMERPING_1BIT_WR_2 (TIMER1LOADCOUNT_2)
-
-#define CC_TIM_APB_DATA_WIDTH_2 32
-#define CC_NUM_TIMERS_2 4
-#define CC_TIM_INTRPT_PLRITY_2 1
-#define CC_TIM_INTR_IO_2 1
-#define CC_TIMER_WIDTH_2_2 32
-#define CC_TIMER_HAS_TOGGLE_2_2 0
-#define CC_TIM_METASTABLE_2_2 1
-#define CC_TIM_PULSE_EXTD_2_2 0
-#define CC_TIM_COHERENCY_2_2 0
-#define CC_TIMER_WIDTH_3_2 32
-#define CC_TIMER_HAS_TOGGLE_3_2 0
-#define CC_TIM_METASTABLE_3_2 1
-#define CC_TIM_PULSE_EXTD_3_2 0
-#define CC_TIM_COHERENCY_3_2 0
-#define CC_TIMER_WIDTH_4_2 32
-#define CC_TIMER_HAS_TOGGLE_4_2 0
-#define CC_TIM_METASTABLE_4_2 1
-#define CC_TIM_PULSE_EXTD_4_2 0
-#define CC_TIM_COHERENCY_4_2 0
-#define CC_TIMER_WIDTH_5_2 32
-#define CC_TIMER_HAS_TOGGLE_5_2 0
-#define CC_TIM_METASTABLE_5_2 0
-#define CC_TIM_PULSE_EXTD_5_2 0
-#define CC_TIM_COHERENCY_5_2 0
-#define CC_TIMER_WIDTH_6_2 32
-#define CC_TIMER_HAS_TOGGLE_6_2 0
-#define CC_TIM_METASTABLE_6_2 0
-#define CC_TIM_PULSE_EXTD_6_2 0
-#define CC_TIM_COHERENCY_6_2 0
-#define CC_TIMER_WIDTH_7_2 32
-#define CC_TIMER_HAS_TOGGLE_7_2 0
-#define CC_TIM_METASTABLE_7_2 0
-#define CC_TIM_PULSE_EXTD_7_2 0
-#define CC_TIM_COHERENCY_7_2 0
-#define CC_TIMER_WIDTH_8_2 32
-#define CC_TIMER_HAS_TOGGLE_8_2 0
-#define CC_TIM_METASTABLE_8_2 0
-#define CC_TIM_PULSE_EXTD_8_2 0
-#define CC_TIM_COHERENCY_8_2 0
-
-#endif /* __ASM_ARCH_ARM_TIMER2_H */
-
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_uart1.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_uart1.h
deleted file mode 100644
index e002701deb..0000000000
--- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_uart1.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * include/asm-arm/arch-spc300/arm_uart1.h
- *
- * Copyright (C) 2009 SPiDCOM Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_ARM_UART1_H
-#define __ASM_ARCH_ARM_UART1_H
-
-#ifndef ARM_UART1_BASE
- #error "ARM_UART1_BASE macro needs to be defined before including file arm_uart1.h"
-#endif
-
-#define UARTReceiveBufferReg_Offset_1 0x00
-#define UARTTransmitHoldingReg_Offset_1 0x00
-#define UARTDivisorLatchLow_Offset_1 0x00
-#define UARTInterruptEnableReg_Offset_1 0x04
-#define UARTDivisorLatchHigh_Offset_1 0x04
-#define UARTInterruptIdentificationReg_Offset_1 0x08
-#define UARTFIFOControlReg_Offset_1 0x08
-#define UARTLineControlReg_Offset_1 0x0C
-#define UARTModemControlReg_Offset_1 0x10
-#define UARTLineStatusReg_Offset_1 0x14
-#define UARTModemStatusReg_Offset_1 0x18
-
-#define UARTScratchpadReg_Offset_1 0x1C
-
-#define UARTShadowReceiveBufferRegLow_Offset_1 0x30
-
-#define UARTShadowReceiveBufferRegHigh_Offset_1 0x6C
-
-#define UARTShadowTransmitHoldingRegLow_Offset_1 0x30
-
-#define UARTShadowTransmitHoldingRegHigh_Offset_1 0x6C
-
-#define UARTFIFOAccessReg_Offset_1 0x70
-
-#define UARTTransmitFIFOReadReg_Offset_1 0x74
-
-#define UARTReceiveFIFOWriteReg_Offset_1 0x78
-
-#define UARTUARTStatusReg_Offset_1 0x7C
-
-#define UARTTransmitFIFOLevelReg_Offset_1 0x80
-
-#define UARTReceiveFIFOLevelReg_Offset_1 0x84
-
-#define UARTSoftwareResetReg_Offset_1 0x88
-
-#define UARTShadowRequestToSendReg_Offset_1 0x8C
-
-#define UARTShadowBreakControlReg_Offset_1 0x90
-
-#define UARTShadowDMAModeReg_Offset_1 0x94
-
-#define UARTShadowFIFOEnableReg_Offset_1 0x98
-
-#define UARTShadowRCVRTriggerReg_Offset_1 0x9C
-
-#define UARTShadowTXEmptyTriggerReg_Offset_1 0xA0
-
-#define UARTHaltTXReg_Offset_1 0xA4
-
-#define UARTDMASAReg_Offset_1 0xA8
-
-#define UARTCIDReg_Offset_1 0xF4
-
-#define UARTCVReg_Offset_1 0xF8
-
-#define UARTPIDReg_Offset_1 0xFC
-
-#define UARTReceiveBufferReg_1 (ARM_UART1_BASE + UARTReceiveBufferReg_Offset_1 )
-#define UARTTransmitHoldingReg_1 (ARM_UART1_BASE + UARTTransmitHoldingReg_Offset_1 )
-#define UARTDivisorLatchLow_1 (ARM_UART1_BASE + UARTDivisorLatchLow_Offset_1 )
-#define UARTInterruptEnableReg_1 (ARM_UART1_BASE + UARTInterruptEnableReg_Offset_1 )
-#define UARTDivisorLatchHigh_1 (ARM_UART1_BASE + UARTDivisorLatchHigh_Offset_1 )
-#define UARTInterruptIdentificationReg_1 (ARM_UART1_BASE + UARTInterruptIdentificationReg_Offset_1 )
-#define UARTFIFOControlReg_1 (ARM_UART1_BASE + UARTFIFOControlReg_Offset_1 )
-#define UARTLineControlReg_1 (ARM_UART1_BASE + UARTLineControlReg_Offset_1 )
-#define UARTModemControlReg_1 (ARM_UART1_BASE + UARTModemControlReg_Offset_1 )
-#define UARTLineStatusReg_1 (ARM_UART1_BASE + UARTLineStatusReg_Offset_1 )
-#define UARTModemStatusReg_1 (ARM_UART1_BASE + UARTModemStatusReg_Offset_1 )
-#define UARTScratchpadReg_1 (ARM_UART1_BASE + UARTScratchpadReg_Offset_1 )
-#define UARTShadowReceiveBufferRegLow_1 (ARM_UART1_BASE + UARTShadowReceiveBufferRegLow_Offset_1 )
-#define UARTShadowReceiveBufferRegHigh_1 (ARM_UART1_BASE + UARTShadowReceiveBufferRegHigh_Offset_1 )
-#define UARTShadowTransmitHoldingRegLow_1 (ARM_UART1_BASE + UARTShadowTransmitHoldingRegLow_Offset_1 )
-#define UARTShadowTransmitHoldingRegHigh_1 (ARM_UART1_BASE + UARTShadowTransmitHoldingRegHigh_Offset_1)
-#define UARTFIFOAccessReg_1 (ARM_UART1_BASE + UARTFIFOAccessReg_Offset_1 )
-#define UARTTransmitFIFOReadReg_1 (ARM_UART1_BASE + UARTTransmitFIFOReadReg_Offset_1 )
-#define UARTReceiveFIFOWriteReg_1 (ARM_UART1_BASE + UARTReceiveFIFOWriteReg_Offset_1 )
-#define UARTUARTStatusReg_1 (ARM_UART1_BASE + UARTUARTStatusReg_Offset_1 )
-#define UARTTransmitFIFOLevelReg_1 (ARM_UART1_BASE + UARTTransmitFIFOLevelReg_Offset_1 )
-#define UARTReceiveFIFOLevelReg_1 (ARM_UART1_BASE + UARTReceiveFIFOLevelReg_Offset_1 )
-#define UARTSoftwareResetReg_1 (ARM_UART1_BASE + UARTSoftwareResetReg_Offset_1 )
-#define UARTShadowRequestToSendReg_1 (ARM_UART1_BASE + UARTShadowRequestToSendReg_Offset_1 )
-#define UARTShadowBreakControlReg_1 (ARM_UART1_BASE + UARTShadowBreakControlReg_Offset_1 )
-#define UARTShadowDMAModeReg_1 (ARM_UART1_BASE + UARTShadowDMAModeReg_Offset_1 )
-#define UARTShadowFIFOEnableReg_1 (ARM_UART1_BASE + UARTShadowFIFOEnableReg_Offset_1 )
-#define UARTShadowRCVRTriggerReg_1 (ARM_UART1_BASE + UARTShadowRCVRTriggerReg_Offset_1 )
-#define UARTShadowTXEmptyTriggerReg_1 (ARM_UART1_BASE + UARTShadowTXEmptyTriggerReg_Offset_1 )
-#define UARTHaltTXReg_1 (ARM_UART1_BASE + UARTHaltTXReg_Offset_1 )
-#define UARTDMASAReg_1 (ARM_UART1_BASE + UARTDMASAReg_Offset_1 )
-#define UARTCIDReg_1 (ARM_UART1_BASE + UARTCIDReg_Offset_1 )
-#define UARTCVReg_1 (ARM_UART1_BASE + UARTCVReg_Offset_1 )
-#define UARTPIDReg_1 (ARM_UART1_BASE + UARTPIDReg_Offset_1 )
-
-#define UART_RBR_1 (ARM_UART1_BASE + UARTReceiveBufferReg_Offset_1 )
-#define UART_THR_1 (ARM_UART1_BASE + UARTTransmitHoldingReg_Offset_1 )
-#define UART_DLL_1 (ARM_UART1_BASE + UARTDivisorLatchLow_Offset_1 )
-#define UART_IER_1 (ARM_UART1_BASE + UARTInterruptEnableReg_Offset_1 )
-#define UART_DLH_1 (ARM_UART1_BASE + UARTDivisorLatchHigh_Offset_1 )
-#define UART_IIR_1 (ARM_UART1_BASE + UARTInterruptIdentificationReg_Offset_1 )
-#define UART_FCR_1 (ARM_UART1_BASE + UARTFIFOControlReg_Offset_1 )
-#define UART_LCR_1 (ARM_UART1_BASE + UARTLineControlReg_Offset_1 )
-#define UART_MCR_1 (ARM_UART1_BASE + UARTModemControlReg_Offset_1 )
-#define UART_LSR_1 (ARM_UART1_BASE + UARTLineStatusReg_Offset_1 )
-#define UART_MSR_1 (ARM_UART1_BASE + UARTModemStatusReg_Offset_1 )
-#define UART_SCR_1 (ARM_UART1_BASE + UARTScratchpadReg_Offset_1 )
-#define UARTPING_1BIT_WR_1 (UART_LCR_1)
-#define CC_UART_APB_DATA_WIDTH_1 32
-#define CC_UART_MAX_APB_DATA_WIDTH_1 32
-#define CC_UART_FIFO_MODE_1 16
-#define CC_UART_MEM_SELECT_1 1
-#define CC_UART_MEM_MODE_1 0
-#define CC_UART_CLOCK_MODE_1 1
-#define CC_UART_AFCE_MODE_1 1
-#define CC_UART_THRE_MODE_1 1
-#define CC_UART_SIR_MODE_1 0
-#define CC_UART_CLK_GATE_EN_1 1
-#define CC_UART_FIFO_ACCESS_1 1
-#define CC_UART_DMA_EXTRA_1 0
-#define CC_UART_DMA_POL_1 1
-#define CC_UART_SIR_LP_MODE_1 0
-#define CC_UART_DEBUG_1 0
-#define CC_UART_BAUD_CLK_1 0
-#define CC_UART_ADDITIONAL_FEATURES_1 1
-#define CC_UART_FIFO_STAT_1 1
-#define CC_UART_SHADOW_1 1
-#define CC_UART_ADD_ENCODED_PARAMS_1 0
-#define CC_UART_LATCH_MODE_1 0
-#define CC_UART_ADDR_SLICE_LHS_1 8
-#define CC_UART_COMP_VERSION_1 0x3330362a
-
-#define UART_DLS_8 0x03
-#define UART_RT_HALF (0x02 << 6)
-#define UART_TET_QUARTER (0x02 << 4)
-#define UART_XFIFOR (0x01 << 2)
-#define UART_RFIFOR (0x01 << 1)
-#define UART_FIFOE (0x01)
-#define UART_TEMT (0x01 << 6)
-#define UART_DR (0x01)
-
-#endif /* __ASM_ARCH_ARM_UART1_H */
-
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_uart2.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_uart2.h
deleted file mode 100644
index 4bd848a38f..0000000000
--- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_uart2.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * include/asm-arm/arch-spc300/arm_uart2.h
- *
- * Copyright (C) 2009 SPiDCOM Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_ARM_UART2_H
-#define __ASM_ARCH_ARM_UART2_H
-
-#ifndef ARM_UART2_BASE
- #error "ARM_UART2_BASE macro needs to be defined before including file arm_uart2.h"
-#endif
-
-#define UARTReceiveBufferReg_Offset_2 0x00
-#define UARTTransmitHoldingReg_Offset_2 0x00
-#define UARTDivisorLatchLow_Offset_2 0x00
-#define UARTInterruptEnableReg_Offset_2 0x04
-#define UARTDivisorLatchHigh_Offset_2 0x04
-#define UARTInterruptIdentificationReg_Offset_2 0x08
-#define UARTFIFOControlReg_Offset_2 0x08
-#define UARTLineControlReg_Offset_2 0x0C
-#define UARTModemControlReg_Offset_2 0x10
-#define UARTLineStatusReg_Offset_2 0x14
-#define UARTModemStatusReg_Offset_2 0x18
-
-#define UARTScratchpadReg_Offset_2 0x1C
-
-#define UARTShadowReceiveBufferRegLow_Offset_2 0x30
-
-#define UARTShadowReceiveBufferRegHigh_Offset_2 0x6C
-
-#define UARTShadowTransmitHoldingRegLow_Offset_2 0x30
-
-#define UARTShadowTransmitHoldingRegHigh_Offset_2 0x6C
-
-#define UARTFIFOAccessReg_Offset_2 0x70
-
-#define UARTTransmitFIFOReadReg_Offset_2 0x74
-
-#define UARTReceiveFIFOWriteReg_Offset_2 0x78
-
-#define UARTUARTStatusReg_Offset_2 0x7C
-
-#define UARTTransmitFIFOLevelReg_Offset_2 0x80
-
-#define UARTReceiveFIFOLevelReg_Offset_2 0x84
-
-#define UARTSoftwareResetReg_Offset_2 0x88
-
-#define UARTShadowRequestToSendReg_Offset_2 0x8C
-
-#define UARTShadowBreakControlReg_Offset_2 0x90
-
-#define UARTShadowDMAModeReg_Offset_2 0x94
-
-#define UARTShadowFIFOEnableReg_Offset_2 0x98
-
-#define UARTShadowRCVRTriggerReg_Offset_2 0x9C
-
-#define UARTShadowTXEmptyTriggerReg_Offset_2 0xA0
-
-#define UARTHaltTXReg_Offset_2 0xA4
-
-#define UARTDMASAReg_Offset_2 0xA8
-
-#define UARTCIDReg_Offset_2 0xF4
-
-#define UARTCVReg_Offset_2 0xF8
-
-#define UARTPIDReg_Offset_2 0xFC
-
-#define UARTReceiveBufferReg_2 (ARM_UART2_BASE + UARTReceiveBufferReg_Offset_2 )
-#define UARTTransmitHoldingReg_2 (ARM_UART2_BASE + UARTTransmitHoldingReg_Offset_2 )
-#define UARTDivisorLatchLow_2 (ARM_UART2_BASE + UARTDivisorLatchLow_Offset_2 )
-#define UARTInterruptEnableReg_2 (ARM_UART2_BASE + UARTInterruptEnableReg_Offset_2 )
-#define UARTDivisorLatchHigh_2 (ARM_UART2_BASE + UARTDivisorLatchHigh_Offset_2 )
-#define UARTInterruptIdentificationReg_2 (ARM_UART2_BASE + UARTInterruptIdentificationReg_Offset_2 )
-#define UARTFIFOControlReg_2 (ARM_UART2_BASE + UARTFIFOControlReg_Offset_2 )
-#define UARTLineControlReg_2 (ARM_UART2_BASE + UARTLineControlReg_Offset_2 )
-#define UARTModemControlReg_2 (ARM_UART2_BASE + UARTModemControlReg_Offset_2 )
-#define UARTLineStatusReg_2 (ARM_UART2_BASE + UARTLineStatusReg_Offset_2 )
-#define UARTModemStatusReg_2 (ARM_UART2_BASE + UARTModemStatusReg_Offset_2 )
-#define UARTScratchpadReg_2 (ARM_UART2_BASE + UARTScratchpadReg_Offset_2 )
-#define UARTShadowReceiveBufferRegLow_2 (ARM_UART2_BASE + UARTShadowReceiveBufferRegLow_Offset_2 )
-#define UARTShadowReceiveBufferRegHigh_2 (ARM_UART2_BASE + UARTShadowReceiveBufferRegHigh_Offset_2 )
-#define UARTShadowTransmitHoldingRegLow_2 (ARM_UART2_BASE + UARTShadowTransmitHoldingRegLow_Offset_2 )
-#define UARTShadowTransmitHoldingRegHigh_2 (ARM_UART2_BASE + UARTShadowTransmitHoldingRegHigh_Offset_2)
-#define UARTFIFOAccessReg_2 (ARM_UART2_BASE + UARTFIFOAccessReg_Offset_2 )
-#define UARTTransmitFIFOReadReg_2 (ARM_UART2_BASE + UARTTransmitFIFOReadReg_Offset_2 )
-#define UARTReceiveFIFOWriteReg_2 (ARM_UART2_BASE + UARTReceiveFIFOWriteReg_Offset_2 )
-#define UARTUARTStatusReg_2 (ARM_UART2_BASE + UARTUARTStatusReg_Offset_2 )
-#define UARTTransmitFIFOLevelReg_2 (ARM_UART2_BASE + UARTTransmitFIFOLevelReg_Offset_2 )
-#define UARTReceiveFIFOLevelReg_2 (ARM_UART2_BASE + UARTReceiveFIFOLevelReg_Offset_2 )
-#define UARTSoftwareResetReg_2 (ARM_UART2_BASE + UARTSoftwareResetReg_Offset_2 )
-#define UARTShadowRequestToSendReg_2 (ARM_UART2_BASE + UARTShadowRequestToSendReg_Offset_2 )
-#define UARTShadowBreakControlReg_2 (ARM_UART2_BASE + UARTShadowBreakControlReg_Offset_2 )
-#define UARTShadowDMAModeReg_2 (ARM_UART2_BASE + UARTShadowDMAModeReg_Offset_2 )
-#define UARTShadowFIFOEnableReg_2 (ARM_UART2_BASE + UARTShadowFIFOEnableReg_Offset_2 )
-#define UARTShadowRCVRTriggerReg_2 (ARM_UART2_BASE + UARTShadowRCVRTriggerReg_Offset_2 )
-#define UARTShadowTXEmptyTriggerReg_2 (ARM_UART2_BASE + UARTShadowTXEmptyTriggerReg_Offset_2 )
-#define UARTHaltTXReg_2 (ARM_UART2_BASE + UARTHaltTXReg_Offset_2 )
-#define UARTDMASAReg_2 (ARM_UART2_BASE + UARTDMASAReg_Offset_2 )
-#define UARTCIDReg_2 (ARM_UART2_BASE + UARTCIDReg_Offset_2 )
-#define UARTCVReg_2 (ARM_UART2_BASE + UARTCVReg_Offset_2 )
-#define UARTPIDReg_2 (ARM_UART2_BASE + UARTPIDReg_Offset_2 )
-
-#define UART_RBR_2 (ARM_UART2_BASE + UARTReceiveBufferReg_Offset_2 )
-#define UART_THR_2 (ARM_UART2_BASE + UARTTransmitHoldingReg_Offset_2 )
-#define UART_DLL_2 (ARM_UART2_BASE + UARTDivisorLatchLow_Offset_2 )
-#define UART_IER_2 (ARM_UART2_BASE + UARTInterruptEnableReg_Offset_2 )
-#define UART_DLH_2 (ARM_UART2_BASE + UARTDivisorLatchHigh_Offset_2 )
-#define UART_IIR_2 (ARM_UART2_BASE + UARTInterruptIdentificationReg_Offset_2 )
-#define UART_FCR_2 (ARM_UART2_BASE + UARTFIFOControlReg_Offset_2 )
-#define UART_LCR_2 (ARM_UART2_BASE + UARTLineControlReg_Offset_2 )
-#define UART_MCR_2 (ARM_UART2_BASE + UARTModemControlReg_Offset_2 )
-#define UART_LSR_2 (ARM_UART2_BASE + UARTLineStatusReg_Offset_2 )
-#define UART_MSR_2 (ARM_UART2_BASE + UARTModemStatusReg_Offset_2 )
-#define UART_SCR_2 (ARM_UART2_BASE + UARTScratchpadReg_Offset_2 )
-#define UARTPING_1BIT_WR_2 (UART_LCR_2)
-#define CC_UART_APB_DATA_WIDTH_2 32
-#define CC_UART_MAX_APB_DATA_WIDTH_2 32
-#define CC_UART_FIFO_MODE_2 16
-#define CC_UART_MEM_SELECT_2 1
-#define CC_UART_MEM_MODE_2 0
-#define CC_UART_CLOCK_MODE_2 1
-#define CC_UART_AFCE_MODE_2 1
-#define CC_UART_THRE_MODE_2 1
-#define CC_UART_SIR_MODE_2 0
-#define CC_UART_CLK_GATE_EN_2 1
-#define CC_UART_FIFO_ACCESS_2 1
-#define CC_UART_DMA_EXTRA_2 0
-#define CC_UART_DMA_POL_2 1
-#define CC_UART_SIR_LP_MODE_2 0
-#define CC_UART_DEBUG_2 0
-#define CC_UART_BAUD_CLK_2 0
-#define CC_UART_ADDITIONAL_FEATURES_2 1
-#define CC_UART_FIFO_STAT_2 1
-#define CC_UART_SHADOW_2 1
-#define CC_UART_ADD_ENCODED_PARAMS_2 0
-#define CC_UART_LATCH_MODE_2 0
-#define CC_UART_ADDR_SLICE_LHS_2 8
-#define CC_UART_COMP_VERSION_2 0x3330362a
-
-#endif /* __ASM_ARCH_ARM_UART2_H */
-
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_wdt.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_wdt.h
deleted file mode 100644
index 27253a9228..0000000000
--- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_wdt.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * include/asm-arm/arch-spc300/arm_wdt.h
- *
- * Copyright (C) 2009 SPiDCOM Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_ARM_WDT_H
-#define __ASM_ARCH_ARM_WDT_H
-
-#ifndef ARM_WDT_BASE
- #error "ARM_WDT_BASE macro needs to be defined before including file arm_wdt.h"
-#endif
-
-#define WDTControlReg_Offset 0x00
-#define WDTTimeoutRangeReg_Offset 0x04
-#define WDTCurrentCounterValueReg_Offset 0x08
-#define WDTCounterResetReg_Offset 0x0C
-#define WDTStatReg_Offset 0x10
-#define WDTEOIReg_Offset 0x14
-#define WDTVIDReg_Offset 0x18
-
-#define WDTCOMP_PARAMS_5_Offset 0xe4
-#define WDTCOMP_PARAMS_4_Offset 0xe8
-#define WDTCOMP_PARAMS_3_Offset 0xec
-#define WDTCOMP_PARAMS_2_Offset 0xf0
-#define WDTCOMP_PARAMS_1_Offset 0xf4
-#define WDTCOMP_VERSION_Offset 0xf8
-#define WDTCOMP_TYPE_Offset 0xfc
-
-#ifdef QUICKSTART_WDT
-#define WDTControlReg (ARM_WDT_BASE + WDTControlReg_Offset )
-#define WDTTimeoutRangeReg (ARM_WDT_BASE + WDTTimeoutRangeReg_Offset )
-#define WDTCurrentCounterValueReg (ARM_WDT_BASE + WDTCurrentCounterValueReg_Offset)
-#define WDTCounterResetReg (ARM_WDT_BASE + WDTCounterResetReg_Offset )
-#define WDTStatReg (ARM_WDT_BASE + WDTStatReg_Offset )
-#define WDTEOIReg (ARM_WDT_BASE + WDTEOIReg_Offset )
-#define WDTVIDReg (ARM_WDT_BASE + WDTVIDReg_Offset )
-#endif
-
-#define WDT_CR (ARM_WDT_BASE + WDTControlReg_Offset )
-#define WDT_TORR (ARM_WDT_BASE + WDTTimeoutRangeReg_Offset )
-#define WDT_CCVR (ARM_WDT_BASE + WDTCurrentCounterValueReg_Offset)
-#define WDT_CRR (ARM_WDT_BASE + WDTCounterResetReg_Offset )
-#define WDT_STAT (ARM_WDT_BASE + WDTStatReg_Offset )
-#define WDT_EOI (ARM_WDT_BASE + WDTEOIReg_Offset )
-#define WDT_VID (ARM_WDT_BASE + WDTVIDReg_Offset )
-#define WDT_COMP_PARAMS_5 (ARM_WDT_BASE + WDTCOMP_PARAMS_5_Offset )
-#define WDT_COMP_PARAMS_4 (ARM_WDT_BASE + WDTCOMP_PARAMS_4_Offset )
-#define WDT_COMP_PARAMS_3 (ARM_WDT_BASE + WDTCOMP_PARAMS_3_Offset )
-#define WDT_COMP_PARAMS_2 (ARM_WDT_BASE + WDTCOMP_PARAMS_2_Offset )
-#define WDT_COMP_PARAMS_1 (ARM_WDT_BASE + WDTCOMP_PARAMS_1_Offset )
-#define WDT_COMP_VERSION (ARM_WDT_BASE + WDTCOMP_VERSION_Offset )
-#define WDT_COMP_TYPE (ARM_WDT_BASE + WDTCOMP_TYPE_Offset )
-
-#define WDTPING_1BIT_WR (WDT_CR )
-
-#define CC_WDT_APB_DATA_WIDTH 32
-#define CC_WDT_MAX_APB_DATA_WIDTH 32
-#define CC_WDT_CNT_WIDTH 32
-#define CC_WDT_INT_POL 1
-#define CC_WDT_RST_POL 0
-#define CC_WDT_HC_TOP 0
-#define CC_WDT_DUAL_TOP 0
-#define CC_WDT_DFLT_TOP 11
-#define CC_WDT_DFLT_TOP_INIT 0
-#define CC_WDT_USE_FIX_TOP 1
-#define CC_WDT_USER_TOP_0 0xffff
-#define CC_WDT_USER_TOP_1 0x1ffff
-#define CC_WDT_USER_TOP_2 0x3ffff
-#define CC_WDT_USER_TOP_3 0x7ffff
-#define CC_WDT_USER_TOP_4 0xfffff
-#define CC_WDT_USER_TOP_5 0x1fffff
-#define CC_WDT_USER_TOP_6 0x3fffff
-#define CC_WDT_USER_TOP_7 0x7fffff
-#define CC_WDT_USER_TOP_8 0xffffff
-#define CC_WDT_USER_TOP_9 0x1ffffff
-#define CC_WDT_USER_TOP_10 0x3ffffff
-#define CC_WDT_USER_TOP_11 0x7ffffff
-#define CC_WDT_USER_TOP_12 0xfffffff
-#define CC_WDT_USER_TOP_13 0x1fffffff
-#define CC_WDT_USER_TOP_14 0x3fffffff
-#define CC_WDT_USER_TOP_15 0x7fffffff
-#define CC_WDT_USER_TOP_INIT_0 0xffff
-#define CC_WDT_USER_TOP_INIT_1 0x1ffff
-#define CC_WDT_USER_TOP_INIT_2 0x3ffff
-#define CC_WDT_USER_TOP_INIT_3 0x7ffff
-#define CC_WDT_USER_TOP_INIT_4 0xfffff
-#define CC_WDT_USER_TOP_INIT_5 0x1fffff
-#define CC_WDT_USER_TOP_INIT_6 0x3fffff
-#define CC_WDT_USER_TOP_INIT_7 0x7fffff
-#define CC_WDT_USER_TOP_INIT_8 0xffffff
-#define CC_WDT_USER_TOP_INIT_9 0x1ffffff
-#define CC_WDT_USER_TOP_INIT_10 0x3ffffff
-#define CC_WDT_USER_TOP_INIT_11 0x7ffffff
-#define CC_WDT_USER_TOP_INIT_12 0xfffffff
-#define CC_WDT_USER_TOP_INIT_13 0x1fffffff
-#define CC_WDT_USER_TOP_INIT_14 0x3fffffff
-#define CC_WDT_USER_TOP_INIT_15 0x7fffffff
-#define CC_WDT_DFLT_RPL 0
-#define CC_WDT_HC_RPL 0
-#define CC_WDT_DFLT_RMOD 1
-#define CC_WDT_HC_RMOD 0
-#define CC_WDT_ALWAYS_EN 0
-#define CC_WDT_CLK_EN 0
-#define CC_WDT_PAUSE 1
-#define CC_WDT_TORR_WIDTH 4
-#define CC_WDT_TOP_RST 11
-#define CC_WDT_CNT_RST 0x7ffffff
-#define CC_WDT_ADDR_SLICE_LHS 8
-#define CC_WDT_VERSION_ID 0x3130332a
-
-#endif /* __ASM_ARCH_ARM_WDT_H */
-
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/boot_arm_hard.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/boot_arm_hard.h
deleted file mode 100644
index ebe5311a48..0000000000
--- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/boot_arm_hard.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * include/asm-arm/arch-spc300/boot_arm_hard.h
- *
- * Copyright (C) 2009 SPiDCOM Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_BOOT_ARM_HARD_H
-#define __ASM_ARCH_BOOT_ARM_HARD_H
-
-extern void(*adr_reset)(void);
-extern void(*adr_undefined_instruction)(void);
-extern void(*adr_software_interrupt)(void);
-extern void(*adr_abort_prefetch)(void);
-extern void(*adr_abort_data)(void);
-extern void(*adr_irq)(void);
-extern void(*adr_fiq)(void);
-extern void(*adr_stack)(void);
-
-extern int* test_status;
-
-
-#define ARM_ENABLE_ICACHE \
- asm(" \
- MRC p15,0,R0,c1,c0,0 \n\
- ORR R0,R0,#0x1000 \n\
- MCR p15,0,R0,c1,c0,0");
-
-#define ARM_ENABLE_DCACHE \
- asm(" \
- MRC p15,0,R0,c1,c0,0 \n\
- ORR R0,R0,#0x4 \n\
- MCR p15,0,R0,c1,c0,0");
-
-#define ARM_ENABLE_IRQ \
- asm(" \
- MRS R0, CPSR \n\
- BIC R0, #0x80 \n\
- MSR CPSR_c, R0");
-
-#define ARM_DISABLE_IRQ \
- asm(" \
- MRS R0, CPSR \n\
- ORR R0, #0x80 \n\
- MSR CPSR_c, R0");
-
-#define ARM_ENABLE_FIQ \
- asm(" \
- MRS R0, CPSR \n\
- BIC R0, #0x40 \n\
- MSR CPSR_c, R0");
-
-#define ARM_DISABLE_FIQ \
- asm(" \
- MRS R0, CPSR \n\
- ORR R0, #0x40 \n\
- MSR CPSR_c, R0");
-
-
-//#define ARM_ENABLE_IRQ asm("CPSIE i");
-
-#define END_OF_INTERRUPT asm("SUBS PC, R14, #4");
-
-#define ARM_STANDBY \
- asm(" \n\
- start_arm_standby: \n\
- MCR p15,0,R0,c7,c0,4 \n\
- end_arm_standby: \n\
- ");
-
-#define TEST_OK 0xabcdef01
-
-#define TEST_BAD 0x55555555
-
-#define Write32( adr, data ) *((volatile int*)(adr))= data
-
-#define Read32( adr ) (*(volatile int*)(adr))
-
-#define Write8( adr, data ) *((volatile unsigned char *)(adr))= data
-#define Read8( adr ) (*(volatile unsigned char *)(adr))
-
-#define Write16( adr, data ) *((volatile short int *)(adr))= data
-#define Read16( adr ) (*(volatile short int *)(adr))
-
-#define XSTR(x) STR(x)
-#define STR(x) #x
-
-#endif /* __ASM_ARCH_BOOT_ARM_HARD_H */
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/bus_sys.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/bus_sys.h
deleted file mode 100644
index b0ce550a14..0000000000
--- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/bus_sys.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * include/asm-arm/arch-spc300/bus_sys.h
- *
- * Copyright (C) 2009 SPiDCOM Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_BUS_SYS_H
-#define __ASM_ARCH_BUS_SYS_H
-
-#define SYS_APB_BASE (0xc8000000)
-#include "sys_apb.h"
-
-#define SPI_BASE (0xf0000000)
-#include "spi.h"
-
-#define SPI_BASE_DIR (0x30000000)
-
-#define ARM_APB_BASE (0xc0000000)
-#include "arm_apb.h"
-
-#define GPDMA_BASE (0xf8000000)
-#include "gpdma.h"
-
-#define PCM_BASE (0xE8000000)
-#include "pcm.h"
-
-#define TCU_BASE (0x20000000)
-
-#define MIU_REG_BASE (0xC8050000)
-#define MIU_ATOP_REG_BASE (0xC8060000)
-#include "miu.h"
-
-#define SDRAM_CTRL_BASE (0xE0000000)
-#include "sdram.h"
-
-#define ETHERNET_CTRL_BASE (0xD0000000)
-#include "ethernet_ctrl.h"
-
-#endif /* __ASM_ARCH_BUS_SYS_H */
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/dsp.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/dsp.h
deleted file mode 100644
index cb50596e4e..0000000000
--- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/dsp.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * include/asm-arm/arch-spc300/dsp.h
- *
- * Copyright (C) 2009 SPiDCOM Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_DSP_H
-#define __ASM_ARCH_DSP_H
-
-#define DSP_PRATIC_BASE (0xA0001000)
-#define DSP_PRATIC_STA_LOCAL_TIMER (0x10)
-
-#endif /* __ASM_ARCH_DSP_H */
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/ethernet_ctrl.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/ethernet_ctrl.h
deleted file mode 100644
index f532b9994d..0000000000
--- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/ethernet_ctrl.h
+++ /dev/null
@@ -1,748 +0,0 @@
-/*
- * include/asm-arm/arch-spc300/ethernet_ctrl.h
- *
- * Copyright (C) 2009 SPiDCOM Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_ETHERNET_CTRL_H
-#define __ASM_ARCH_ETHERNET_CTRL_H
-
-#define GMAC_BaseAddress (ETHERNET_CTRL_BASE)
-
-/* Register Register0 */
-/* MAC Configuration Register */
-#define Register0 (GMAC_BaseAddress )
-#define Register0_RegisterSize 32
-#define Register0_RegisterResetValue 0x0
-#define Register0_RegisterResetMask 0x0
-
-
-/* Register Register1 */
-/* MAC Frame Filter */
-#define Register1 (GMAC_BaseAddress + 0x4)
-#define Register1_RegisterSize 32
-#define Register1_RegisterResetValue 0x0
-#define Register1_RegisterResetMask 0x0
-
-/* Register Register2 */
-/* MAC hash table high Filter */
-#define Register2 (GMAC_BaseAddress + 0x8)
-#define Register2_RegisterSize 32
-#define Register2_RegisterResetValue 0x0
-#define Register2_RegisterResetMask 0x0
-/* Register Register3 */
-/* MAC hash table low Filter */
-#define Register3 (GMAC_BaseAddress + 0xC)
-#define Register3_RegisterSize 32
-#define Register3_RegisterResetValue 0x0
-#define Register3_RegisterResetMask 0x0
-
-/* Register Register4 */
-/* GMII Address Register */
-#define Register4 (GMAC_BaseAddress + 0x10)
-#define Register4_RegisterSize 32
-#define Register4_RegisterResetValue 0x0
-#define Register4_RegisterResetMask 0x0
-
-/* Register Register5 */
-/* GMII Data Register */
-#define Register5 (GMAC_BaseAddress + 0x14)
-#define Register5_RegisterSize 32
-#define Register5_RegisterResetValue 0x0
-#define Register5_RegisterResetMask 0x0
-
-/* Register Register6 */
-/* Flow Control Register */
-#define Register6 (GMAC_BaseAddress + 0x18)
-#define Register6_RegisterSize 32
-#define Register6_RegisterResetValue 0x0
-#define Register6_RegisterResetMask 0x0
-
-
-/* Register Register7 */
-/* VLAN Tag Register */
-#define Register7 (GMAC_BaseAddress + 0x1c)
-#define Register7_RegisterSize 32
-#define Register7_RegisterResetValue 0x0
-#define Register7_RegisterResetMask 0x0
-
-/* Register Register8 */
-/* Version Register */
-#define Register8 (GMAC_BaseAddress + 0x20)
-#define Register8_RegisterSize 32
-#define Register8_RegisterResetValue 0x33
-#define Register8_RegisterResetMask 0x0
-
-/* Register Register14 */
-/* Interrupt Register */
-#define Register14 (GMAC_BaseAddress + 0x38)
-#define Register14_RegisterSize 32
-#define Register14_RegisterResetValue 0x0
-#define Register14_RegisterResetMask 0x0
-
-/* Register Register15 */
-/* Interrupt Mask Register */
-#define Register15 (GMAC_BaseAddress + 0x3c)
-#define Register15_RegisterSize 32
-#define Register15_RegisterResetValue 0x0
-#define Register15_RegisterResetMask 0x0
-
-/* Register Register16 */
-/* MAC Address0 High Register */
-#define Register16 (GMAC_BaseAddress + 0x40)
-#define Register16_RegisterSize 32
-#define Register16_RegisterResetValue 0x8000ffff
-#define Register16_RegisterResetMask 0x0
-
-/* Register Register17 */
-/* MAC Address0 Low Register */
-#define Register17 (GMAC_BaseAddress + 0x44)
-#define Register17_RegisterSize 32
-#define Register17_RegisterResetValue 0xffffffff
-#define Register17_RegisterResetMask 0x0
-
-/* Register Register18 */
-/* MAC Address1 High Register */
-#define Register18 (GMAC_BaseAddress + 0x48)
-#define Register18_RegisterSize 32
-#define Register18_RegisterResetValue 0xffff
-#define Register18_RegisterResetMask 0x0
-
-/* Register Register19 */
-/* MAC Address1 Low Register */
-#define Register19 (GMAC_BaseAddress + 0x4c)
-#define Register19_RegisterSize 32
-#define Register19_RegisterResetValue 0xffffffff
-#define Register19_RegisterResetMask 0x0
-
-
-/* Register Register20 */
-/* MAC Address2 High Register */
-#define Register20 (GMAC_BaseAddress + 0x50)
-#define Register20_RegisterSize 32
-#define Register20_RegisterResetValue 0xffff
-#define Register20_RegisterResetMask 0x0
-
-/* Register Register21 */
-/* MAC Address2 Low Register */
-#define Register21 (GMAC_BaseAddress + 0x54)
-#define Register21_RegisterSize 32
-#define Register21_RegisterResetValue 0xffffffff
-#define Register21_RegisterResetMask 0x0
-
-/* Register Register22 */
-/* MAC Address3 High Register */
-#define Register22 (GMAC_BaseAddress + 0x58)
-#define Register22_RegisterSize 32
-#define Register22_RegisterResetValue 0xffff
-#define Register22_RegisterResetMask 0x0
-
-/* Register Register23 */
-/* MAC Address3 Low Register */
-#define Register23 (GMAC_BaseAddress + 0x5c)
-#define Register23_RegisterSize 32
-#define Register23_RegisterResetValue 0xffffffff
-#define Register23_RegisterResetMask 0x0
-
-/* Register Register24 */
-/* MAC Address4 High Register */
-#define Register24 (GMAC_BaseAddress + 0x60)
-#define Register24_RegisterSize 32
-#define Register24_RegisterResetValue 0xffff
-#define Register24_RegisterResetMask 0x0
-
-/* Register Register25 */
-/* MAC Address4 Low Register */
-#define Register25 (GMAC_BaseAddress + 0x64)
-#define Register25_RegisterSize 32
-#define Register25_RegisterResetValue 0xffffffff
-#define Register25_RegisterResetMask 0x0
-
-/* Register Register26 */
-/* MAC Address5 High Register */
-#define Register26 (GMAC_BaseAddress + 0x68)
-#define Register26_RegisterSize 32
-#define Register26_RegisterResetValue 0xffff
-#define Register26_RegisterResetMask 0x0
-
-/* Register Register27 */
-/* MAC Address5 Low Register */
-#define Register27 (GMAC_BaseAddress + 0x6c)
-#define Register27_RegisterSize 32
-#define Register27_RegisterResetValue 0xffffffff
-#define Register27_RegisterResetMask 0x0
-
-/* Register Register28 */
-/* MAC Address6 High Register */
-#define Register28 (GMAC_BaseAddress + 0x70)
-#define Register28_RegisterSize 32
-#define Register28_RegisterResetValue 0xffff
-#define Register28_RegisterResetMask 0x0
-
-/* Register Register29 */
-/* MAC Address6 Low Register */
-#define Register29 (GMAC_BaseAddress + 0x74)
-#define Register29_RegisterSize 32
-#define Register29_RegisterResetValue 0xffffffff
-#define Register29_RegisterResetMask 0x0
-
-/* Register Field information for Register29 */
-
-/* Register Register30 */
-/* MAC Address7 High Register */
-#define Register30 (GMAC_BaseAddress + 0x78)
-#define Register30_RegisterSize 32
-#define Register30_RegisterResetValue 0xffff
-#define Register30_RegisterResetMask 0x0
-
-/* Register Register31 */
-/* MAC Address7 Low Register */
-#define Register31 (GMAC_BaseAddress + 0x7c)
-#define Register31_RegisterSize 32
-#define Register31_RegisterResetValue 0xffffffff
-#define Register31_RegisterResetMask 0x0
-
-/* Register Register64 */
-/* mmc_cntrl */
-#define Register64 (GMAC_BaseAddress + 0x100)
-#define Register64_RegisterSize 32
-#define Register64_RegisterResetValue 0x0
-#define Register64_RegisterResetMask 0x0
-
-/* Register Register65 */
-/* mmc_intr_rx */
-#define Register65 (GMAC_BaseAddress + 0x104)
-#define Register65_RegisterSize 32
-#define Register65_RegisterResetValue 0x0
-#define Register65_RegisterResetMask 0x0
-
-/* Register Register66 */
-/* mmc_intr_tx */
-#define Register66 (GMAC_BaseAddress + 0x108)
-#define Register66_RegisterSize 32
-#define Register66_RegisterResetValue 0x0
-#define Register66_RegisterResetMask 0x0
-
-/* Register Register67 */
-/* mmc_intr_mask_rx */
-#define Register67 (GMAC_BaseAddress + 0x10c)
-#define Register67_RegisterSize 32
-#define Register67_RegisterResetValue 0x0
-#define Register67_RegisterResetMask 0x0
-
-/* Register Register68 */
-/* mmc_intr_mask_tx */
-#define Register68 (GMAC_BaseAddress + 0x110)
-#define Register68_RegisterSize 32
-#define Register68_RegisterResetValue 0x0
-#define Register68_RegisterResetMask 0x0
-
-/* Register Register69 */
-/* txoctetcount_gb */
-#define Register69 (GMAC_BaseAddress + 0x114)
-#define Register69_RegisterSize 32
-#define Register69_RegisterResetValue 0x0
-#define Register69_RegisterResetMask 0x0
-
-
-/* Register Register70 */
-/* txfrmecount_gb */
-#define Register70 (GMAC_BaseAddress + 0x118)
-#define Register70_RegisterSize 32
-#define Register70_RegisterResetValue 0x0
-#define Register70_RegisterResetMask 0x0
-
-
-/* Register Register71 */
-/* txbroadcastframes_g */
-#define Register71 (GMAC_BaseAddress + 0x11c)
-#define Register71_RegisterSize 32
-#define Register71_RegisterResetValue 0x0
-#define Register71_RegisterResetMask 0x0
-
-
-/* Register Register72 */
-/* txmulticastframes_g */
-#define Register72 (GMAC_BaseAddress + 0x120)
-#define Register72_RegisterSize 32
-#define Register72_RegisterResetValue 0x0
-#define Register72_RegisterResetMask 0x0
-
-
-/* Register Register73 */
-/* tx64octets_gb */
-#define Register73 (GMAC_BaseAddress + 0x124)
-#define Register73_RegisterSize 32
-#define Register73_RegisterResetValue 0x0
-#define Register73_RegisterResetMask 0x0
-
-
-/* Register Register74 */
-/* tx65to127octets_gb */
-#define Register74 (GMAC_BaseAddress + 0x128)
-#define Register74_RegisterSize 32
-#define Register74_RegisterResetValue 0x0
-#define Register74_RegisterResetMask 0x0
-
-
-/* Register Register75 */
-/* tx128to255octets_gb */
-#define Register75 (GMAC_BaseAddress + 0x12c)
-#define Register75_RegisterSize 32
-#define Register75_RegisterResetValue 0x0
-#define Register75_RegisterResetMask 0x0
-
-/* Register Register76 */
-/* tx256to511octets_gb */
-#define Register76 (GMAC_BaseAddress + 0x130)
-#define Register76_RegisterSize 32
-#define Register76_RegisterResetValue 0x0
-#define Register76_RegisterResetMask 0x0
-
-/* Register Register77 */
-/* tx512to1023octets_gb */
-#define Register77 (GMAC_BaseAddress + 0x134)
-#define Register77_RegisterSize 32
-#define Register77_RegisterResetValue 0x0
-#define Register77_RegisterResetMask 0x0
-
-
-/* Register Register78 */
-/* tx1024tomaxoctets_gb */
-#define Register78 (GMAC_BaseAddress + 0x138)
-#define Register78_RegisterSize 32
-#define Register78_RegisterResetValue 0x0
-#define Register78_RegisterResetMask 0x0
-
-
-/* Register Register79 */
-/* txunicastframes_gb */
-#define Register79 (GMAC_BaseAddress + 0x13c)
-#define Register79_RegisterSize 32
-#define Register79_RegisterResetValue 0x0
-#define Register79_RegisterResetMask 0x0
-
-
-/* Register Register80 */
-/* txmulticastframes_gb */
-#define Register80 (GMAC_BaseAddress + 0x140)
-#define Register80_RegisterSize 32
-#define Register80_RegisterResetValue 0x0
-#define Register80_RegisterResetMask 0x0
-
-
-/* Register Register81 */
-/* txbroadcastframes_gb */
-#define Register81 (GMAC_BaseAddress + 0x144)
-#define Register81_RegisterSize 32
-#define Register81_RegisterResetValue 0x0
-#define Register81_RegisterResetMask 0x0
-
-
-/* Register Register82 */
-/* txunderflowerror */
-#define Register82 (GMAC_BaseAddress + 0x148)
-#define Register82_RegisterSize 32
-#define Register82_RegisterResetValue 0x0
-#define Register82_RegisterResetMask 0x0
-
-/* Register Register83 */
-/* txsingelcol_g */
-#define Register83 (GMAC_BaseAddress + 0x14c)
-#define Register83_RegisterSize 32
-#define Register83_RegisterResetValue 0x0
-#define Register83_RegisterResetMask 0x0
-
-/* Register Register84 */
-/* txmultilcol_g */
-#define Register84 (GMAC_BaseAddress + 0x150)
-#define Register84_RegisterSize 32
-#define Register84_RegisterResetValue 0x0
-#define Register84_RegisterResetMask 0x0
-
-/* Register Register85 */
-/* txdeferred */
-#define Register85 (GMAC_BaseAddress + 0x154)
-#define Register85_RegisterSize 32
-#define Register85_RegisterResetValue 0x0
-#define Register85_RegisterResetMask 0x0
-
-/* Register Register86 */
-/* txlatecol */
-#define Register86 (GMAC_BaseAddress + 0x158)
-#define Register86_RegisterSize 32
-#define Register86_RegisterResetValue 0x0
-#define Register86_RegisterResetMask 0x0
-
-/* Register Register87 */
-/* txexesscol */
-#define Register87 (GMAC_BaseAddress + 0x15c)
-#define Register87_RegisterSize 32
-#define Register87_RegisterResetValue 0x0
-#define Register87_RegisterResetMask 0x0
-
-/* Register Register88 */
-/* txcarriererror */
-#define Register88 (GMAC_BaseAddress + 0x160)
-#define Register88_RegisterSize 32
-#define Register88_RegisterResetValue 0x0
-#define Register88_RegisterResetMask 0x0
-
-/* Register Register89 */
-/* txoctetcount_g */
-#define Register89 (GMAC_BaseAddress + 0x164)
-#define Register89_RegisterSize 32
-#define Register89_RegisterResetValue 0x0
-#define Register89_RegisterResetMask 0x0
-
-/* Register Register90 */
-/* txframecount_g */
-#define Register90 (GMAC_BaseAddress + 0x168)
-#define Register90_RegisterSize 32
-#define Register90_RegisterResetValue 0x0
-#define Register90_RegisterResetMask 0x0
-
-/* Register Register91 */
-/* txexcessdef */
-#define Register91 (GMAC_BaseAddress + 0x16c)
-#define Register91_RegisterSize 32
-#define Register91_RegisterResetValue 0x0
-#define Register91_RegisterResetMask 0x0
-
-/* Register Register92 */
-/* txpauseframes */
-#define Register92 (GMAC_BaseAddress + 0x170)
-#define Register92_RegisterSize 32
-#define Register92_RegisterResetValue 0x0
-#define Register92_RegisterResetMask 0x0
-
-/* Register Register93 */
-/* txvlanframes_g */
-#define Register93 (GMAC_BaseAddress + 0x174)
-#define Register93_RegisterSize 32
-#define Register93_RegisterResetValue 0x0
-#define Register93_RegisterResetMask 0x0
-
-
-/* Register Register96 */
-/* rxframecount_gb */
-#define Register96 (GMAC_BaseAddress + 0x180)
-#define Register96_RegisterSize 32
-#define Register96_RegisterResetValue 0x0
-#define Register96_RegisterResetMask 0x0
-
-/* Register Register97 */
-/* rxoctetcount_gb */
-#define Register97 (GMAC_BaseAddress + 0x184)
-#define Register97_RegisterSize 32
-#define Register97_RegisterResetValue 0x0
-#define Register97_RegisterResetMask 0x0
-
-
-/* Register Register98 */
-/* rxoctetcount_g */
-#define Register98 (GMAC_BaseAddress + 0x188)
-#define Register98_RegisterSize 32
-#define Register98_RegisterResetValue 0x0
-#define Register98_RegisterResetMask 0x0
-
-
-/* Register Register99 */
-/* rxbroadcastframes_g */
-#define Register99 (GMAC_BaseAddress + 0x18c)
-#define Register99_RegisterSize 32
-#define Register99_RegisterResetValue 0x0
-#define Register99_RegisterResetMask 0x0
-
-
-/* Register Register100 */
-/* rxmulticastframes_g */
-#define Register100 (GMAC_BaseAddress + 0x190)
-#define Register100_RegisterSize 32
-#define Register100_RegisterResetValue 0x0
-#define Register100_RegisterResetMask 0x0
-
-
-/* Register Register101 */
-/* rxcrcerror */
-#define Register101 (GMAC_BaseAddress + 0x194)
-#define Register101_RegisterSize 32
-#define Register101_RegisterResetValue 0x0
-#define Register101_RegisterResetMask 0x0
-
-
-/* Register Register102 */
-/* rxalignmenterror */
-#define Register102 (GMAC_BaseAddress + 0x198)
-#define Register102_RegisterSize 32
-#define Register102_RegisterResetValue 0x0
-#define Register102_RegisterResetMask 0x0
-
-
-/* Register Register103 */
-/* rxrunterror */
-#define Register103 (GMAC_BaseAddress + 0x19c)
-#define Register103_RegisterSize 32
-#define Register103_RegisterResetValue 0x0
-#define Register103_RegisterResetMask 0x0
-
-
-/* Register Register104 */
-/* rxjabbererror */
-#define Register104 (GMAC_BaseAddress + 0x1a0)
-#define Register104_RegisterSize 32
-#define Register104_RegisterResetValue 0x0
-#define Register104_RegisterResetMask 0x0
-
-/* End of Register Definition for Register104 */
-
-/* Register Register105 */
-/* rxundersize_g */
-#define Register105 (GMAC_BaseAddress + 0x1a4)
-#define Register105_RegisterSize 32
-#define Register105_RegisterResetValue 0x0
-#define Register105_RegisterResetMask 0x0
-
-
-/* Register Register106 */
-/* rxoversize_g */
-#define Register106 (GMAC_BaseAddress + 0x1a8)
-#define Register106_RegisterSize 32
-#define Register106_RegisterResetValue 0x0
-#define Register106_RegisterResetMask 0x0
-
-/* End of Register Definition for Register106 */
-
-/* Register Register107 */
-/* rx64octets_gb */
-#define Register107 (GMAC_BaseAddress + 0x1ac)
-#define Register107_RegisterSize 32
-#define Register107_RegisterResetValue 0x0
-#define Register107_RegisterResetMask 0x0
-
-/* End of Register Definition for Register107 */
-
-/* Register Register108 */
-/* rx65to127octets_gb */
-#define Register108 (GMAC_BaseAddress + 0x1b0)
-#define Register108_RegisterSize 32
-#define Register108_RegisterResetValue 0x0
-#define Register108_RegisterResetMask 0x0
-
-
-/* Register Register109 */
-/* rx128to255octets_gb */
-#define Register109 (GMAC_BaseAddress + 0x1b4)
-#define Register109_RegisterSize 32
-#define Register109_RegisterResetValue 0x0
-#define Register109_RegisterResetMask 0x0
-
-
-/* Register Register110 */
-/* rx256to511octets_gb */
-#define Register110 (GMAC_BaseAddress + 0x1b8)
-#define Register110_RegisterSize 32
-#define Register110_RegisterResetValue 0x0
-#define Register110_RegisterResetMask 0x0
-
-
-/* Register Register111 */
-/* rx512to1023octets_gb */
-#define Register111 (GMAC_BaseAddress + 0x1bc)
-#define Register111_RegisterSize 32
-#define Register111_RegisterResetValue 0x0
-#define Register111_RegisterResetMask 0x0
-
-
-/* Register Register112 */
-/* rx1024tomaxoctets_gb */
-#define Register112 (GMAC_BaseAddress + 0x1c0)
-#define Register112_RegisterSize 32
-#define Register112_RegisterResetValue 0x0
-#define Register112_RegisterResetMask 0x0
-
-
-/* Register Register113 */
-/* rxunicastframes_g */
-#define Register113 (GMAC_BaseAddress + 0x1c4)
-#define Register113_RegisterSize 32
-#define Register113_RegisterResetValue 0x0
-#define Register113_RegisterResetMask 0x0
-
-
-/* Register Register114 */
-/* rxlengtherror */
-#define Register114 (GMAC_BaseAddress + 0x1c8)
-#define Register114_RegisterSize 32
-#define Register114_RegisterResetValue 0x0
-#define Register114_RegisterResetMask 0x0
-
-
-/* Register Register115 */
-/* rxoutofrangetype */
-#define Register115 (GMAC_BaseAddress + 0x1cc)
-#define Register115_RegisterSize 32
-#define Register115_RegisterResetValue 0x0
-#define Register115_RegisterResetMask 0x0
-
-/* Register Register116 */
-/* rxpauseframes */
-#define Register116 (GMAC_BaseAddress + 0x1d0)
-#define Register116_RegisterSize 32
-#define Register116_RegisterResetValue 0x0
-#define Register116_RegisterResetMask 0x0
-
-/* Register Register117 */
-/* rxfifooverflow */
-#define Register117 (GMAC_BaseAddress + 0x1d4)
-#define Register117_RegisterSize 32
-#define Register117_RegisterResetValue 0x0
-#define Register117_RegisterResetMask 0x0
-
-
-/* Register Register118 */
-/* rxvlanframes_gb */
-#define Register118 (GMAC_BaseAddress + 0x1d8)
-#define Register118_RegisterSize 32
-#define Register118_RegisterResetValue 0x0
-#define Register118_RegisterResetMask 0x0
-
-
-/* Register Register119 */
-/* rxwatchdogerror */
-#define Register119 (GMAC_BaseAddress + 0x1dc)
-#define Register119_RegisterSize 32
-#define Register119_RegisterResetValue 0x0
-#define Register119_RegisterResetMask 0x0
-
-
-#define DMA_BaseAddress (ETHERNET_CTRL_BASE + 0x1000)
-
-/* Register Register0 */
-/* Bus Mode Register */
-#define D_Register0 (DMA_BaseAddress)
-#define D_Register0_RegisterSize 32
-#define D_Register0_RegisterResetValue 0x20101
-#define D_Register0_RegisterResetMask 0x0
-
-
-/* Register Register1 */
-/* Transmit Poll Demand Register */
-#define D_Register1 (DMA_BaseAddress + 0x4)
-#define D_Register1_RegisterSize 32
-#define D_Register1_RegisterResetValue 0x0
-#define D_Register1_RegisterResetMask 0x0
-
-/* Register Register2 */
-/* Receive Poll Demand Register */
-#define D_Register2 (DMA_BaseAddress + 0x8)
-#define D_Register2_RegisterSize 32
-#define D_Register2_RegisterResetValue 0x0
-#define D_Register2_RegisterResetMask 0x0
-
-
-/* Register Register3 */
-/* Receive Descriptor List Address Register */
-#define D_Register3 (DMA_BaseAddress + 0xc)
-#define D_Register3_RegisterSize 32
-#define D_Register3_RegisterResetValue 0x0
-#define D_Register3_RegisterResetMask 0x0
-
-
-/* Register Register4 */
-/* Transmit Descriptor List Address Register */
-#define D_Register4 (DMA_BaseAddress + 0x10)
-#define D_Register4_RegisterSize 32
-#define D_Register4_RegisterResetValue 0x0
-#define D_Register4_RegisterResetMask 0x0
-
-
-/* Register Register5 */
-/* Status Register */
-#define D_Register5 (DMA_BaseAddress + 0x14)
-#define D_Register5_RegisterSize 32
-#define D_Register5_RegisterResetValue 0x0
-#define D_Register5_RegisterResetMask 0x0
-
-
-
-/* Register Register6 */
-/* Operation Mode Register */
-#define D_Register6 (DMA_BaseAddress + 0x18)
-#define D_Register6_RegisterSize 32
-#define D_Register6_RegisterResetValue 0x0
-#define D_Register6_RegisterResetMask 0x0
-
-
-/* Register Register7 */
-/* Interrupt enable Register */
-#define D_Register7 (DMA_BaseAddress + 0x1c)
-#define D_Register7_RegisterSize 32
-#define D_Register7_RegisterResetValue 0x0
-#define D_Register7_RegisterResetMask 0x0
-
-/* D_Register Register8 */
-/* Missed Frame and Buffer Oerflow Counter Register */
-#define D_Register8 (DMA_BaseAddress + 0x20)
-#define D_Register8_RegisterSize 32
-#define D_Register8_RegisterResetValue 0x0
-#define D_Register8_RegisterResetMask 0x0
-
-/* Register Register18 */
-/* Current Host Transmit Descriptor Register */
-#define D_Register18 (DMA_BaseAddress + 0x48)
-#define D_Register18_RegisterSize 32
-#define D_Register18_RegisterResetValue 0x0
-#define D_Register18_RegisterResetMask 0x0
-
-
-/* Register Register19 */
-/* Current Host Receive Descriptor Register */
-#define D_Register19 (DMA_BaseAddress + 0x4c)
-#define D_Register19_RegisterSize 32
-#define D_Register19_RegisterResetValue 0x0
-#define D_Register19_RegisterResetMask 0x0
-
-
-
-/* Register Register20 */
-/* Current Host Transmit Buffer Address Register */
-#define D_Register20 (DMA_BaseAddress + 0x50)
-#define D_Register20_RegisterSize 32
-#define D_Register20_RegisterResetValue 0x0
-#define D_Register20_RegisterResetMask 0x0
-
-
-/* Register Register21 */
-/* Current Host Receive Buffer Address Register */
-#define D_Register21 (DMA_BaseAddress + 0x54)
-#define D_Register21_RegisterSize 32
-#define D_Register21_RegisterResetValue 0x0
-#define D_Register21_RegisterResetMask 0x0
-
-/* MDIO M2M adress*/
-
-#define MDIO_control (SYS_APB_BASE+ 0x20000)
-#define MDIO_status (SYS_APB_BASE+ 0x20004)
-#define MDIO_ext_stat (SYS_APB_BASE+ 0x20008)
-#define MDIO_PHY_id (SYS_APB_BASE+ 0x2000C)
-#define MDIO_PHY_addr (SYS_APB_BASE+ 0x20010)
-#define MDIO_it (SYS_APB_BASE+ 0x20014)
-#define MDIO_mask_it (SYS_APB_BASE+ 0x20018)
-
-#endif /* __ASM_ARCH_ETHERNET_CTRL_H */
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/gpdma.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/gpdma.h
deleted file mode 100644
index 64d78abb63..0000000000
--- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/gpdma.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * include/asm-arm/arch-spc300/gpdma.h
- *
- * Copyright (C) 2009 SPiDCOM Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_GPDMA_H
-#define __ASM_ARCH_GPDMA_H
-
-#ifndef GPDMA_BASE
- #error "#define GPDMA_BASE macro needs to be defined before including file gpdma.h"
-#endif
-
-
-#define GPDMA_CHANNEL0 (0x000)
-#define GPDMA_CHANNEL1 (0x058)
-
-#define GPDMA_SAR (GPDMA_BASE+0x000)
-#define GPDMA_DAR (GPDMA_BASE+0x008)
-#define GPDMA_LLP (GPDMA_BASE+0x010)
-#define GPDMA_CTL (GPDMA_BASE+0x018)
-#define GPDMA_CTLh (GPDMA_BASE+0x018+4)
-#define GPDMA_SSTAT (GPDMA_BASE+0x020)
-#define GPDMA_DSTAT (GPDMA_BASE+0x028)
-#define GPDMA_SSTATAR (GPDMA_BASE+0x030)
-#define GPDMA_DSTATAR (GPDMA_BASE+0x038)
-#define GPDMA_CFG (GPDMA_BASE+0x040)
-#define GPDMA_CFGh (GPDMA_BASE+0x040+4)
-#define GPDMA_SGR (GPDMA_BASE+0x048)
-#define GPDMA_DSR (GPDMA_BASE+0x050)
-
-#define GPDMA_SAR0 (GPDMA_BASE+0x000)
-#define GPDMA_DAR0 (GPDMA_BASE+0x008)
-#define GPDMA_LLP0 (GPDMA_BASE+0x010)
-#define GPDMA_CTL0 (GPDMA_BASE+0x018)
-#define GPDMA_CTL0h (GPDMA_BASE+0x018+4)
-#define GPDMA_SSTAT0 (GPDMA_BASE+0x020)
-#define GPDMA_DSTAT0 (GPDMA_BASE+0x028)
-#define GPDMA_SSTATAR0 (GPDMA_BASE+0x030)
-#define GPDMA_DSTATAR0 (GPDMA_BASE+0x038)
-#define GPDMA_CFG0 (GPDMA_BASE+0x040)
-#define GPDMA_CFG0h (GPDMA_BASE+0x040+4)
-#define GPDMA_SGR0 (GPDMA_BASE+0x048)
-#define GPDMA_DSR0 (GPDMA_BASE+0x050)
-
-#define GPDMA_SAR1 (GPDMA_BASE+0x058)
-#define GPDMA_DAR1 (GPDMA_BASE+0x060)
-#define GPDMA_LLP1 (GPDMA_BASE+0x068)
-#define GPDMA_CTL1 (GPDMA_BASE+0x070)
-#define GPDMA_CTL1h (GPDMA_BASE+0x070+4)
-#define GPDMA_SSTAT1 (GPDMA_BASE+0x078)
-#define GPDMA_DSTAT1 (GPDMA_BASE+0x080)
-#define GPDMA_SSTATAR1 (GPDMA_BASE+0x088)
-#define GPDMA_DSTATAR1 (GPDMA_BASE+0x090)
-#define GPDMA_CFG1 (GPDMA_BASE+0x098)
-#define GPDMA_CFG1h (GPDMA_BASE+0x098+4)
-#define GPDMA_SGR1 (GPDMA_BASE+0x0A0)
-#define GPDMA_DSR1 (GPDMA_BASE+0x0A8)
-
-// Interrupt Registers
-#define GPDMA_RawTfr (GPDMA_BASE+0x2C0)
-#define GPDMA_RawBlock (GPDMA_BASE+0x2C8)
-#define GPDMA_RawSrcTran (GPDMA_BASE+0x2D0)
-#define GPDMA_RawDstTran (GPDMA_BASE+0x2D8)
-#define GPDMA_RawErr (GPDMA_BASE+0x2E0)
-
-#define GPDMA_StatusTfr (GPDMA_BASE+0x2E8)
-#define GPDMA_StatusBlock (GPDMA_BASE+0x2F0)
-#define GPDMA_StatusSrcTran (GPDMA_BASE+0x2F8)
-#define GPDMA_StatusDstTran (GPDMA_BASE+0x300)
-#define GPDMA_StatusErr (GPDMA_BASE+0x308)
-
-#define GPDMA_MaskTfr (GPDMA_BASE+0x310)
-#define GPDMA_MaskBlock (GPDMA_BASE+0x318)
-#define GPDMA_MaskSrcTran (GPDMA_BASE+0x320)
-#define GPDMA_MaskDstTran (GPDMA_BASE+0x328)
-#define GPDMA_MaskErr (GPDMA_BASE+0x330)
-
-#define GPDMA_ClearTfr (GPDMA_BASE+0x338)
-#define GPDMA_ClearBlock (GPDMA_BASE+0x340)
-#define GPDMA_ClearSrcTran (GPDMA_BASE+0x348)
-#define GPDMA_ClearDstTran (GPDMA_BASE+0x350)
-#define GPDMA_ClearErr (GPDMA_BASE+0x358)
-#define GPDMA_StatusInt (GPDMA_BASE+0x360)
-
-// Software Handshaking Registers
-#define GPDMA_ReqSrcReg (GPDMA_BASE+0x368)
-#define GPDMA_ReqDstReg (GPDMA_BASE+0x370)
-#define GPDMA_SglReqSrcReg (GPDMA_BASE+0x378)
-#define GPDMA_SglReqDstReg (GPDMA_BASE+0x380)
-#define GPDMA_LstSrcReg (GPDMA_BASE+0x388)
-#define GPDMA_LstDstReg (GPDMA_BASE+0x390)
-
-// Miscellaneous Registers
-#define GPDMA_DmaCfgReg (GPDMA_BASE+0x398)
-#define GPDMA_ChEnReg (GPDMA_BASE+0x3A0)
-#define GPDMA_DmaIdReg (GPDMA_BASE+0x3A8)
-#define GPDMA_DmaTestReg (GPDMA_BASE+0x3B0)
-
-
-/*
-#define GPDMA_SAR0 (GPDMA_BASE+0x000)
-#define GPDMA_DAR0 (GPDMA_BASE+0x008)
-#define GPDMA_LLP0 (GPDMA_BASE+0x010)
-#define GPDMA_CTL0 (GPDMA_BASE+0x018)
-#define GPDMA_CTL0h (GPDMA_BASE+0x018+4)
-#define GPDMA_CFG0 (GPDMA_BASE+0x040)
-#define GPDMA_RawTfr (GPDMA_BASE+0x2c0)
-#define GPDMA_MaskTfr (GPDMA_BASE+0x310)
-#define GPDMA_MaskBlock (GPDMA_BASE+0x318)
-#define GPDMA_ClearTfr (GPDMA_BASE+0x338)
-#define GPDMA_ClearBlock (GPDMA_BASE+0x340)
-#define GPDMA_ClearSrcTran (GPDMA_BASE+0x348)
-#define GPDMA_ClearDstTran (GPDMA_BASE+0x350)
-#define GPDMA_ClearErr (GPDMA_BASE+0x358)
-#define GPDMA_DmaCfgReg (GPDMA_BASE+0x398)
-#define GPDMA_ChEnReg (GPDMA_BASE+0x3a0)
-*/
-
-#endif /* __ASM_ARCH_GPDMA_H */
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/hardware.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/hardware.h
index 68d7a7c581..7b421268f1 100644
--- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/hardware.h
+++ b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/hardware.h
@@ -25,10 +25,7 @@
#include <config.h>
-#include "bus_sys.h"
-#include "dsp.h"
-#include "sdk300.h"
-#include "spi.h"
+#include "asm/arch/ips/hardware/bus_sys.h"
#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/i2s.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/i2s.h
deleted file mode 100644
index a2cbc8f370..0000000000
--- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/i2s.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * include/asm-arm/arch-spc300/i2s.h
- *
- * Copyright (C) 2009 SPiDCOM Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_I2S_H
-#define __ASM_ARCH_I2S_H
-
-#ifndef I2S_BASE
- #error "I2S_BASE macro needs to be defined before including file I2S.h"
-#endif
-
-#define I2S_IER (I2S_BASE+0x00)
-#define I2S_ITER (I2S_BASE+0x08)
-#define I2S_CER (I2S_BASE+0x0c)
-#define I2S_CCR (I2S_BASE+0x10)
-#define I2S_RXFFR (I2S_BASE+0x14)
-#define I2S_TXFFR (I2S_BASE+0x18)
-#define I2S_LRBR0 (I2S_BASE+0x20)
-#define I2S_LTHR0 (I2S_BASE+0x20)
-#define I2S_RRBR0 (I2S_BASE+0x24)
-#define I2S_RTHR0 (I2S_BASE+0x24)
-#define I2S_TER0 (I2S_BASE+0x2c)
-#define I2S_TCR0 (I2S_BASE+0x34)
-#define I2S_ISR0 (I2S_BASE+0x38)
-#define I2S_IMR0 (I2S_BASE+0x3c)
-#define I2S_TOR0 (I2S_BASE+0x44)
-#define I2S_TFCR0 (I2S_BASE+0x4c)
-#define I2S_TXDMA (I2S_BASE+0x1c8)
-#define I2S_COMP_PARAM_1 (I2S_BASE+0x1f4)
-
-#endif /* __ASM_ARCH_I2S_H */
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/pcm.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/pcm.h
deleted file mode 100644
index b84415971e..0000000000
--- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/pcm.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * include/asm-arm/arch-spc300/pcm.h
- *
- * (C) Copyright 2008 SPiDCOM Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_PCM_H
-#define __ASM_ARCH_PCM_H
-
-/*
- * Register address of PCM Controller
- *
- * 2007-12-10
- */
-
-#ifndef PCM_BASE
- #error "PCM_BASE macro needs to be defined before including file pcm.h"
-#endif
-
-
-#define PCM_CONFIG_SYNC (PCM_BASE + 0x00)
-#define PCM_CONFIG_FRAME_PERIOD (PCM_BASE + 0x04)
-#define PCM_START_DELAY_TX (PCM_BASE + 0x08)
-#define PCM_START_DELAY_RX (PCM_BASE + 0x0C)
-#define PCM_DATA_BYTE_SIZE (PCM_BASE + 0x10)
-#define PCM_TX_EMP_TRIG (PCM_BASE + 0x14)
-#define PCM_RX_DATA_TRIG (PCM_BASE + 0x18)
-#define PCM_REG_TX (PCM_BASE + 0x20)
-#define PCM_REG_RX (PCM_BASE + 0x24)
-#define PCM_REG_IRQ (PCM_BASE + 0x30)
-#define PCM_REG_MASK (PCM_BASE + 0x34)
-#define PCM_REG_STATUS (PCM_BASE + 0x38)
-
-#endif /* __ASM_ARCH_PCM_H */
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/pkg_maria_regbank.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/pkg_maria_regbank.h
deleted file mode 100644
index 54b3ac85e2..0000000000
--- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/pkg_maria_regbank.h
+++ /dev/null
@@ -1,256 +0,0 @@
-/*
- * include/asm-arm/arch-spc300/pkg_maria_regbank.h
- *
- * Copyright (C) 2009 SPiDCOM Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_MARIA_REGBANK_H
-#define __ASM_ARCH_MARIA_REGBANK_H
-
-
-#ifndef MARIA_REGBANK_BASE
- #error "MARIA_REGBANK_BASE macro needs to be defined before including file pkg_maria_regbank.h"
-#endif
-
-
-#define IS_TRUE (0x1)
-#define SLAVE_MARIA_REGBANK (0x8030)
-#define RB_PACKAGE (0x000)
-#define PACKAGE_PFBGA265 (0x1)
-#define PACKAGE_LQFP176 (0x0)
-#define RB_SDRAM_RETURN_LAT (0x004)
-#define RB_MARIA_IMPLEMENTATION (0x008)
-#define MARIA_IMPLEMENTATION_ASIC (0x0)
-#define MARIA_IMPLEMENTATION_FCM3 (0x1)
-#define RB_BUS_SYS_REMAPPED (0x100)
-#define RB_BUS_SYS_ARBITER_INIT (0x104)
-#define RB_BUS_SYS_ARBITER_INIT_VALUE (0x108)
-#define RB_BUS_INTF_ARBITER_INIT (0x10c)
-#define RB_BUS_INTF_ARBITER_INIT_VALUE (0x110)
-#define RB_BUS_DSP_ARBITER_INIT (0x114)
-#define RB_BUS_DSP_ARBITER_INIT_VALUE (0x118)
-#define RB_ICM_PRIORITY (0x11c)
-#define RB_LEON_ADD_START (0x120)
-#define RB_LEON_TICK_CNT (0x124)
-#define RB_DSP_HLOCK (0x128)
-#define LEON_ADD_START_RESET (0x00011000)
-#define LEON_TICK_CNT_RESET (0x1d4c)
-#define RB_PIO_CONFIG (0x200)
-#define PIO_CONFIG_0 (0x0)
-#define PIO_CONFIG_1 (0x1)
-#define PIO_CONFIG_2 (0x2)
-#define PIO_CONFIG_3 (0x3)
-#define PIO_CONFIG_4 (0x4)
-#define PIO_CONFIG_5 (0x5)
-#define PIO_CONFIG_6 (0x6)
-#define PIO_CONFIG_7 (0x7)
-#define RB_PIO_ENABLE (0x204)
-#define RB_GPIO_0_CONFIG (0x208)
-#define RB_GPIO_1_CONFIG (0x20c)
-#define RB_GPIO_2_CONFIG (0x210)
-#define RB_GPIO_3_CONFIG (0x214)
-#define RB_GPIO_4_CONFIG (0x218)
-#define RB_GPIO_5_CONFIG (0x21c)
-#define RB_GPIO_6_CONFIG (0x220)
-#define RB_GPIO_7_CONFIG (0x224)
-#define RB_GPIO_8_CONFIG (0x228)
-#define RB_GPIO_9_CONFIG (0x22c)
-#define RB_GPIO_10_CONFIG (0x230)
-#define RB_GPIO_11_CONFIG (0x234)
-#define RB_GPIO_12_CONFIG (0x238)
-#define RB_GPIO_13_CONFIG (0x23c)
-#define RB_GPIO_14_CONFIG (0x240)
-#define RB_GPIO_15_CONFIG (0x244)
-#define RB_GPIO_DEBUG (0x248)
-#define GPIO_CONFIG_0 (0x0)
-#define GPIO_CONFIG_1 (0x1)
-#define GPIO_CONFIG_2 (0x2)
-#define GPIO_CONFIG_3 (0x3)
-#define GPIO_CONFIG_4 (0x4)
-#define GPIO_CONFIG_5 (0x5)
-#define GPIO_CONFIG_6 (0x6)
-#define GPIO_CONFIG_7 (0x7)
-#define GPIO_CONFIG_8 (0x8)
-#define GPIO_CONFIG_9 (0x9)
-#define RB_WDT_SPEED_UP (0x300)
-#define RB_AFE_CLKO_POL (0x304)
-#define CLK_CMD_ON (0x1)
-#define CLK_CMD_OFF (0x0)
-#define CLK_IS_ON (0x1)
-#define CLK_IS_OFF (0x2)
-#define CLK_CMD_BYPASS (0x1)
-#define CLK_CMD_PLL (0x0)
-#define CLK_IS_BYPASS (0x1)
-#define CLK_IS_PLL (0x2)
-#define RB_CLK_CMD_ETH_RMII (0x400)
-#define RB_CLK_STAT_ETH_RMII (0x404)
-#define RB_CLK_DIV_ETH_25 (0x408)
-#define RB_CLK_DIV_STAT_ETH_25 (0x40C)
-#define CLK_DIV_ETH_25_2 (0x0)
-#define CLK_DIV_ETH_25_20 (0x1)
-#define RB_CLK_CMD_ETH_TX_EXT (0x410)
-#define RB_CLK_STAT_ETH_TX_EXT (0x414)
-#define RB_CLK_CMD_ETH_TX_125 (0x420)
-#define RB_CLK_STAT_ETH_TX_125 (0x424)
-#define RB_CLK_SEL_ETH_TX (0x430)
-#define RB_CLK_SEL_STAT_ETH_TX (0x434)
-#define CLK_SEL_ETH_TX_25 (0x0)
-#define CLK_SEL_ETH_TX_125 (0x1)
-#define CLK_SEL_ETH_TX_EXT (0x2)
-#define RB_CLK_CMD_ETH_RX_EXT (0x440)
-#define RB_CLK_STAT_ETH_RX_EXT (0x444)
-#define RB_CLK_SEL_ETH_RX (0x450)
-#define RB_CLK_SEL_STAT_ETH_RX (0x454)
-#define CLK_SEL_ETH_RX_25 (0x0)
-#define CLK_SEL_ETH_RX_EXT (0x1)
-#define RB_CLK_SEL_ETH_MAC (0x460)
-#define RB_CLK_SEL_STAT_ETH_MAC (0x464)
-#define CLK_SEL_ETH_MAC_RMII (0x0)
-#define CLK_SEL_ETH_MAC_125 (0x1)
-#define RB_CLK_CMD_DSP (0x470)
-#define RB_CLK_STAT_DSP (0x474)
-#define RB_CLK_CMD_AFE (0x480)
-#define RB_CLK_STAT_AFE (0x484)
-#define RB_CLK_CMD_ARM (0x490)
-#define RB_CLK_STAT_ARM (0x494)
-#define RB_CLK_DIV_ARM (0x498)
-#define RB_CLK_DIV_STAT_ARM (0x49C)
-#define CLK_DIV_ARM_2 (0x0)
-#define CLK_DIV_ARM_4 (0x1)
-#define CLK_DIV_SYS_4 (0x0)
-#define RB_CLK_CMD_SRAM (0x4A0)
-#define RB_CLK_STAT_SRAM (0x4A4)
-#define RB_CLK_DIV_SRAM (0x4A8)
-#define RB_CLK_DIV_STAT_SRAM (0x4AC)
-#define CLK_DIV_SRAM_8 (0x0)
-#define CLK_DIV_SRAM_12 (0x1)
-#define CLK_DIV_SRAM_16 (0x2)
-#define RB_CLK_CMD_MPG_EXT (0x4B0)
-#define RB_CLK_STAT_MPG_EXT (0x4B4)
-#define RB_CLK_CMD_MPG_INT (0x4C0)
-#define RB_CLK_STAT_MPG_INT (0x4C4)
-#define RB_CLK_DIV_MPG_INT (0x4C8)
-#define RB_CLK_DIV_STAT_MPG_INT (0x4CC)
-#define RB_CLK_SEL_MPG (0x4D0)
-#define RB_CLK_SEL_STAT_MPG (0x4D4)
-#define CLK_SEL_MPG_INT (0x0)
-#define CLK_SEL_MPG_EXT (0x1)
-#define RB_CLK_POL_MPG (0x4D8)
-#define RB_CLK_CMD_SPI (0x4E0)
-#define RB_CLK_STAT_SPI (0x4E4)
-#define RB_CLK_CMD_I2S (0x4F0)
-#define RB_CLK_STAT_I2S (0x4F4)
-#define RB_CLK_DIV_I2S (0x4F8)
-#define RB_CLK_DIV_STAT_I2S (0x4FC)
-#define RB_CLK_CMD_PCM (0x500)
-#define RB_CLK_STAT_PCM (0x504)
-#define RB_CLK_DIV_PCM (0x508)
-#define RB_CLK_DIV_STAT_PCM (0x50C)
-#define RB_CLK_POL_PCM (0x510)
-#define RB_CLK_DIV_T1 (0x518)
-#define RB_CLK_DIV_STAT_T1 (0x51C)
-#define RB_CLK_DIV_T2 (0x528)
-#define RB_CLK_DIV_STAT_T2 (0x52C)
-#define RB_PPLL_FBDIV (0x530)
-#define RB_PPLL_PREDIV (0x534)
-#define RB_PPLL_LBWS (0x538)
-#define RB_PPLL_PD (0x53C)
-#define RB_PPLL_BYPASS (0x540)
-#define RB_PPLL_BYPASS_STAT (0x544)
-#define RB_PPLL_DEBUG (0x548)
-#define RB_DPLL_FBDIV (0x550)
-#define RB_DPLL_PREDIV (0x554)
-#define RB_DPLL_LBWS (0x558)
-#define RB_DPLL_PD (0x55C)
-#define RB_DPLL_BYPASS (0x560)
-#define RB_DPLL_BYPASS_STAT (0x564)
-#define RB_DPLL_DEBUG (0x568)
-#define RB_SPLL_FBDIV (0x570)
-#define RB_SPLL_PREDIV (0x574)
-#define RB_SPLL_LBWS (0x578)
-#define RB_SPLL_PD (0x57C)
-#define RB_SPLL_BYPASS (0x580)
-#define RB_SPLL_BYPASS_STAT (0x584)
-#define RB_SPLL_FCW (0x588)
-#define RB_SPLL_FMW (0x58C)
-#define RB_SPLL_MDW (0x590)
-#define RB_SPLL_EN (0x594)
-#define RB_SPLL_DEBUG (0x598)
-#define RB_SPLL_SSCGNRST (0x59C)
-#define PLL_CMD_ON (0x0)
-#define PLL_CMD_OFF (0x1)
-#define PLL_CMD_BYPASS (0x1)
-#define PLL_CMD_PLL (0x0)
-#define PLL_IS_BYPASS (0x1)
-#define PLL_IS_PLL (0x2)
-#define PLL_LBWS_OFF (0x0)
-#define PLL_LBWS_ON (0x1)
-#define RB_CLK_CMD_SDR (0x5A0)
-#define RB_CLK_STAT_SDR (0x5A4)
-#define RB_CLK_CMD_OUT25 (0x5B0)
-#define RB_CLK_STAT_OUT25 (0x5B4)
-#define RB_PWM_ENABLE (0x600)
-#define RB_PWM_PERIOD_0 (0x604)
-#define RB_PWM_PERIOD_1 (0x608)
-#define RB_PWM_PERIOD_2 (0x60C)
-#define RB_PWM_PERIOD_3 (0x610)
-#define RB_PWM_PULSE_0 (0x614)
-#define RB_PWM_PULSE_1 (0x618)
-#define RB_PWM_PULSE_2 (0x61C)
-#define RB_PWM_PULSE_3 (0x620)
-#define RB_ETH_CONFIG (0x630)
-#define ETH_CFG_MAC_TO_MAC (0x1)
-#define ETH_CFG_RMII_100 (0x2)
-#define ETH_CFG_RMII (0x4)
-#define ETH_CFG_FLOW_CTRL (0x8)
-#define RB_RST_GSRC (0x700)
-#define RST_GSRC_POWER (0x1)
-#define RST_GSRC_EXT (0x2)
-#define RST_GSRC_WDOG (0x4)
-#define RST_GSRC_SOFT (0x8)
-#define RB_RST_GLOBAL (0x704)
-#define RST_GLOBAL (0x1)
-#define RB_RST_GROUP (0x708)
-#define RST_SYS (0x1)
-#define RST_INTF (0x2)
-#define RST_DSP (0x4)
-#define RST_LEONSS (0x8)
-#define RB_RST_MODULE (0x70C)
-#define RST_ARM (0x1)
-#define RST_GPDMA (0x2)
-#define RST_ARM_APB (0x4)
-#define RST_SPI (0x8)
-#define RST_PCM (0x10)
-#define RST_SRAM (0x20)
-#define RST_I2S (0x40)
-#define RST_MBOX (0x80)
-#define RST_ETH (0x100)
-#define RST_MPG (0x200)
-#define RST_DMAB (0x400)
-#define RST_LCPU (0x800)
-#define RST_EXT (0x1000)
-#define RB_RST_GMASK (0x710)
-#define RB_FCM3_UART_SELECT (0x800)
-#define RB_FCM3_AD_SPIEN (0x804)
-#define RB_DINI_UART_SELECT (0x900)
-#define RB_DINI_UART_SELECT_LEON (0x0)
-#define RB_DINI_UART_SELECT_ARM (0x1)
-#define RB_DINI_SPARE_1 (0x904)
-#define RB_DINI_SPARE_1_ETH_RX_CLOCK_INVERT (0x800)
-
-#endif /* __ASM_ARCH_MARIA_REGBANK_H */
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/sdk300.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/sdk300.h
deleted file mode 100644
index 8790c6e291..0000000000
--- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/sdk300.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * include/asm-arm/arch-spc300/sdk300.h
- *
- * Copyright (C) 2009 SPiDCOM Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_SDK300_H
-#define __ASM_ARCH_SDK300_H
-
-/*
- * FCM3 base addresses
- */
-#define MARIA_BASE 0x70000000
-
-/*
- * Interrupt controller
- */
-#define IT_CTRL_OFFSET 0x000fef00
-#define GIC_OFFSET 0x000ff100
-
-/*
- * MPU
- */
-#define MPU_MAIN_OFFSET 0x000e8100
-#define MPU_CHILD0_OFFSET 0x000ec100
-#define MPU_CHILD1_OFFSET 0x000f0100
-#define MPU_CHILD3_OFFSET 0x000f8100
-#define MARIA_MPU_CHILD0_BASE (MARIA_BASE | MPU_CHILD0_OFFSET)
-
-/*
- * Flash
- */
-#define MARIA_EBI_FLASH_BASE (MARIA_BASE | 0x08000000)
-
-/*
- * PLL Clock manager
- */
-#define PLL_CLOCK_OFFSET 0x0009c000
-#define MARIA_PLL_CLOCK_BASE (MARIA_BASE | PLL_CLOCK_OFFSET)
-
-/*
- * EBI flash controller
- */
-#define EBI_OFFSET 0x000cc000
-#define MARIA_EBI_BASE (MARIA_BASE | EBI_OFFSET)
-
-#endif /* __ASM_ARCH_SDK300_H */
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/sdram.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/sdram.h
deleted file mode 100644
index 0fc7e0fa10..0000000000
--- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/sdram.h
+++ /dev/null
@@ -1,933 +0,0 @@
-/*
- * include/asm-arm/arch-spc300/sdram.h
- *
- * Copyright (C) 2009 SPiDCOM Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_SDRAM_H
-#define __ASM_ARCH_SDRAM_H
-
-/* Register SCONR */
-/* SDRAM configuration register */
-#define SCONR 0x0
-#define SCONR_RegisterSize 32
-#define SCONR_RegisterResetValue 0xe5188
-#define SCONR_RegisterResetMask 0x0
-
-/* Register Field information for SCONR */
-
-/* Register SCONR field s_bank_addr_width */
-/* Number of bank address bits */
-#define SCONR_s_bank_addr_width_BitAddressOffset 3
-#define SCONR_s_bank_addr_width_RegisterSize 2
-#define SCONR_s_bank_addr_width_RegisterMask (3<<SCONR_s_bank_addr_width_BitAddressOffset)
-
-/* Register SCONR field s_row_addr_width */
-/* Number of address bits for row address */
-#define SCONR_s_row_addr_width_BitAddressOffset 5
-#define SCONR_s_row_addr_width_RegisterSize 4
-#define SCONR_s_row_addr_width_RegisterMask (0x0f<<SCONR_s_row_addr_width_BitAddressOffset)
-
-/* Register SCONR field s_col_addr_width */
-/* Number of address bits for column address */
-#define SCONR_s_col_addr_width_BitAddressOffset 9
-#define SCONR_s_col_addr_width_RegisterSize 4
-#define SCONR_s_col_addr_width_RegisterMask (0x0f<<SCONR_s_col_addr_width_BitAddressOffset)
-
-/* Register SCONR field s_data_width */
-/* SDRAM data width */
-#define SCONR_s_data_width_BitAddressOffset 13
-#define SCONR_s_data_width_RegisterSize 2
-#define SCONR_s_data_width_RegisterMask (3<<SCONR_s_data_width_BitAddressOffset)
-
-/* Register SCONR field s_sa */
-/* Serial presence detect address bits */
-#define SCONR_s_sa_BitAddressOffset 15
-#define SCONR_s_sa_RegisterSize 2
-
-/* Register SCONR field s_scl */
-/* Clock for serial presence detect logic */
-#define SCONR_s_scl_BitAddressOffset 18
-#define SCONR_s_scl_RegisterSize 1
-
-/* Register SCONR field s_sd */
-/* Bi-directional data for serial presence detect (SPD) logic */
-#define SCONR_s_sd_BitAddressOffset 19
-#define SCONR_s_sd_RegisterSize 1
-
-/* Register SCONR field s_sda_oe_n */
-/* Output enable for bi-directional data pin for I2C serial presence detect (SPD) logic */
-#define SCONR_s_sda_oe_n_BitAddressOffset 20
-#define SCONR_s_sda_oe_n_RegisterSize 1
-
-/* End of Register Definition for SCONR */
-
-/* Register STMG0R */
-/* SDRAM timing register 0 */
-#define STMG0R (0x0 + 0x4)
-#define STMG0R_RegisterSize 32
-#define STMG0R_RegisterResetValue 0x22e569a
-#define STMG0R_RegisterResetMask 0x0
-
-/* Register Field information for STMG0R */
-
-/* Register STMG0R field cas_latency */
-/* Delay in clock cycles between read command and availability of first data */
-#define STMG0R_cas_latency_BitAddressOffset 0
-#define STMG0R_cas_latency_RegisterSize 2
-
-/* Register STMG0R field t_ras_min */
-/* Minimum delay between active and precharge commands */
-#define STMG0R_t_ras_min_BitAddressOffset 2
-#define STMG0R_t_ras_min_RegisterSize 4
-
-/* Register STMG0R field t_rcd */
-/* Minimum delay between active and read/write commands */
-#define STMG0R_t_rcd_BitAddressOffset 6
-#define STMG0R_t_rcd_RegisterSize 3
-
-/* Register STMG0R field t_rp */
-/* Precharge period */
-#define STMG0R_t_rp_BitAddressOffset 9
-#define STMG0R_t_rp_RegisterSize 3
-
-/* Register STMG0R field t_wr */
-/* For writes, delay from last data in to next precharge command */
-#define STMG0R_t_wr_BitAddressOffset 12
-#define STMG0R_t_wr_RegisterSize 2
-
-/* Register STMG0R field t_rcar */
-/* Auto-refresh period; minimum time between two auto-refresh commands */
-#define STMG0R_t_rcar_BitAddressOffset 14
-#define STMG0R_t_rcar_RegisterSize 4
-
-/* Register STMG0R field t_xsr */
-/* Exit self-refresh to active or auto-refresh command time */
-#define STMG0R_t_xsr_BitAddressOffset 18
-#define STMG0R_t_xsr_RegisterSize 4
-
-/* Register STMG0R field t_rc */
-/* Active-to-active command period */
-#define STMG0R_t_rc_BitAddressOffset 22
-#define STMG0R_t_rc_RegisterSize 4
-
-/* Register STMG0R field extended_cas_latency */
-/* Bitfield extension for cas_latency (used for DDR) */
-#define STMG0R_extended_cas_latency_BitAddressOffset 26
-#define STMG0R_extended_cas_latency_RegisterSize 1
-
-/* Register STMG0R field extended_t_xsr */
-/* Bitfield extension for t_xsr */
-#define STMG0R_extended_t_xsr_BitAddressOffset 27
-#define STMG0R_extended_t_xsr_RegisterSize 5
-
-/* End of Register Definition for STMG0R */
-
-/* Register STMG1R */
-/* SDRAM timing register 1 */
-#define STMG1R (0x0 + 0x8)
-#define STMG1R_RegisterSize 32
-#define STMG1R_RegisterResetValue 0x70008
-#define STMG1R_RegisterResetMask 0x0
-
-/* Register Field information for STMG1R */
-
-/* Register STMG1R field t_init */
-/* Number of clock cycles to hold SDRAM inputs stable after power-up */
-#define STMG1R_t_init_BitAddressOffset 0
-#define STMG1R_t_init_RegisterSize 16
-
-/* Register STMG1R field num_init_ref */
-/* Number of auto-refreshes during initialization */
-#define STMG1R_num_init_ref_BitAddressOffset 16
-#define STMG1R_num_init_ref_RegisterSize 4
-
-/* Register STMG1R field t_wtr */
-/* Internal write-to-read delay for DDR-SDRAMs */
-#define STMG1R_t_wtr_BitAddressOffset 20
-#define STMG1R_t_wtr_RegisterSize 2
-
-/* End of Register Definition for STMG1R */
-
-/* Register SCTLR */
-/* SDRAM control register */
-#define SCTLR (0x0 + 0xc)
-#define SCTLR_RegisterSize 32
-#define SCTLR_RegisterResetValue 0x3089
-#define SCTLR_RegisterResetMask 0x0
-
-/* Register Field information for SCTLR */
-
-/* Register SCTLR field initialize */
-/* Forces initialization of SDRAM */
-#define SCTLR_initialize_BitAddressOffset 0
-#define SCTLR_initialize_RegisterSize 1
-
-/* Register SCTLR field self_refresh */
-/* Forces SDRAM into self-refresh mode */
-#define SCTLR_self_refresh_BitAddressOffset 1
-#define SCTLR_self_refresh_RegisterSize 1
-
-/* Register SCTLR field power_down_mode */
-/* Forces SDRAM into power-down mode */
-#define SCTLR_power_down_mode_BitAddressOffset 2
-#define SCTLR_power_down_mode_RegisterSize 1
-
-/* Register SCTLR field precharge_algorithm */
-/* Determines when row is precharged */
-#define SCTLR_precharge_algorithm_BitAddressOffset 3
-#define SCTLR_precharge_algorithm_RegisterSize 1
-
-/* Register SCTLR field full_refresh_before_sr */
-/* Controls number of refreshes done before putting SDRAM into self-refresh mode */
-#define SCTLR_full_refresh_before_sr_BitAddressOffset 4
-#define SCTLR_full_refresh_before_sr_RegisterSize 1
-
-/* Register SCTLR field full_refresh_after_sr */
-/* Controls number of refreshes done after SDRAM is taken out of self-refresh mode */
-#define SCTLR_full_refresh_after_sr_BitAddressOffset 5
-#define SCTLR_full_refresh_after_sr_RegisterSize 1
-
-/* Register SCTLR field read_pipe */
-/* Number of registers inserted in read data path for SDRAM in order to correctly latch data */
-#define SCTLR_read_pipe_BitAddressOffset 6
-#define SCTLR_read_pipe_RegisterSize 3
-
-/* Register SCTLR field set_mode_reg */
-/* Forces update of SDRAM mode register */
-#define SCTLR_set_mode_reg_BitAddressOffset 9
-#define SCTLR_set_mode_reg_RegisterSize 1
-
-/* Register SCTLR field self_refresh_status */
-/* Indicates SDRAM self-refresh mode status */
-#define SCTLR_self_refresh_status_BitAddressOffset 11
-#define SCTLR_self_refresh_status_RegisterSize 1
-
-/* Register SCTLR field num_open_banks */
-/* Number of SDRAM internal banks to be open at any time */
-#define SCTLR_num_open_banks_BitAddressOffset 12
-#define SCTLR_num_open_banks_RegisterSize 5
-
-/* Register SCTLR field s_rd_ready_mode */
-/* SDRAM read-data-ready mode */
-#define SCTLR_s_rd_ready_mode_BitAddressOffset 17
-#define SCTLR_s_rd_ready_mode_RegisterSize 1
-
-/* Register SCTLR field exn_mode_reg_update */
-/* Update Mobile-SDRAM extended-mode register */
-#define SCTLR_exn_mode_reg_update_BitAddressOffset 18
-#define SCTLR_exn_mode_reg_update_RegisterSize 1
-
-/* Register SCTLR field mobile_sdram_dpd_en */
-/* Mobile-SDRAM deep-power-down enable */
-#define SCTLR_mobile_sdram_dpd_en_BitAddressOffset 19
-#define SCTLR_mobile_sdram_dpd_en_RegisterSize 1
-
-/* Register SCTLR field dpd_status */
-/* Mobile-SDRAM deep-power-down mode status */
-#define SCTLR_dpd_status_BitAddressOffset 20
-#define SCTLR_dpd_status_RegisterSize 1
-
-/* End of Register Definition for SCTLR */
-
-/* Register SREFR */
-/* SDRAM refresh register */
-#define SREFR (0x0 + 0x10)
-#define SREFR_RegisterSize 32
-#define SREFR_RegisterResetValue 0x410
-#define SREFR_RegisterResetMask 0x0
-
-/* Register Field information for SREFR */
-
-/* Register SREFR field t_ref */
-/* Number of clock cycles between consecutive refresh cycles */
-#define SREFR_t_ref_BitAddressOffset 0
-#define SREFR_t_ref_RegisterSize 16
-
-/* Register SREFR field gpo */
-/* General purpose output signals */
-#define SREFR_gpo_BitAddressOffset 16
-#define SREFR_gpo_RegisterSize 8
-
-/* Register SREFR field gpi */
-/* General purpose input signals */
-#define SREFR_gpi_BitAddressOffset 24
-#define SREFR_gpi_RegisterSize 8
-
-/* End of Register Definition for SREFR */
-
-/* Register SCSLR0_LOW */
-/* Chip select register 0 */
-#define SCSLR0_LOW (0x0 + 0x14)
-#define SCSLR0_LOW_RegisterSize 32
-#define SCSLR0_LOW_RegisterResetValue 0x80000000
-#define SCSLR0_LOW_RegisterResetMask 0x0
-
-/* Register Field information for SCSLR0_LOW */
-
-/* Register SCSLR0_LOW field addr */
-/* Base address for chip select 0 */
-#define SCSLR0_LOW_addr_BitAddressOffset 16
-#define SCSLR0_LOW_addr_RegisterSize 16
-
-/* End of Register Definition for SCSLR0_LOW */
-
-/* Register SCSLR1_LOW */
-/* Chip select register 1 */
-#define SCSLR1_LOW (0x0 + 0x18)
-#define SCSLR1_LOW_RegisterSize 32
-#define SCSLR1_LOW_RegisterResetValue 0x10000000
-#define SCSLR1_LOW_RegisterResetMask 0x0
-
-/* Register Field information for SCSLR1_LOW */
-
-/* Register SCSLR1_LOW field addr */
-/* Base address for chip select 1 */
-#define SCSLR1_LOW_addr_BitAddressOffset 16
-#define SCSLR1_LOW_addr_RegisterSize 16
-
-/* End of Register Definition for SCSLR1_LOW */
-
-/* Register SCSLR2_LOW */
-/* Chip select register 2 */
-#define SCSLR2_LOW (0x0 + 0x1c)
-#define SCSLR2_LOW_RegisterSize 32
-#define SCSLR2_LOW_RegisterResetValue 0x20000000
-#define SCSLR2_LOW_RegisterResetMask 0x0
-
-/* Register Field information for SCSLR2_LOW */
-
-/* Register SCSLR2_LOW field addr */
-/* Base address for chip select 2 */
-#define SCSLR2_LOW_addr_BitAddressOffset 16
-#define SCSLR2_LOW_addr_RegisterSize 16
-
-/* End of Register Definition for SCSLR2_LOW */
-
-/* Register SCSLR3_LOW */
-/* Chip select register 3 */
-#define SCSLR3_LOW (0x0 + 0x20)
-#define SCSLR3_LOW_RegisterSize 32
-#define SCSLR3_LOW_RegisterResetValue 0x30000000
-#define SCSLR3_LOW_RegisterResetMask 0x0
-
-/* Register Field information for SCSLR3_LOW */
-
-/* Register SCSLR3_LOW field addr */
-/* Base address for chip select 3 */
-#define SCSLR3_LOW_addr_BitAddressOffset 16
-#define SCSLR3_LOW_addr_RegisterSize 16
-
-/* End of Register Definition for SCSLR3_LOW */
-
-/* Register SCSLR4_LOW */
-/* Chip select register 4 */
-#define SCSLR4_LOW (0x0 + 0x24)
-#define SCSLR4_LOW_RegisterSize 32
-#define SCSLR4_LOW_RegisterResetValue 0x40000000
-#define SCSLR4_LOW_RegisterResetMask 0x0
-
-/* Register Field information for SCSLR4_LOW */
-
-/* Register SCSLR4_LOW field addr */
-/* Base address for chip select 4 */
-#define SCSLR4_LOW_addr_BitAddressOffset 16
-#define SCSLR4_LOW_addr_RegisterSize 16
-
-/* End of Register Definition for SCSLR4_LOW */
-
-/* Register SCSLR5_LOW */
-/* Chip select register 5 */
-#define SCSLR5_LOW (0x0 + 0x28)
-#define SCSLR5_LOW_RegisterSize 32
-#define SCSLR5_LOW_RegisterResetValue 0x50000000
-#define SCSLR5_LOW_RegisterResetMask 0x0
-
-/* Register Field information for SCSLR5_LOW */
-
-/* Register SCSLR5_LOW field addr */
-/* Base address for chip select 5 */
-#define SCSLR5_LOW_addr_BitAddressOffset 16
-#define SCSLR5_LOW_addr_RegisterSize 16
-
-/* End of Register Definition for SCSLR5_LOW */
-
-/* Register SCSLR6_LOW */
-/* Chip select register 6 */
-#define SCSLR6_LOW (0x0 + 0x2c)
-#define SCSLR6_LOW_RegisterSize 32
-#define SCSLR6_LOW_RegisterResetValue 0x60000000
-#define SCSLR6_LOW_RegisterResetMask 0x0
-
-/* Register Field information for SCSLR6_LOW */
-
-/* Register SCSLR6_LOW field addr */
-/* Base address for chip select 6 */
-#define SCSLR6_LOW_addr_BitAddressOffset 16
-#define SCSLR6_LOW_addr_RegisterSize 16
-
-/* End of Register Definition for SCSLR6_LOW */
-
-/* Register SCSLR7_LOW */
-/* Chip select register 7 */
-#define SCSLR7_LOW (0x0 + 0x30)
-#define SCSLR7_LOW_RegisterSize 32
-#define SCSLR7_LOW_RegisterResetValue 0x70000000
-#define SCSLR7_LOW_RegisterResetMask 0x0
-
-/* Register Field information for SCSLR7_LOW */
-
-/* Register SCSLR7_LOW field addr */
-/* Base address for chip select 7 */
-#define SCSLR7_LOW_addr_BitAddressOffset 16
-#define SCSLR7_LOW_addr_RegisterSize 16
-
-/* End of Register Definition for SCSLR7_LOW */
-
-/* Register SMSKR0 */
-/* Mask register 0 */
-#define SMSKR0 (0x0 + 0x54)
-#define SMSKR0_RegisterSize 32
-#define SMSKR0_RegisterResetValue 0x20d
-#define SMSKR0_RegisterResetMask 0x0
-
-/* Register Field information for SMSKR0 */
-
-/* Register SMSKR0 field mem_size */
-/* Size of memory connected to chip select 0 */
-#define SMSKR0_mem_size_BitAddressOffset 0
-#define SMSKR0_mem_size_RegisterSize 5
-
-/* Register SMSKR0 field mem_type */
-/* Type of memory connected to chip select 0 */
-#define SMSKR0_mem_type_BitAddressOffset 5
-#define SMSKR0_mem_type_RegisterSize 3
-
-/* Register SMSKR0 field reg_select */
-/* Timing parameters to associate with chip select 0 */
-#define SMSKR0_reg_select_BitAddressOffset 8
-#define SMSKR0_reg_select_RegisterSize 3
-
-/* End of Register Definition for SMSKR0 */
-
-/* Register SMSKR1 */
-/* Mask register 1 */
-#define SMSKR1 (0x0 + 0x58)
-#define SMSKR1_RegisterSize 32
-#define SMSKR1_RegisterResetValue 0x207
-#define SMSKR1_RegisterResetMask 0x0
-
-/* Register Field information for SMSKR1 */
-
-/* Register SMSKR1 field mem_size */
-/* Size of memory connected to chip select 1 */
-#define SMSKR1_mem_size_BitAddressOffset 0
-#define SMSKR1_mem_size_RegisterSize 5
-
-/* Register SMSKR1 field mem_type */
-/* Type of memory connected to chip select 1 */
-#define SMSKR1_mem_type_BitAddressOffset 5
-#define SMSKR1_mem_type_RegisterSize 3
-
-/* Register SMSKR1 field reg_select */
-/* Timing parameters to associate with chip select 1 */
-#define SMSKR1_reg_select_BitAddressOffset 8
-#define SMSKR1_reg_select_RegisterSize 3
-
-/* End of Register Definition for SMSKR1 */
-
-/* Register SMSKR2 */
-/* Mask register 2 */
-#define SMSKR2 (0x0 + 0x5c)
-#define SMSKR2_RegisterSize 32
-#define SMSKR2_RegisterResetValue 0x21
-#define SMSKR2_RegisterResetMask 0x0
-
-/* Register Field information for SMSKR2 */
-
-/* Register SMSKR2 field mem_size */
-/* Size of memory connected to chip select 2 */
-#define SMSKR2_mem_size_BitAddressOffset 0
-#define SMSKR2_mem_size_RegisterSize 5
-
-/* Register SMSKR2 field mem_type */
-/* Type of memory connected to chip select 2 */
-#define SMSKR2_mem_type_BitAddressOffset 5
-#define SMSKR2_mem_type_RegisterSize 3
-
-/* Register SMSKR2 field reg_select */
-/* Timing parameters to associate with chip select 2 */
-#define SMSKR2_reg_select_BitAddressOffset 8
-#define SMSKR2_reg_select_RegisterSize 3
-
-/* End of Register Definition for SMSKR2 */
-
-/* Register SMSKR3 */
-/* Mask register 3 */
-#define SMSKR3 (0x0 + 0x60)
-#define SMSKR3_RegisterSize 32
-#define SMSKR3_RegisterResetValue 0x141
-#define SMSKR3_RegisterResetMask 0x0
-
-/* Register Field information for SMSKR3 */
-
-/* Register SMSKR3 field mem_size */
-/* Size of memory connected to chip select 3 */
-#define SMSKR3_mem_size_BitAddressOffset 0
-#define SMSKR3_mem_size_RegisterSize 5
-
-/* Register SMSKR3 field mem_type */
-/* Type of memory connected to chip select 3 */
-#define SMSKR3_mem_type_BitAddressOffset 5
-#define SMSKR3_mem_type_RegisterSize 3
-
-/* Register SMSKR3 field reg_select */
-/* Timing parameters to associate with chip select 3 */
-#define SMSKR3_reg_select_BitAddressOffset 8
-#define SMSKR3_reg_select_RegisterSize 3
-
-/* End of Register Definition for SMSKR3 */
-
-/* Register SMSKR4 */
-/* Mask register 4 */
-#define SMSKR4 (0x0 + 0x64)
-#define SMSKR4_RegisterSize 32
-#define SMSKR4_RegisterResetValue 0x261
-#define SMSKR4_RegisterResetMask 0x0
-
-/* Register Field information for SMSKR4 */
-
-/* Register SMSKR4 field mem_size */
-/* Size of memory connected to chip select 4 */
-#define SMSKR4_mem_size_BitAddressOffset 0
-#define SMSKR4_mem_size_RegisterSize 5
-
-/* Register SMSKR4 field mem_type */
-/* Type of memory connected to chip select 4 */
-#define SMSKR4_mem_type_BitAddressOffset 5
-#define SMSKR4_mem_type_RegisterSize 3
-
-/* Register SMSKR4 field reg_select */
-/* Timing parameters to associate with chip select 4 */
-#define SMSKR4_reg_select_BitAddressOffset 8
-#define SMSKR4_reg_select_RegisterSize 3
-
-/* End of Register Definition for SMSKR4 */
-
-/* Register SMSKR5 */
-/* Mask register 5 */
-#define SMSKR5 (0x0 + 0x68)
-#define SMSKR5_RegisterSize 32
-#define SMSKR5_RegisterResetValue 0x101
-#define SMSKR5_RegisterResetMask 0x0
-
-/* Register Field information for SMSKR5 */
-
-/* Register SMSKR5 field mem_size */
-/* Size of memory connected to chip select 5 */
-#define SMSKR5_mem_size_BitAddressOffset 0
-#define SMSKR5_mem_size_RegisterSize 5
-
-/* Register SMSKR5 field mem_type */
-/* Type of memory connected to chip select 5 */
-#define SMSKR5_mem_type_BitAddressOffset 5
-#define SMSKR5_mem_type_RegisterSize 3
-
-/* Register SMSKR5 field reg_select */
-/* Timing parameters to associate with chip select 5 */
-#define SMSKR5_reg_select_BitAddressOffset 8
-#define SMSKR5_reg_select_RegisterSize 3
-
-/* End of Register Definition for SMSKR5 */
-
-/* Register SMSKR6 */
-/* Mask register 6 */
-#define SMSKR6 (0x0 + 0x6c)
-#define SMSKR6_RegisterSize 32
-#define SMSKR6_RegisterResetValue 0x101
-#define SMSKR6_RegisterResetMask 0x0
-
-/* Register Field information for SMSKR6 */
-
-/* Register SMSKR6 field mem_size */
-/* Size of memory connected to chip select 6 */
-#define SMSKR6_mem_size_BitAddressOffset 0
-#define SMSKR6_mem_size_RegisterSize 5
-
-/* Register SMSKR6 field mem_type */
-/* Type of memory connected to chip select 6 */
-#define SMSKR6_mem_type_BitAddressOffset 5
-#define SMSKR6_mem_type_RegisterSize 3
-
-/* Register SMSKR6 field reg_select */
-/* Timing parameters to associate with chip select 6 */
-#define SMSKR6_reg_select_BitAddressOffset 8
-#define SMSKR6_reg_select_RegisterSize 3
-
-/* End of Register Definition for SMSKR6 */
-
-/* Register SMSKR7 */
-/* Mask register 7 */
-#define SMSKR7 (0x0 + 0x70)
-#define SMSKR7_RegisterSize 32
-#define SMSKR7_RegisterResetValue 0x101
-#define SMSKR7_RegisterResetMask 0x0
-
-/* Register Field information for SMSKR7 */
-
-/* Register SMSKR7 field mem_size */
-/* Size of memory connected to chip select 7 */
-#define SMSKR7_mem_size_BitAddressOffset 0
-#define SMSKR7_mem_size_RegisterSize 5
-
-/* Register SMSKR7 field mem_type */
-/* Type of memory connected to chip select 7 */
-#define SMSKR7_mem_type_BitAddressOffset 5
-#define SMSKR7_mem_type_RegisterSize 3
-
-/* Register SMSKR7 field reg_select */
-/* Timing parameters to associate with chip select 7 */
-#define SMSKR7_reg_select_BitAddressOffset 8
-#define SMSKR7_reg_select_RegisterSize 3
-
-/* End of Register Definition for SMSKR7 */
-
-/* Register CSALIAS0_LOW */
-/* Alias register for chip select 0 */
-#define CSALIAS0_LOW (0x0 + 0x74)
-#define CSALIAS0_LOW_RegisterSize 32
-#define CSALIAS0_LOW_RegisterResetValue 0x80000000
-#define CSALIAS0_LOW_RegisterResetMask 0x0
-
-/* Register Field information for CSALIAS0_LOW */
-
-/* Register CSALIAS0_LOW field csalias0_low */
-/* Lower aliasing register bits for chip select 0 */
-#define CSALIAS0_LOW_csalias0_low_BitAddressOffset 16
-#define CSALIAS0_LOW_csalias0_low_RegisterSize 16
-
-/* End of Register Definition for CSALIAS0_LOW */
-
-/* Register CSALIAS1_LOW */
-/* Alias register for chip select 1 */
-#define CSALIAS1_LOW (0x0 + 0x78)
-#define CSALIAS1_LOW_RegisterSize 32
-#define CSALIAS1_LOW_RegisterResetValue 0x18000000
-#define CSALIAS1_LOW_RegisterResetMask 0x0
-
-/* Register Field information for CSALIAS1_LOW */
-
-/* Register CSALIAS1_LOW field csalias1_low */
-/* Lower aliasing register bits for chip select 1 */
-#define CSALIAS1_LOW_csalias1_low_BitAddressOffset 16
-#define CSALIAS1_LOW_csalias1_low_RegisterSize 16
-
-/* End of Register Definition for CSALIAS1_LOW */
-
-/* Register CSREMAP0_LOW */
-/* Remap register for chip select 0 */
-#define CSREMAP0_LOW (0x0 + 0x84)
-#define CSREMAP0_LOW_RegisterSize 32
-#define CSREMAP0_LOW_RegisterResetValue 0x80000000
-#define CSREMAP0_LOW_RegisterResetMask 0x0
-
-/* Register Field information for CSREMAP0_LOW */
-
-/* Register CSREMAP0_LOW field csremap0_low */
-/* Lower remap register bits for chip select 0 */
-#define CSREMAP0_LOW_csremap0_low_BitAddressOffset 16
-#define CSREMAP0_LOW_csremap0_low_RegisterSize 16
-
-/* End of Register Definition for CSREMAP0_LOW */
-
-/* Register CSREMAP1_LOW */
-/* Remap register for chip select 1 */
-#define CSREMAP1_LOW (0x0 + 0x88)
-#define CSREMAP1_LOW_RegisterSize 32
-#define CSREMAP1_LOW_RegisterResetValue 0x12000000
-#define CSREMAP1_LOW_RegisterResetMask 0x0
-
-/* Register Field information for CSREMAP1_LOW */
-
-/* Register CSREMAP1_LOW field csremap1_low */
-/* Lower remap register bits for chip select 1 */
-#define CSREMAP1_LOW_csremap1_low_BitAddressOffset 16
-#define CSREMAP1_LOW_csremap1_low_RegisterSize 16
-
-/* End of Register Definition for CSREMAP1_LOW */
-
-/* Register SMTMGR_SET0 */
-/* Static memory timing register set 0 */
-#define SMTMGR_SET0 (0x0 + 0x94)
-#define SMTMGR_SET0_RegisterSize 32
-#define SMTMGR_SET0_RegisterResetValue 0x10441
-#define SMTMGR_SET0_RegisterResetMask 0x0
-
-/* Register Field information for SMTMGR_SET0 */
-
-/* Register SMTMGR_SET0 field t_rc */
-/* Read cycle time */
-#define SMTMGR_SET0_t_rc_BitAddressOffset 0
-#define SMTMGR_SET0_t_rc_RegisterSize 6
-
-/* Register SMTMGR_SET0 field t_as */
-/* Write address setup time */
-#define SMTMGR_SET0_t_as_BitAddressOffset 6
-#define SMTMGR_SET0_t_as_RegisterSize 2
-
-/* Register SMTMGR_SET0 field t_wr */
-/* Write address/data hold time */
-#define SMTMGR_SET0_t_wr_BitAddressOffset 8
-#define SMTMGR_SET0_t_wr_RegisterSize 2
-
-/* Register SMTMGR_SET0 field t_wp */
-/* Write pulse width */
-#define SMTMGR_SET0_t_wp_BitAddressOffset 10
-#define SMTMGR_SET0_t_wp_RegisterSize 6
-
-/* Register SMTMGR_SET0 field t_bta */
-/* Static memory idle cycles between "read to write", or "write to read", or "read to read when chip-select changes" for memory data bus turnaround time */
-#define SMTMGR_SET0_t_bta_BitAddressOffset 16
-#define SMTMGR_SET0_t_bta_RegisterSize 2
-
-/* Register SMTMGR_SET0 field t_prc */
-/* Page mode read cycle time */
-#define SMTMGR_SET0_t_prc_BitAddressOffset 19
-#define SMTMGR_SET0_t_prc_RegisterSize 4
-
-/* Register SMTMGR_SET0 field page_mode */
-/* Page mode support */
-#define SMTMGR_SET0_page_mode_BitAddressOffset 23
-#define SMTMGR_SET0_page_mode_RegisterSize 1
-
-/* Register SMTMGR_SET0 field page_size */
-/* Page size */
-#define SMTMGR_SET0_page_size_BitAddressOffset 24
-#define SMTMGR_SET0_page_size_RegisterSize 2
-
-/* Register SMTMGR_SET0 field ready_mode */
-/* Is memory a data-ready device? */
-#define SMTMGR_SET0_ready_mode_BitAddressOffset 26
-#define SMTMGR_SET0_ready_mode_RegisterSize 1
-
-/* Register SMTMGR_SET0 field low_freq_sync_device */
-/* Sample sm_clken before starting any static memory operation */
-#define SMTMGR_SET0_low_freq_sync_device_BitAddressOffset 27
-#define SMTMGR_SET0_low_freq_sync_device_RegisterSize 1
-
-/* Register SMTMGR_SET0 field sm_read_pipe */
-/* Number of registers inserted in the read data path */
-#define SMTMGR_SET0_sm_read_pipe_BitAddressOffset 28
-#define SMTMGR_SET0_sm_read_pipe_RegisterSize 2
-
-/* End of Register Definition for SMTMGR_SET0 */
-
-/* Register SMTMGR_SET1 */
-/* Static memory timing register set 1 */
-#define SMTMGR_SET1 (0x0 + 0x98)
-#define SMTMGR_SET1_RegisterSize 32
-#define SMTMGR_SET1_RegisterResetValue 0x7c4f5b
-#define SMTMGR_SET1_RegisterResetMask 0x0
-
-/* Register Field information for SMTMGR_SET1 */
-
-/* Register SMTMGR_SET1 field t_rc */
-/* Read cycle time */
-#define SMTMGR_SET1_t_rc_BitAddressOffset 0
-#define SMTMGR_SET1_t_rc_RegisterSize 6
-
-/* Register SMTMGR_SET1 field t_as */
-/* Write address setup time */
-#define SMTMGR_SET1_t_as_BitAddressOffset 6
-#define SMTMGR_SET1_t_as_RegisterSize 2
-
-/* Register SMTMGR_SET1 field t_wr */
-/* Write address/data hold time */
-#define SMTMGR_SET1_t_wr_BitAddressOffset 8
-#define SMTMGR_SET1_t_wr_RegisterSize 2
-
-/* Register SMTMGR_SET1 field t_wp */
-/* Write pulse width */
-#define SMTMGR_SET1_t_wp_BitAddressOffset 10
-#define SMTMGR_SET1_t_wp_RegisterSize 6
-
-/* Register SMTMGR_SET1 field t_bta */
-/* Static memory idle cycles between "read to write", or "write to read", or "read to read when chip-select changes" for memory data bus turnaround time */
-#define SMTMGR_SET1_t_bta_BitAddressOffset 16
-#define SMTMGR_SET1_t_bta_RegisterSize 2
-
-/* Register SMTMGR_SET1 field t_prc */
-/* Page mode read cycle time */
-#define SMTMGR_SET1_t_prc_BitAddressOffset 19
-#define SMTMGR_SET1_t_prc_RegisterSize 4
-
-/* Register SMTMGR_SET1 field page_mode */
-/* Page mode support */
-#define SMTMGR_SET1_page_mode_BitAddressOffset 23
-#define SMTMGR_SET1_page_mode_RegisterSize 1
-
-/* Register SMTMGR_SET1 field page_size */
-/* Page size */
-#define SMTMGR_SET1_page_size_BitAddressOffset 24
-#define SMTMGR_SET1_page_size_RegisterSize 2
-
-/* Register SMTMGR_SET1 field ready_mode */
-/* Is memory a data-ready device? */
-#define SMTMGR_SET1_ready_mode_BitAddressOffset 26
-#define SMTMGR_SET1_ready_mode_RegisterSize 1
-
-/* Register SMTMGR_SET1 field low_freq_sync_device */
-/* Sample sm_clken before starting any static memory operation */
-#define SMTMGR_SET1_low_freq_sync_device_BitAddressOffset 27
-#define SMTMGR_SET1_low_freq_sync_device_RegisterSize 1
-
-/* Register SMTMGR_SET1 field sm_read_pipe */
-/* Number of registers inserted in the read data path */
-#define SMTMGR_SET1_sm_read_pipe_BitAddressOffset 28
-#define SMTMGR_SET1_sm_read_pipe_RegisterSize 2
-
-/* End of Register Definition for SMTMGR_SET1 */
-
-/* Register SMTMGR_SET2 */
-/* Static memory timing register set 2 */
-#define SMTMGR_SET2 (0x0 + 0x9c)
-#define SMTMGR_SET2_RegisterSize 32
-#define SMTMGR_SET2_RegisterResetValue 0x1c4f5b
-#define SMTMGR_SET2_RegisterResetMask 0x0
-
-/* Register Field information for SMTMGR_SET2 */
-
-/* Register SMTMGR_SET2 field t_rc */
-/* Read cycle time */
-#define SMTMGR_SET2_t_rc_BitAddressOffset 0
-#define SMTMGR_SET2_t_rc_RegisterSize 6
-
-/* Register SMTMGR_SET2 field t_as */
-/* Write address setup time */
-#define SMTMGR_SET2_t_as_BitAddressOffset 6
-#define SMTMGR_SET2_t_as_RegisterSize 2
-
-/* Register SMTMGR_SET2 field t_wr */
-/* Write address/data hold time */
-#define SMTMGR_SET2_t_wr_BitAddressOffset 8
-#define SMTMGR_SET2_t_wr_RegisterSize 2
-
-/* Register SMTMGR_SET2 field t_wp */
-/* Write pulse width */
-#define SMTMGR_SET2_t_wp_BitAddressOffset 10
-#define SMTMGR_SET2_t_wp_RegisterSize 6
-
-/* Register SMTMGR_SET2 field t_bta */
-/* Static memory idle cycles between "read to write", or "write to read", or "read to read when chip-select changes" for memory data bus turnaround time */
-#define SMTMGR_SET2_t_bta_BitAddressOffset 16
-#define SMTMGR_SET2_t_bta_RegisterSize 2
-
-/* Register SMTMGR_SET2 field t_prc */
-/* Page mode read cycle time */
-#define SMTMGR_SET2_t_prc_BitAddressOffset 19
-#define SMTMGR_SET2_t_prc_RegisterSize 4
-
-/* Register SMTMGR_SET2 field page_mode */
-/* Page mode support */
-#define SMTMGR_SET2_page_mode_BitAddressOffset 23
-#define SMTMGR_SET2_page_mode_RegisterSize 1
-
-/* Register SMTMGR_SET2 field page_size */
-/* Page size */
-#define SMTMGR_SET2_page_size_BitAddressOffset 24
-#define SMTMGR_SET2_page_size_RegisterSize 2
-
-/* Register SMTMGR_SET2 field ready_mode */
-/* Is memory a data-ready device? */
-#define SMTMGR_SET2_ready_mode_BitAddressOffset 26
-#define SMTMGR_SET2_ready_mode_RegisterSize 1
-
-/* Register SMTMGR_SET2 field low_freq_sync_device */
-/* Sample sm_clken before starting any static memory operation */
-#define SMTMGR_SET2_low_freq_sync_device_BitAddressOffset 27
-#define SMTMGR_SET2_low_freq_sync_device_RegisterSize 1
-
-/* Register SMTMGR_SET2 field sm_read_pipe */
-/* Number of registers inserted in the read data path */
-#define SMTMGR_SET2_sm_read_pipe_BitAddressOffset 28
-#define SMTMGR_SET2_sm_read_pipe_RegisterSize 2
-
-/* End of Register Definition for SMTMGR_SET2 */
-
-/* Register FLASH_TRPDR */
-/* FLASH memory tRPD timing register */
-#define FLASH_TRPDR (0x0 + 0xa0)
-#define FLASH_TRPDR_RegisterSize 32
-#define FLASH_TRPDR_RegisterResetValue 0xc8
-#define FLASH_TRPDR_RegisterResetMask 0x0
-
-/* Register Field information for FLASH_TRPDR */
-
-/* Register FLASH_TRPDR field t_rpd */
-/* FLASH reset/power-down high to read/write delay */
-#define FLASH_TRPDR_t_rpd_BitAddressOffset 0
-#define FLASH_TRPDR_t_rpd_RegisterSize 12
-
-/* End of Register Definition for FLASH_TRPDR */
-
-/* Register SMCTLR */
-/* Static memory control register */
-#define SMCTLR (0x0 + 0xa4)
-#define SMCTLR_RegisterSize 32
-#define SMCTLR_RegisterResetValue 0x2481
-#define SMCTLR_RegisterResetMask 0x0
-
-/* Register Field information for SMCTLR */
-
-/* Register SMCTLR field sm_rp_n */
-/* FLASH reset/power-down mode */
-#define SMCTLR_sm_rp_n_BitAddressOffset 0
-#define SMCTLR_sm_rp_n_RegisterSize 1
-
-/* Register SMCTLR field wp_n */
-/* FLASH write-protection mode */
-#define SMCTLR_wp_n_BitAddressOffset 1
-#define SMCTLR_wp_n_RegisterSize 3
-
-/* Register SMCTLR field sm_data_width_set0 */
-/* Width of static meory data bus controlled by SMTMGR_SET0 */
-#define SMCTLR_sm_data_width_set0_BitAddressOffset 7
-#define SMCTLR_sm_data_width_set0_RegisterSize 3
-
-/* Register SMCTLR field sm_data_width_set1 */
-/* Width of static meory data bus controlled by SMTMGR_SET1 */
-#define SMCTLR_sm_data_width_set1_BitAddressOffset 10
-#define SMCTLR_sm_data_width_set1_RegisterSize 3
-
-/* Register SMCTLR field sm_data_width_set2 */
-/* Width of static meory data bus controlled by SMTMGR_SET2 */
-#define SMCTLR_sm_data_width_set2_BitAddressOffset 13
-#define SMCTLR_sm_data_width_set2_RegisterSize 3
-
-/* End of Register Definition for SMCTLR */
-
-/* Register EXN_MODE_REG */
-/* DDR/Mobile-SDR, Mobile-DDR extension mode register */
-#define EXN_MODE_REG (0x0 + 0xac)
-#define EXN_MODE_REG_RegisterSize 32
-#define EXN_MODE_REG_RegisterResetValue 0x0
-#define EXN_MODE_REG_RegisterResetMask 0x0
-
-/* End of Register Definition for EXN_MODE_REG */
-
-#endif /* __ASM_ARCH_SDRAM_H */
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/spi.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/spi.h
deleted file mode 100644
index 2493c7ab13..0000000000
--- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/spi.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * include/asm-arm/arch-spc300/spi.h
- *
- * Copyright (C) 2009 SPiDCOM Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_SPI_H
-#define __ASM_ARCH_SPI_H
-
-/*
- * Register address SPI_Controller
- *
- * 2007-12-10
- */
-
-#ifndef SPI_BASE
- #error "SPI_BASE macro needs to be defined before including file spi.h"
-#endif
-
-#define SPI_MASTER_SLAVE (SPI_BASE + 0x00)
-#define SPI_CTRL_CFG (SPI_BASE + 0x04)
-#define SPI_FREQ (SPI_BASE + 0x08)
-#define SPI_SER (SPI_BASE + 0x0C)
-#define SPI_CONF_TX (SPI_BASE + 0x10)
-#define SPI_CONF_RX (SPI_BASE + 0x14)
-#define SPI_REG_TX (SPI_BASE + 0x20)
-#define SPI_REG_RX (SPI_BASE + 0x24)
-#define SPI_REG_IRQ (SPI_BASE + 0x30)
-#define SPI_REG_Mask (SPI_BASE + 0x34)
-#define SPI_REG_STATUS (SPI_BASE + 0x38)
-
-#endif /* __ASM_ARCH_SPI_H */
-
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/sys_apb.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/sys_apb.h
deleted file mode 100644
index 1624483b18..0000000000
--- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/sys_apb.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * include/asm-arm/arch-spc300/sys_apb.h
- *
- * Copyright (C) 2009 SPiDCOM Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_SYS_APB_H
-#define __ASM_ARCH_SYS_APB_H
-
-#ifndef SYS_APB_BASE
- #error "SYS_APB_BASE macro needs to be defined before including file sys_apb.h"
-#endif
-
-
-#define I2S_BASE (SYS_APB_BASE+0)
-#include "i2s.h"
-
-#define MPEG_TS_BASE (SYS_APB_BASE+0x010000)
-#include "mpeg_ts.h"
-
-#define MAILBOXES_BASE (SYS_APB_BASE+0x030000)
-
-#define MARIA_REGBANK_BASE (SYS_APB_BASE+0x040000)
-#define REGBANK_BASE (SYS_APB_BASE+0x040000)
-#include "pkg_maria_regbank.h"
-
-#endif /* __ASM_ARCH_SYS_APB_H */
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/wdt.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/wdt.h
deleted file mode 100644
index 82d38d2d1a..0000000000
--- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/wdt.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright (C) 2009 SPiDCOM Technologies
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef _ARCH_ARM_SPC300_WDT_H
-#define _ARCH_ARM_SPC300_WDT_H
-
-#define WDT_DEFAULT_TIME 5 //seconds
-#define WDT_MAX_TIME 21 //seconds
-
-// Bitfields in Control Register
-#define WDT_EN_SHIFT 0
-#define WDT_EN_SIZE 1
-#define WDT_RMOD_SHIFT 1
-#define WDT_RMOD_SIZE 1
-#define WDT_RPL_SHIFT 2
-#define WDT_RPL_SIZE 3
-
-// Bitfields in Timeout Range Register
-#define WDT_TOP_SHIFT 0
-#define WDT_TOP_SIZE 4
-#define WDT_TOP_INIT_SHIFT 4
-#define WDT_TOP_INIT_SIZE 4
-
-// Bitfields in Current Counter Register
-#define WDT_CCV_SHIFT 0
-#define WDT_CCV_SIZE 32
-
-// Bitfields in Counter Restart Register
-#define WDT_CR_SHIFT 0
-#define WDT_CR_SIZE 8
-#define WDT_CR_VAL 0x76
-
-// Bitfields in Interrupt Status Register
-#define WDT_IT_STAT_SHIFT 0
-#define WDT_IT_STAT_SIZE 1
-
-// Bitfields in Clear Interrupt Register
-#define WDT_IT_CLEAR_SHIFT 0
-#define WDT_IT_CLEAR_SIZE 1
-
-// Bit manipulation macros
-#define WDT_BIT(name) \
- (1 << WDT_##name##_SHIFT)
-#define WDT_BF(name,value) \
- (((value) & ((1 << WDT_##name##_SIZE) - 1)) << WDT_##name##_SHIFT)
-#define WDT_BFEXT(name,value) \
- (((value) >> WDT_##name##_SHIFT) & ((1 << WDT_##name##_SIZE) - 1))
-#define WDT_BFINS(name,value,old) \
- ( ((old) & ~(((1 << WDT_##name##_SIZE) - 1) << WDT_##name##_SHIFT)) \
- | WDT_BF(name,value))
-
-#endif /* _ARCH_ARM_SPC300_WDT_H */
diff --git a/common/include/asm/arch/ips/gic.h b/common/include/asm/arch/ips/gic.h
index ed7474980d..5b2448b31a 100644
--- a/common/include/asm/arch/ips/gic.h
+++ b/common/include/asm/arch/ips/gic.h
@@ -22,6 +22,7 @@
#include <asm/arch/ips/ips_access.h>
+#ifndef __ASSEMBLY__
/** Virtual Address for gic */
#define IRQ_INTEN_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_INTEN_OFFSET)))
#define IRQ_INTMASK_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_INTMASK_OFFSET)))
@@ -70,6 +71,7 @@
#define IRQ_P29_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P29_OFFSET)))
#define IRQ_P30_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P30_OFFSET)))
#define IRQ_P31_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P31_OFFSET)))
-
#define IRQ_PRIO_ADDR_VA ((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P0_OFFSET))
+#endif /* __ASSEMBLY__ */
+
#endif /* __ASM_ARCH_IPS_GIC_H */
diff --git a/common/include/asm/arch/ips/gpio.h b/common/include/asm/arch/ips/gpio.h
index d821e8b9e5..ceecd3fc93 100644
--- a/common/include/asm/arch/ips/gpio.h
+++ b/common/include/asm/arch/ips/gpio.h
@@ -22,8 +22,8 @@
#include <asm/arch/ips/ips_access.h>
+#ifndef __ASSEMBLY__
/** Virtual Address for gpios */
-
#define GPIO_SWPORTA_DR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_GPIO_BASE) + GPIO_SWPORTA_DR_OFFSET)))
#define GPIO_SWPORTA_DDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_GPIO_BASE) + GPIO_SWPORTA_DDR_OFFSET)))
#define GPIO_SWPORTA_CTL_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_GPIO_BASE) + GPIO_SWPORTA_CTL_OFFSET)))
@@ -56,5 +56,6 @@
extern void spc300_init_gpio(void);
extern int gpio_write(int no, int value);
+#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_IPS_GPIO_H */
diff --git a/common/include/asm/arch/ips/hardware/bus_sys.h b/common/include/asm/arch/ips/hardware/bus_sys.h
index 8484aa0b96..0e48aacb99 100644
--- a/common/include/asm/arch/ips/hardware/bus_sys.h
+++ b/common/include/asm/arch/ips/hardware/bus_sys.h
@@ -44,7 +44,16 @@
#include "sdram.h"
#endif
+#if defined (CONFIG_CHIP_FEATURE_MIU_CTRL)
+#define MIU_REG_BASE (0xC8050000)
+#define MIU_ATOP_REG_BASE (0xC8060000)
+#include "miu.h"
+#endif
+
#define ETHERNET_CTRL_BASE (0xD0000000)
#include "ethernet_ctrl.h"
+#define DSP_BASE (0xA0000000)
+#include "dsp.h"
+
#endif /* __ASM_ARCH_IPS_HW_BUS_SYS_H */
diff --git a/common/include/asm/arch/ips/hardware/dsp.h b/common/include/asm/arch/ips/hardware/dsp.h
new file mode 100644
index 0000000000..f8040fb85d
--- /dev/null
+++ b/common/include/asm/arch/ips/hardware/dsp.h
@@ -0,0 +1,31 @@
+/*
+ * include/asm/arch/ips/hardware/dsp.h
+ *
+ * (C) Copyright 2008 SPiDCOM Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_IPS_HW_DSP_H
+#define __ASM_ARCH_IPS_HW_DSP_H
+
+#ifndef DSP_BASE
+ #error "DSP_BASE macro needs to be defined before including file dsp.h"
+#endif
+
+#define DSP_PRATIC_OFFSET (0x1000)
+#define DSP_PRATIC_BASE (DSP_BASE+DSP_PRATIC_OFFSET)
+#define DSP_PRATIC_STA_LOCAL_TIMER (DSP_PRATIC_BASE+0x10)
+
+#endif /* __ASM_ARCH_IPS_HW_DSP_H */
diff --git a/common/include/asm/arch/ips/hardware/ethernet_ctrl.h b/common/include/asm/arch/ips/hardware/ethernet_ctrl.h
index 88389cd888..6104614b97 100644
--- a/common/include/asm/arch/ips/hardware/ethernet_ctrl.h
+++ b/common/include/asm/arch/ips/hardware/ethernet_ctrl.h
@@ -37,6 +37,18 @@
#define Register1_RegisterResetValue 0x0
#define Register1_RegisterResetMask 0x0
+/* Register Register2 */
+/* MAC hash table high Filter */
+#define Register2 (GMAC_BaseAddress + 0x8)
+#define Register2_RegisterSize 32
+#define Register2_RegisterResetValue 0x0
+#define Register2_RegisterResetMask 0x0
+/* Register Register3 */
+/* MAC hash table low Filter */
+#define Register3 (GMAC_BaseAddress + 0xC)
+#define Register3_RegisterSize 32
+#define Register3_RegisterResetValue 0x0
+#define Register3_RegisterResetMask 0x0
/* Register Register4 */
/* GMII Address Register */
@@ -617,7 +629,7 @@
#define Register119_RegisterResetMask 0x0
-#define DMA_BaseAddress (ETHERNET_CTRL_BASE + 0x1000)
+#define DMA_BaseAddress (ETHERNET_CTRL_BASE + 0x1000)
/* Register Register0 */
/* Bus Mode Register */
diff --git a/common/include/asm/arch/ips/hardware/gpdma.h b/common/include/asm/arch/ips/hardware/gpdma.h
index 7c5ab26a6e..91d25b1c00 100644
--- a/common/include/asm/arch/ips/hardware/gpdma.h
+++ b/common/include/asm/arch/ips/hardware/gpdma.h
@@ -118,6 +118,7 @@
#define GPDMA_CTL0 (GPDMA_BASE+0x018)
#define GPDMA_CTL0h (GPDMA_BASE+0x018+4)
#define GPDMA_CFG0 (GPDMA_BASE+0x040)
+#define GPDMA_RawTfr (GPDMA_BASE+0x2c0)
#define GPDMA_MaskTfr (GPDMA_BASE+0x310)
#define GPDMA_MaskBlock (GPDMA_BASE+0x318)
#define GPDMA_ClearTfr (GPDMA_BASE+0x338)
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/miu.h b/common/include/asm/arch/ips/hardware/miu.h
index eb74a5177b..7f0f4ce3cb 100644
--- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/miu.h
+++ b/common/include/asm/arch/ips/hardware/miu.h
@@ -1,12 +1,12 @@
/*
- * include/asm-arm/arch-spc300/miu.h
+ * include/asm/arch/ips/hardware/miu.h
*
- * Copyright (C) 2012 SPiDCOM Technologies
+ * (C) Copyright 2008 SPiDCOM Technologies.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -15,14 +15,13 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
+#ifndef __ASM_ARCH_IPS_HW_MIU_H
+#define __ASM_ARCH_IPS_HW_MIU_H
-#ifndef __ASM_ARCH_MIU_H
-#define __ASM_ARCH_MIU_H
#define MIU_INIT_DONE_REG 0
#define MIU_INIT_DONE_BIT 15
-#endif /* __ASM_ARCH_MIU_H */
+#endif /* __ASM_ARCH_IPS_HW_MIU_H */
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/mpeg_ts.h b/common/include/asm/arch/ips/hardware/mpeg_ts.h
index e711386824..0199439c75 100644
--- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/mpeg_ts.h
+++ b/common/include/asm/arch/ips/hardware/mpeg_ts.h
@@ -1,12 +1,12 @@
/*
- * include/asm-arm/arch-spc300/mpeg_ts.h
+ * include/asm/arch/ips/hardware/mpeg_ts.h
*
- * Copyright (C) 2009 SPiDCOM Technologies
+ * (C) Copyright 2008 SPiDCOM Technologies.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -15,13 +15,10 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
-
-#ifndef __ASM_ARCH_MPEG_TS_H
-#define __ASM_ARCH_MPEG_TS_H
-
+#ifndef __ASM_ARCH_IPS_HW_MPEG_TS_H
+#define __ASM_ARCH_IPS_HW_MPEG_TS_H
#ifndef MPEG_TS_BASE
#error "MPEG_TS_BASE macro needs to be defined before including file mpeg_ts.h"
#endif
@@ -37,4 +34,4 @@
#define MPEG_TS_LOCAL_TIMER (MPEG_TS_BASE + 0x1C)
#define MPEG_TS_TX_POOL_TIMER (MPEG_TS_BASE + 0x20)
-#endif /* __ASM_ARCH_MPEG_TS_H */
+#endif /* __ASM_ARCH_IPS_HW_MPEG_TS_H */
diff --git a/common/include/asm/arch/ips/hardware/pcm.h b/common/include/asm/arch/ips/hardware/pcm.h
index 3fd15b3642..1eb8bb25e6 100644
--- a/common/include/asm/arch/ips/hardware/pcm.h
+++ b/common/include/asm/arch/ips/hardware/pcm.h
@@ -21,7 +21,7 @@
#define __ASM_ARCH_IPS_HW_PCM_H
/*
- * Register address SPI_Controller
+ * Register address of PCM Controller
*
* 2007-12-10
*/
diff --git a/common/include/asm/arch/ips/hardware/pkg_maria_regbank.h b/common/include/asm/arch/ips/hardware/pkg_maria_regbank.h
index e9420764b1..839f433c86 100644
--- a/common/include/asm/arch/ips/hardware/pkg_maria_regbank.h
+++ b/common/include/asm/arch/ips/hardware/pkg_maria_regbank.h
@@ -37,6 +37,7 @@
#define RB_ICM_PRIORITY_OFFSET (0x11c)
#define RB_LEON_ADD_START_OFFSET (0x120)
#define RB_LEON_TICK_CNT_OFFSET (0x124)
+#define RB_DSP_HLOCK_OFFSET (0x128)
#define RB_PIO_CONFIG_OFFSET (0x200)
#define RB_PIO_ENABLE_OFFSET (0x204)
#define RB_GPIO_0_CONFIG_OFFSET (0x208)
@@ -94,6 +95,7 @@
#define RB_CLK_DIV_STAT_MPG_INT_OFFSET (0x4CC)
#define RB_CLK_SEL_MPG_OFFSET (0x4D0)
#define RB_CLK_SEL_STAT_MPG_OFFSET (0x4D4)
+#define RB_CLK_POL_MPG_OFFSET (0x4D8)
#define RB_CLK_CMD_SPI_OFFSET (0x4E0)
#define RB_CLK_STAT_SPI_OFFSET (0x4E4)
#define RB_CLK_CMD_I2S_OFFSET (0x4F0)
@@ -104,6 +106,7 @@
#define RB_CLK_STAT_PCM_OFFSET (0x504)
#define RB_CLK_DIV_PCM_OFFSET (0x508)
#define RB_CLK_DIV_STAT_PCM_OFFSET (0x50C)
+#define RB_CLK_POL_PCM_OFFSET (0x510)
#define RB_CLK_DIV_T1_OFFSET (0x518)
#define RB_CLK_DIV_STAT_T1_OFFSET (0x51C)
#define RB_CLK_DIV_T2_OFFSET (0x528)
@@ -153,6 +156,8 @@
#define RB_RST_GROUP_OFFSET (0x708)
#define RB_RST_MODULE_OFFSET (0x70C)
#define RB_RST_GMASK_OFFSET (0x710)
+#define RB_DINI_UART_SELECT_OFFSET (0x900)
+#define RB_DINI_SPARE_1_OFFSET (0x904)
#define SLAVE_MARIA_REGBANK (0x8030)
#define RB_PACKAGE (MARIA_REGBANK_BASE+0x000)
@@ -172,6 +177,7 @@
#define RB_ICM_PRIORITY (MARIA_REGBANK_BASE+0x11c)
#define RB_LEON_ADD_START (MARIA_REGBANK_BASE+0x120)
#define RB_LEON_TICK_CNT (MARIA_REGBANK_BASE+0x124)
+#define RB_DSP_HLOCK (MARIA_REGBANK_BASE+0x128)
#define LEON_ADD_START_RESET (0x00011000)
#define LEON_TICK_CNT_RESET (0x1d4c)
#define RB_PIO_CONFIG (MARIA_REGBANK_BASE+0x200)
@@ -274,6 +280,7 @@
#define RB_CLK_SEL_STAT_MPG (MARIA_REGBANK_BASE+0x4D4)
#define CLK_SEL_MPG_INT (0x0)
#define CLK_SEL_MPG_EXT (0x1)
+#define RB_CLK_POL_MPG (MARIA_REGBANK_BASE+0x4D8)
#define RB_CLK_CMD_SPI (MARIA_REGBANK_BASE+0x4E0)
#define RB_CLK_STAT_SPI (MARIA_REGBANK_BASE+0x4E4)
#define RB_CLK_CMD_I2S (MARIA_REGBANK_BASE+0x4F0)
@@ -284,6 +291,7 @@
#define RB_CLK_STAT_PCM (MARIA_REGBANK_BASE+0x504)
#define RB_CLK_DIV_PCM (MARIA_REGBANK_BASE+0x508)
#define RB_CLK_DIV_STAT_PCM (MARIA_REGBANK_BASE+0x50C)
+#define RB_CLK_POL_PCM (MARIA_REGBANK_BASE+0x510)
#define RB_CLK_DIV_T1 (MARIA_REGBANK_BASE+0x518)
#define RB_CLK_DIV_STAT_T1 (MARIA_REGBANK_BASE+0x51C)
#define RB_CLK_DIV_T2 (MARIA_REGBANK_BASE+0x528)
@@ -314,6 +322,14 @@
#define RB_SPLL_EN (MARIA_REGBANK_BASE+0x594)
#define RB_SPLL_DEBUG (MARIA_REGBANK_BASE+0x598)
#define RB_SPLL_SSCGNRST (MARIA_REGBANK_BASE+0x59C)
+#define PLL_CMD_ON (0x0)
+#define PLL_CMD_OFF (0x1)
+#define PLL_CMD_BYPASS (0x1)
+#define PLL_CMD_PLL (0x0)
+#define PLL_IS_BYPASS (0x1)
+#define PLL_IS_PLL (0x2)
+#define PLL_LBWS_OFF (0x0)
+#define PLL_LBWS_ON (0x1)
#define RB_CLK_CMD_SDR (MARIA_REGBANK_BASE+0x5A0)
#define RB_CLK_STAT_SDR (MARIA_REGBANK_BASE+0x5A4)
#define RB_CLK_CMD_OUT25 (MARIA_REGBANK_BASE+0x5B0)
@@ -362,5 +378,10 @@
#define RB_RST_GMASK (MARIA_REGBANK_BASE+0x710)
#define RB_FCM3_UART_SELECT (MARIA_REGBANK_BASE+0x800)
#define RB_FCM3_AD_SPIEN (MARIA_REGBANK_BASE+0x804)
+#define RB_DINI_UART_SELECT (MARIA_REGBANK_BASE+0x900)
+#define RB_DINI_UART_SELECT_LEON (0x0)
+#define RB_DINI_UART_SELECT_ARM (0x1)
+#define RB_DINI_SPARE_1 (MARIA_REGBANK_BASE+0x904)
+#define RB_DINI_SPARE_1_ETH_RX_CLOCK_INVERT (0x800)
#endif /* __ASM_ARCH_IPS_HW_PKG_MARIA_REGBANK_H */
diff --git a/common/include/asm/arch/ips/hardware/sdram.h b/common/include/asm/arch/ips/hardware/sdram.h
index ed25de04b4..8634b42b28 100644
--- a/common/include/asm/arch/ips/hardware/sdram.h
+++ b/common/include/asm/arch/ips/hardware/sdram.h
@@ -33,21 +33,25 @@
/* Number of bank address bits */
#define SCONR_s_bank_addr_width_BitAddressOffset 3
#define SCONR_s_bank_addr_width_RegisterSize 2
+#define SCONR_s_bank_addr_width_RegisterMask (3<<SCONR_s_bank_addr_width_BitAddressOffset)
/* Register SCONR field s_row_addr_width */
/* Number of address bits for row address */
#define SCONR_s_row_addr_width_BitAddressOffset 5
#define SCONR_s_row_addr_width_RegisterSize 4
+#define SCONR_s_row_addr_width_RegisterMask (0x0f<<SCONR_s_row_addr_width_BitAddressOffset)
/* Register SCONR field s_col_addr_width */
/* Number of address bits for column address */
#define SCONR_s_col_addr_width_BitAddressOffset 9
#define SCONR_s_col_addr_width_RegisterSize 4
+#define SCONR_s_col_addr_width_RegisterMask (0x0f<<SCONR_s_col_addr_width_BitAddressOffset)
/* Register SCONR field s_data_width */
/* SDRAM data width */
#define SCONR_s_data_width_BitAddressOffset 13
#define SCONR_s_data_width_RegisterSize 2
+#define SCONR_s_data_width_RegisterMask (3<<SCONR_s_data_width_BitAddressOffset)
/* Register SCONR field s_sa */
/* Serial presence detect address bits */
diff --git a/common/include/asm/arch/ips/hardware/sys_apb.h b/common/include/asm/arch/ips/hardware/sys_apb.h
index b463299df2..883015d313 100644
--- a/common/include/asm/arch/ips/hardware/sys_apb.h
+++ b/common/include/asm/arch/ips/hardware/sys_apb.h
@@ -29,6 +29,7 @@
#include "i2s.h"
#define MPEG_TS_BASE (SYS_APB_BASE+0x010000)
+#include "mpeg_ts.h"
#define MAILBOXES_BASE (SYS_APB_BASE+0x030000)
diff --git a/common/include/asm/arch/ips/ips_access.h b/common/include/asm/arch/ips/ips_access.h
index 93ca010b86..efd7d31c67 100644
--- a/common/include/asm/arch/ips/ips_access.h
+++ b/common/include/asm/arch/ips/ips_access.h
@@ -22,6 +22,8 @@
#include <asm/arch/ips/hardware/bus_sys.h>
+#ifdef CONFIG_MMU
+
/* Where are in virtual memory the IO devices (timers, system controllers and so on) */
#define IO_BASE 0xF0000000 // VA of IO
#define IO_SIZE 0x0B000000 // How much?
@@ -29,4 +31,11 @@
/* Macro to get at IO space when running virtually */
#define IO_ADDRESS(x) (((x) >> 4) + IO_BASE)
+#else
+
+/* When there is no MMU, IO space and physical space are the same. */
+#define IO_ADDRESS(x) (x)
+
+#endif /* CONFIG_MMU */
+
#endif /* __ASM_ARCH_IPS_IPS_ACCESS_H */
diff --git a/common/include/asm/arch/ips/regbank.h b/common/include/asm/arch/ips/regbank.h
index ac3f26361c..0a4288eae2 100644
--- a/common/include/asm/arch/ips/regbank.h
+++ b/common/include/asm/arch/ips/regbank.h
@@ -22,6 +22,7 @@
#include <asm/arch/ips/ips_access.h>
+#ifndef __ASSEMBLY__
/** Virtual Address for regbank */
#define RB_PACKAGE_VA (*((volatile uint32_t *)(IO_ADDRESS(MARIA_REGBANK_BASE) + RB_PACKAGE_OFFSET)))
#define RB_SDRAM_RETURN_LAT_VA (*((volatile uint32_t *)(IO_ADDRESS(MARIA_REGBANK_BASE) + RB_SDRAM_RETURN_LAT_OFFSET)))
@@ -152,5 +153,6 @@
#define RB_RST_GROUP_VA (*((volatile uint32_t *)(IO_ADDRESS(MARIA_REGBANK_BASE) + RB_RST_GROUP_OFFSET)))
#define RB_RST_MODULE_VA (*((volatile uint32_t *)(IO_ADDRESS(MARIA_REGBANK_BASE) + RB_RST_MODULE_OFFSET)))
#define RB_RST_GMASK_VA (*((volatile uint32_t *)(IO_ADDRESS(MARIA_REGBANK_BASE) + RB_RST_GMASK_OFFSET)))
+#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_IPS_REGBANK_H */
diff --git a/common/include/asm/arch/ips/spi.h b/common/include/asm/arch/ips/spi.h
index df03cac0f6..a6e660e2ca 100644
--- a/common/include/asm/arch/ips/spi.h
+++ b/common/include/asm/arch/ips/spi.h
@@ -35,6 +35,7 @@
#define SPI_REG_MASK_OFFSET (SPI_REG_Mask - SPI_BASE)
#define SPI_REG_STATUS_OFFSET (SPI_REG_STATUS - SPI_BASE)
+#ifndef __ASSEMBLY__
/** Virtual Address for spi registers */
#define SPI_MASTER_SLAVE_VA (*((volatile uint32_t *)(IO_ADDRESS(SPI_BASE) + SPI_MASTER_SLAVE_OFFSET)))
#define SPI_CTRL_CFG_VA (*((volatile uint32_t *)(IO_ADDRESS(SPI_BASE) + SPI_CTRL_CFG_OFFSET)))
@@ -48,6 +49,7 @@
#define SPI_REG_IRQ_VA (*((volatile uint32_t *)(IO_ADDRESS(SPI_BASE) + SPI_REG_IRQ_OFFSET)))
#define SPI_REG_MASK_VA (*((volatile uint32_t *)(IO_ADDRESS(SPI_BASE) + SPI_REG_MASK_OFFSET)))
#define SPI_REG_STATUS_VA (*((volatile uint32_t *)(IO_ADDRESS(SPI_BASE) + SPI_REG_STATUS_OFFSET)))
+#endif /* __ASSEMBLY__ */
// Bitfields in MASTER_SLAVE
#define SPI_MODE_SHIFT 0
diff --git a/common/include/asm/arch/ips/timer.h b/common/include/asm/arch/ips/timer.h
index 7dc49aa0ca..084a9b74cd 100644
--- a/common/include/asm/arch/ips/timer.h
+++ b/common/include/asm/arch/ips/timer.h
@@ -22,6 +22,7 @@
#include <asm/arch/ips/ips_access.h>
+#ifndef __ASSEMBLY__
/** Virtual Address for timer 1 */
#define TIMER1BASE_1_VA (IO_ADDRESS(ARM_TIMER1_BASE) + 0x00)
#define TIMER2BASE_1_VA (IO_ADDRESS(ARM_TIMER1_BASE) + 0x14)
@@ -89,6 +90,7 @@
#define TIMERSEOI_2_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_TIMER2_BASE) + TIMERSEOIOFF_2)))
#define TIMERSINTSTAT_2_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_TIMER2_BASE) + TIMERSINTSTATOFF_2)))
#define TIMERSRAWINTSTAT_2_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_TIMER2_BASE) + TIMERSRAWINTSTATOFF_2)))
+#endif /* __ASSEMBLY__ */
#define TIMER_ENABLE_MASK (1<<0)
#define TIMER_MODE_MASK (1<<1)
diff --git a/common/include/asm/arch/ips/wdt.h b/common/include/asm/arch/ips/wdt.h
index 6e4c1c1bfc..d3eb59bd57 100644
--- a/common/include/asm/arch/ips/wdt.h
+++ b/common/include/asm/arch/ips/wdt.h
@@ -22,8 +22,8 @@
#include <asm/arch/ips/ips_access.h>
+#ifndef __ASSEMBLY__
/** Virtual Address for watchdog timer */
-
#define WDT_CR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_WDT_BASE) + WDTControlReg_Offset)))
#define WDT_TORR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_WDT_BASE) + WDTTimeoutRangeReg_Offset)))
#define WDT_CCVR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_WDT_BASE) + WDTCurrentCounterValueReg_Offset)))
@@ -40,6 +40,7 @@
#define WDT_COMP_TYPE_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_WDT_BASE) + WDTCOMP_TYPE_Offset)))
#define WDT_CRR_PA (*((volatile uint32_t *)(ARM_WDT_BASE + WDTCounterResetReg_Offset)))
+#endif /* __ASSEMBLY__ */
// Bitfields in Control Register
#define WDT_EN_SHIFT 0
@@ -83,4 +84,7 @@
( ((old) & ~(((1 << WDT_##name##_SIZE) - 1) << WDT_##name##_SHIFT)) \
| WDT_BF(name,value))
+#define WDT_DEFAULT_TIME 5 //seconds
+#define WDT_MAX_TIME 21 //seconds
+
#endif /* __ASM_ARCH_IPS_WDT_H */