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/*
 * include/asm-arm/arch-spc300/ethernet_ctrl.h
 *
 * Copyright (C) 2009 SPiDCOM Technologies
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __ASM_ARCH_ETHERNET_CTRL_H
#define __ASM_ARCH_ETHERNET_CTRL_H

#define GMAC_BaseAddress (ETHERNET_CTRL_BASE)

/* Register Register0 */
/* MAC Configuration Register */
#define Register0 (GMAC_BaseAddress )
#define Register0_RegisterSize 32
#define Register0_RegisterResetValue 0x0
#define Register0_RegisterResetMask 0x0


/* Register Register1 */
/* MAC Frame Filter */
#define Register1 (GMAC_BaseAddress + 0x4)
#define Register1_RegisterSize 32
#define Register1_RegisterResetValue 0x0
#define Register1_RegisterResetMask 0x0

/* Register Register2 */
/* MAC hash table high Filter */
#define Register2 (GMAC_BaseAddress + 0x8)
#define Register2_RegisterSize 32
#define Register2_RegisterResetValue 0x0
#define Register2_RegisterResetMask 0x0
/* Register Register3 */
/* MAC hash table low Filter */
#define Register3 (GMAC_BaseAddress + 0xC)
#define Register3_RegisterSize 32
#define Register3_RegisterResetValue 0x0
#define Register3_RegisterResetMask 0x0

/* Register Register4 */
/* GMII Address Register */
#define Register4 (GMAC_BaseAddress + 0x10)
#define Register4_RegisterSize 32
#define Register4_RegisterResetValue 0x0
#define Register4_RegisterResetMask 0x0

/* Register Register5 */
/* GMII Data Register */
#define Register5 (GMAC_BaseAddress + 0x14)
#define Register5_RegisterSize 32
#define Register5_RegisterResetValue 0x0
#define Register5_RegisterResetMask 0x0

/* Register Register6 */
/* Flow Control Register */
#define Register6 (GMAC_BaseAddress + 0x18)
#define Register6_RegisterSize 32
#define Register6_RegisterResetValue 0x0
#define Register6_RegisterResetMask 0x0


/* Register Register7 */
/* VLAN Tag Register */
#define Register7 (GMAC_BaseAddress + 0x1c)
#define Register7_RegisterSize 32
#define Register7_RegisterResetValue 0x0
#define Register7_RegisterResetMask 0x0

/* Register Register8 */
/* Version Register */
#define Register8 (GMAC_BaseAddress + 0x20)
#define Register8_RegisterSize 32
#define Register8_RegisterResetValue 0x33
#define Register8_RegisterResetMask 0x0

/* Register Register14 */
/* Interrupt Register */
#define Register14 (GMAC_BaseAddress + 0x38)
#define Register14_RegisterSize 32
#define Register14_RegisterResetValue 0x0
#define Register14_RegisterResetMask 0x0

/* Register Register15 */
/* Interrupt Mask Register */
#define Register15 (GMAC_BaseAddress + 0x3c)
#define Register15_RegisterSize 32
#define Register15_RegisterResetValue 0x0
#define Register15_RegisterResetMask 0x0

/* Register Register16 */
/* MAC Address0 High Register */
#define Register16 (GMAC_BaseAddress + 0x40)
#define Register16_RegisterSize 32
#define Register16_RegisterResetValue 0x8000ffff
#define Register16_RegisterResetMask 0x0

/* Register Register17 */
/* MAC Address0 Low Register */
#define Register17 (GMAC_BaseAddress + 0x44)
#define Register17_RegisterSize 32
#define Register17_RegisterResetValue 0xffffffff
#define Register17_RegisterResetMask 0x0

/* Register Register18 */
/* MAC Address1 High Register */
#define Register18 (GMAC_BaseAddress + 0x48)
#define Register18_RegisterSize 32
#define Register18_RegisterResetValue 0xffff
#define Register18_RegisterResetMask 0x0

/* Register Register19 */
/* MAC Address1 Low Register */
#define Register19 (GMAC_BaseAddress + 0x4c)
#define Register19_RegisterSize 32
#define Register19_RegisterResetValue 0xffffffff
#define Register19_RegisterResetMask 0x0


/* Register Register20 */
/* MAC Address2 High Register */
#define Register20 (GMAC_BaseAddress + 0x50)
#define Register20_RegisterSize 32
#define Register20_RegisterResetValue 0xffff
#define Register20_RegisterResetMask 0x0

/* Register Register21 */
/* MAC Address2 Low Register */
#define Register21 (GMAC_BaseAddress + 0x54)
#define Register21_RegisterSize 32
#define Register21_RegisterResetValue 0xffffffff
#define Register21_RegisterResetMask 0x0

/* Register Register22 */
/* MAC Address3 High Register */
#define Register22 (GMAC_BaseAddress + 0x58)
#define Register22_RegisterSize 32
#define Register22_RegisterResetValue 0xffff
#define Register22_RegisterResetMask 0x0

/* Register Register23 */
/* MAC Address3 Low Register */
#define Register23 (GMAC_BaseAddress + 0x5c)
#define Register23_RegisterSize 32
#define Register23_RegisterResetValue 0xffffffff
#define Register23_RegisterResetMask 0x0

/* Register Register24 */
/* MAC Address4 High Register */
#define Register24 (GMAC_BaseAddress + 0x60)
#define Register24_RegisterSize 32
#define Register24_RegisterResetValue 0xffff
#define Register24_RegisterResetMask 0x0

/* Register Register25 */
/* MAC Address4 Low Register */
#define Register25 (GMAC_BaseAddress + 0x64)
#define Register25_RegisterSize 32
#define Register25_RegisterResetValue 0xffffffff
#define Register25_RegisterResetMask 0x0

/* Register Register26 */
/* MAC Address5 High Register */
#define Register26 (GMAC_BaseAddress + 0x68)
#define Register26_RegisterSize 32
#define Register26_RegisterResetValue 0xffff
#define Register26_RegisterResetMask 0x0

/* Register Register27 */
/* MAC Address5 Low Register */
#define Register27 (GMAC_BaseAddress + 0x6c)
#define Register27_RegisterSize 32
#define Register27_RegisterResetValue 0xffffffff
#define Register27_RegisterResetMask 0x0

/* Register Register28 */
/* MAC Address6 High Register */
#define Register28 (GMAC_BaseAddress + 0x70)
#define Register28_RegisterSize 32
#define Register28_RegisterResetValue 0xffff
#define Register28_RegisterResetMask 0x0

/* Register Register29 */
/* MAC Address6 Low Register */
#define Register29 (GMAC_BaseAddress + 0x74)
#define Register29_RegisterSize 32
#define Register29_RegisterResetValue 0xffffffff
#define Register29_RegisterResetMask 0x0

/* Register Field information for Register29 */

/* Register Register30 */
/* MAC Address7 High Register */
#define Register30 (GMAC_BaseAddress + 0x78)
#define Register30_RegisterSize 32
#define Register30_RegisterResetValue 0xffff
#define Register30_RegisterResetMask 0x0

/* Register Register31 */
/* MAC Address7 Low Register */
#define Register31 (GMAC_BaseAddress + 0x7c)
#define Register31_RegisterSize 32
#define Register31_RegisterResetValue 0xffffffff
#define Register31_RegisterResetMask 0x0

/* Register Register64 */
/* mmc_cntrl */
#define Register64 (GMAC_BaseAddress + 0x100)
#define Register64_RegisterSize 32
#define Register64_RegisterResetValue 0x0
#define Register64_RegisterResetMask 0x0

/* Register Register65 */
/* mmc_intr_rx */
#define Register65 (GMAC_BaseAddress + 0x104)
#define Register65_RegisterSize 32
#define Register65_RegisterResetValue 0x0
#define Register65_RegisterResetMask 0x0

/* Register Register66 */
/* mmc_intr_tx */
#define Register66 (GMAC_BaseAddress + 0x108)
#define Register66_RegisterSize 32
#define Register66_RegisterResetValue 0x0
#define Register66_RegisterResetMask 0x0

/* Register Register67 */
/* mmc_intr_mask_rx */
#define Register67 (GMAC_BaseAddress + 0x10c)
#define Register67_RegisterSize 32
#define Register67_RegisterResetValue 0x0
#define Register67_RegisterResetMask 0x0

/* Register Register68 */
/* mmc_intr_mask_tx */
#define Register68 (GMAC_BaseAddress + 0x110)
#define Register68_RegisterSize 32
#define Register68_RegisterResetValue 0x0
#define Register68_RegisterResetMask 0x0

/* Register Register69 */
/* txoctetcount_gb */
#define Register69 (GMAC_BaseAddress + 0x114)
#define Register69_RegisterSize 32
#define Register69_RegisterResetValue 0x0
#define Register69_RegisterResetMask 0x0


/* Register Register70 */
/* txfrmecount_gb */
#define Register70 (GMAC_BaseAddress + 0x118)
#define Register70_RegisterSize 32
#define Register70_RegisterResetValue 0x0
#define Register70_RegisterResetMask 0x0


/* Register Register71 */
/* txbroadcastframes_g */
#define Register71 (GMAC_BaseAddress + 0x11c)
#define Register71_RegisterSize 32
#define Register71_RegisterResetValue 0x0
#define Register71_RegisterResetMask 0x0


/* Register Register72 */
/* txmulticastframes_g */
#define Register72 (GMAC_BaseAddress + 0x120)
#define Register72_RegisterSize 32
#define Register72_RegisterResetValue 0x0
#define Register72_RegisterResetMask 0x0


/* Register Register73 */
/* tx64octets_gb */
#define Register73 (GMAC_BaseAddress + 0x124)
#define Register73_RegisterSize 32
#define Register73_RegisterResetValue 0x0
#define Register73_RegisterResetMask 0x0


/* Register Register74 */
/* tx65to127octets_gb */
#define Register74 (GMAC_BaseAddress + 0x128)
#define Register74_RegisterSize 32
#define Register74_RegisterResetValue 0x0
#define Register74_RegisterResetMask 0x0


/* Register Register75 */
/* tx128to255octets_gb */
#define Register75 (GMAC_BaseAddress + 0x12c)
#define Register75_RegisterSize 32
#define Register75_RegisterResetValue 0x0
#define Register75_RegisterResetMask 0x0

/* Register Register76 */
/* tx256to511octets_gb */
#define Register76 (GMAC_BaseAddress + 0x130)
#define Register76_RegisterSize 32
#define Register76_RegisterResetValue 0x0
#define Register76_RegisterResetMask 0x0

/* Register Register77 */
/* tx512to1023octets_gb */
#define Register77 (GMAC_BaseAddress + 0x134)
#define Register77_RegisterSize 32
#define Register77_RegisterResetValue 0x0
#define Register77_RegisterResetMask 0x0


/* Register Register78 */
/* tx1024tomaxoctets_gb */
#define Register78 (GMAC_BaseAddress + 0x138)
#define Register78_RegisterSize 32
#define Register78_RegisterResetValue 0x0
#define Register78_RegisterResetMask 0x0


/* Register Register79 */
/* txunicastframes_gb */
#define Register79 (GMAC_BaseAddress + 0x13c)
#define Register79_RegisterSize 32
#define Register79_RegisterResetValue 0x0
#define Register79_RegisterResetMask 0x0


/* Register Register80 */
/* txmulticastframes_gb */
#define Register80 (GMAC_BaseAddress + 0x140)
#define Register80_RegisterSize 32
#define Register80_RegisterResetValue 0x0
#define Register80_RegisterResetMask 0x0


/* Register Register81 */
/* txbroadcastframes_gb */
#define Register81 (GMAC_BaseAddress + 0x144)
#define Register81_RegisterSize 32
#define Register81_RegisterResetValue 0x0
#define Register81_RegisterResetMask 0x0


/* Register Register82 */
/* txunderflowerror */
#define Register82 (GMAC_BaseAddress + 0x148)
#define Register82_RegisterSize 32
#define Register82_RegisterResetValue 0x0
#define Register82_RegisterResetMask 0x0

/* Register Register83 */
/* txsingelcol_g */
#define Register83 (GMAC_BaseAddress + 0x14c)
#define Register83_RegisterSize 32
#define Register83_RegisterResetValue 0x0
#define Register83_RegisterResetMask 0x0

/* Register Register84 */
/* txmultilcol_g */
#define Register84 (GMAC_BaseAddress + 0x150)
#define Register84_RegisterSize 32
#define Register84_RegisterResetValue 0x0
#define Register84_RegisterResetMask 0x0

/* Register Register85 */
/* txdeferred */
#define Register85 (GMAC_BaseAddress + 0x154)
#define Register85_RegisterSize 32
#define Register85_RegisterResetValue 0x0
#define Register85_RegisterResetMask 0x0

/* Register Register86 */
/* txlatecol */
#define Register86 (GMAC_BaseAddress + 0x158)
#define Register86_RegisterSize 32
#define Register86_RegisterResetValue 0x0
#define Register86_RegisterResetMask 0x0

/* Register Register87 */
/* txexesscol */
#define Register87 (GMAC_BaseAddress + 0x15c)
#define Register87_RegisterSize 32
#define Register87_RegisterResetValue 0x0
#define Register87_RegisterResetMask 0x0

/* Register Register88 */
/* txcarriererror */
#define Register88 (GMAC_BaseAddress + 0x160)
#define Register88_RegisterSize 32
#define Register88_RegisterResetValue 0x0
#define Register88_RegisterResetMask 0x0

/* Register Register89 */
/* txoctetcount_g */
#define Register89 (GMAC_BaseAddress + 0x164)
#define Register89_RegisterSize 32
#define Register89_RegisterResetValue 0x0
#define Register89_RegisterResetMask 0x0

/* Register Register90 */
/* txframecount_g */
#define Register90 (GMAC_BaseAddress + 0x168)
#define Register90_RegisterSize 32
#define Register90_RegisterResetValue 0x0
#define Register90_RegisterResetMask 0x0

/* Register Register91 */
/* txexcessdef */
#define Register91 (GMAC_BaseAddress + 0x16c)
#define Register91_RegisterSize 32
#define Register91_RegisterResetValue 0x0
#define Register91_RegisterResetMask 0x0

/* Register Register92 */
/* txpauseframes */
#define Register92 (GMAC_BaseAddress + 0x170)
#define Register92_RegisterSize 32
#define Register92_RegisterResetValue 0x0
#define Register92_RegisterResetMask 0x0

/* Register Register93 */
/* txvlanframes_g */
#define Register93 (GMAC_BaseAddress + 0x174)
#define Register93_RegisterSize 32
#define Register93_RegisterResetValue 0x0
#define Register93_RegisterResetMask 0x0


/* Register Register96 */
/* rxframecount_gb */
#define Register96 (GMAC_BaseAddress + 0x180)
#define Register96_RegisterSize 32
#define Register96_RegisterResetValue 0x0
#define Register96_RegisterResetMask 0x0

/* Register Register97 */
/* rxoctetcount_gb */
#define Register97 (GMAC_BaseAddress + 0x184)
#define Register97_RegisterSize 32
#define Register97_RegisterResetValue 0x0
#define Register97_RegisterResetMask 0x0


/* Register Register98 */
/* rxoctetcount_g */
#define Register98 (GMAC_BaseAddress + 0x188)
#define Register98_RegisterSize 32
#define Register98_RegisterResetValue 0x0
#define Register98_RegisterResetMask 0x0


/* Register Register99 */
/* rxbroadcastframes_g */
#define Register99 (GMAC_BaseAddress + 0x18c)
#define Register99_RegisterSize 32
#define Register99_RegisterResetValue 0x0
#define Register99_RegisterResetMask 0x0


/* Register Register100 */
/* rxmulticastframes_g */
#define Register100 (GMAC_BaseAddress + 0x190)
#define Register100_RegisterSize 32
#define Register100_RegisterResetValue 0x0
#define Register100_RegisterResetMask 0x0


/* Register Register101 */
/* rxcrcerror */
#define Register101 (GMAC_BaseAddress + 0x194)
#define Register101_RegisterSize 32
#define Register101_RegisterResetValue 0x0
#define Register101_RegisterResetMask 0x0


/* Register Register102 */
/* rxalignmenterror */
#define Register102 (GMAC_BaseAddress + 0x198)
#define Register102_RegisterSize 32
#define Register102_RegisterResetValue 0x0
#define Register102_RegisterResetMask 0x0


/* Register Register103 */
/* rxrunterror */
#define Register103 (GMAC_BaseAddress + 0x19c)
#define Register103_RegisterSize 32
#define Register103_RegisterResetValue 0x0
#define Register103_RegisterResetMask 0x0


/* Register Register104 */
/* rxjabbererror */
#define Register104 (GMAC_BaseAddress + 0x1a0)
#define Register104_RegisterSize 32
#define Register104_RegisterResetValue 0x0
#define Register104_RegisterResetMask 0x0

/* End of Register Definition for Register104 */

/* Register Register105 */
/* rxundersize_g */
#define Register105 (GMAC_BaseAddress + 0x1a4)
#define Register105_RegisterSize 32
#define Register105_RegisterResetValue 0x0
#define Register105_RegisterResetMask 0x0


/* Register Register106 */
/* rxoversize_g */
#define Register106 (GMAC_BaseAddress + 0x1a8)
#define Register106_RegisterSize 32
#define Register106_RegisterResetValue 0x0
#define Register106_RegisterResetMask 0x0

/* End of Register Definition for Register106 */

/* Register Register107 */
/* rx64octets_gb */
#define Register107 (GMAC_BaseAddress + 0x1ac)
#define Register107_RegisterSize 32
#define Register107_RegisterResetValue 0x0
#define Register107_RegisterResetMask 0x0

/* End of Register Definition for Register107 */

/* Register Register108 */
/* rx65to127octets_gb */
#define Register108 (GMAC_BaseAddress + 0x1b0)
#define Register108_RegisterSize 32
#define Register108_RegisterResetValue 0x0
#define Register108_RegisterResetMask 0x0


/* Register Register109 */
/* rx128to255octets_gb */
#define Register109 (GMAC_BaseAddress + 0x1b4)
#define Register109_RegisterSize 32
#define Register109_RegisterResetValue 0x0
#define Register109_RegisterResetMask 0x0


/* Register Register110 */
/* rx256to511octets_gb */
#define Register110 (GMAC_BaseAddress + 0x1b8)
#define Register110_RegisterSize 32
#define Register110_RegisterResetValue 0x0
#define Register110_RegisterResetMask 0x0


/* Register Register111 */
/* rx512to1023octets_gb */
#define Register111 (GMAC_BaseAddress + 0x1bc)
#define Register111_RegisterSize 32
#define Register111_RegisterResetValue 0x0
#define Register111_RegisterResetMask 0x0


/* Register Register112 */
/* rx1024tomaxoctets_gb */
#define Register112 (GMAC_BaseAddress + 0x1c0)
#define Register112_RegisterSize 32
#define Register112_RegisterResetValue 0x0
#define Register112_RegisterResetMask 0x0


/* Register Register113 */
/* rxunicastframes_g */
#define Register113 (GMAC_BaseAddress + 0x1c4)
#define Register113_RegisterSize 32
#define Register113_RegisterResetValue 0x0
#define Register113_RegisterResetMask 0x0


/* Register Register114 */
/* rxlengtherror */
#define Register114 (GMAC_BaseAddress + 0x1c8)
#define Register114_RegisterSize 32
#define Register114_RegisterResetValue 0x0
#define Register114_RegisterResetMask 0x0


/* Register Register115 */
/* rxoutofrangetype */
#define Register115 (GMAC_BaseAddress + 0x1cc)
#define Register115_RegisterSize 32
#define Register115_RegisterResetValue 0x0
#define Register115_RegisterResetMask 0x0

/* Register Register116 */
/* rxpauseframes */
#define Register116 (GMAC_BaseAddress + 0x1d0)
#define Register116_RegisterSize 32
#define Register116_RegisterResetValue 0x0
#define Register116_RegisterResetMask 0x0

/* Register Register117 */
/* rxfifooverflow */
#define Register117 (GMAC_BaseAddress + 0x1d4)
#define Register117_RegisterSize 32
#define Register117_RegisterResetValue 0x0
#define Register117_RegisterResetMask 0x0


/* Register Register118 */
/* rxvlanframes_gb */
#define Register118 (GMAC_BaseAddress + 0x1d8)
#define Register118_RegisterSize 32
#define Register118_RegisterResetValue 0x0
#define Register118_RegisterResetMask 0x0


/* Register Register119 */
/* rxwatchdogerror */
#define Register119 (GMAC_BaseAddress + 0x1dc)
#define Register119_RegisterSize 32
#define Register119_RegisterResetValue 0x0
#define Register119_RegisterResetMask 0x0


#define DMA_BaseAddress (ETHERNET_CTRL_BASE + 0x1000)

/* Register Register0 */
/* Bus Mode Register */
#define D_Register0 (DMA_BaseAddress)
#define D_Register0_RegisterSize 32
#define D_Register0_RegisterResetValue 0x20101
#define D_Register0_RegisterResetMask 0x0


/* Register Register1 */
/* Transmit Poll Demand Register */
#define D_Register1 (DMA_BaseAddress + 0x4)
#define D_Register1_RegisterSize 32
#define D_Register1_RegisterResetValue 0x0
#define D_Register1_RegisterResetMask 0x0

/* Register Register2 */
/* Receive Poll Demand Register */
#define D_Register2 (DMA_BaseAddress + 0x8)
#define D_Register2_RegisterSize 32
#define D_Register2_RegisterResetValue 0x0
#define D_Register2_RegisterResetMask 0x0


/* Register Register3 */
/* Receive Descriptor List Address Register */
#define D_Register3 (DMA_BaseAddress + 0xc)
#define D_Register3_RegisterSize 32
#define D_Register3_RegisterResetValue 0x0
#define D_Register3_RegisterResetMask 0x0


/* Register Register4 */
/* Transmit Descriptor List Address Register */
#define D_Register4 (DMA_BaseAddress + 0x10)
#define D_Register4_RegisterSize 32
#define D_Register4_RegisterResetValue 0x0
#define D_Register4_RegisterResetMask 0x0


/* Register Register5 */
/* Status Register */
#define D_Register5 (DMA_BaseAddress + 0x14)
#define D_Register5_RegisterSize 32
#define D_Register5_RegisterResetValue 0x0
#define D_Register5_RegisterResetMask 0x0



/* Register Register6 */
/* Operation Mode Register */
#define D_Register6 (DMA_BaseAddress + 0x18)
#define D_Register6_RegisterSize 32
#define D_Register6_RegisterResetValue 0x0
#define D_Register6_RegisterResetMask 0x0


/* Register Register7 */
/* Interrupt enable Register */
#define D_Register7 (DMA_BaseAddress + 0x1c)
#define D_Register7_RegisterSize 32
#define D_Register7_RegisterResetValue 0x0
#define D_Register7_RegisterResetMask 0x0

/* D_Register Register8 */
/* Missed Frame and Buffer Oerflow Counter Register */
#define D_Register8 (DMA_BaseAddress + 0x20)
#define D_Register8_RegisterSize 32
#define D_Register8_RegisterResetValue 0x0
#define D_Register8_RegisterResetMask 0x0

/* Register Register18 */
/* Current Host Transmit Descriptor Register */
#define D_Register18 (DMA_BaseAddress + 0x48)
#define D_Register18_RegisterSize 32
#define D_Register18_RegisterResetValue 0x0
#define D_Register18_RegisterResetMask 0x0


/* Register Register19 */
/* Current Host Receive Descriptor Register */
#define D_Register19 (DMA_BaseAddress + 0x4c)
#define D_Register19_RegisterSize 32
#define D_Register19_RegisterResetValue 0x0
#define D_Register19_RegisterResetMask 0x0



/* Register Register20 */
/* Current Host Transmit Buffer Address Register */
#define D_Register20 (DMA_BaseAddress + 0x50)
#define D_Register20_RegisterSize 32
#define D_Register20_RegisterResetValue 0x0
#define D_Register20_RegisterResetMask 0x0


/* Register Register21 */
/* Current Host Receive Buffer Address Register */
#define D_Register21 (DMA_BaseAddress + 0x54)
#define D_Register21_RegisterSize 32
#define D_Register21_RegisterResetValue 0x0
#define D_Register21_RegisterResetMask 0x0

/* MDIO M2M adress*/

#define MDIO_control (SYS_APB_BASE+ 0x20000)
#define MDIO_status (SYS_APB_BASE+ 0x20004)
#define MDIO_ext_stat (SYS_APB_BASE+ 0x20008)
#define MDIO_PHY_id (SYS_APB_BASE+ 0x2000C)
#define MDIO_PHY_addr (SYS_APB_BASE+ 0x20010)
#define MDIO_it (SYS_APB_BASE+ 0x20014)
#define MDIO_mask_it (SYS_APB_BASE+ 0x20018)

#endif /* __ASM_ARCH_ETHERNET_CTRL_H */