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/*
 * include/asm-arm/arch-spc300/boot_arm_hard.h
 *
 * Copyright (C) 2009 SPiDCOM Technologies
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __ASM_ARCH_BOOT_ARM_HARD_H
#define __ASM_ARCH_BOOT_ARM_HARD_H

extern void(*adr_reset)(void);
extern void(*adr_undefined_instruction)(void);
extern void(*adr_software_interrupt)(void);
extern void(*adr_abort_prefetch)(void);
extern void(*adr_abort_data)(void);
extern void(*adr_irq)(void);
extern void(*adr_fiq)(void);
extern void(*adr_stack)(void);

extern int* test_status;


#define ARM_ENABLE_ICACHE  \
  asm(" \
    MRC p15,0,R0,c1,c0,0 \n\
    ORR R0,R0,#0x1000   \n\
    MCR p15,0,R0,c1,c0,0");

#define ARM_ENABLE_DCACHE  \
  asm(" \
    MRC p15,0,R0,c1,c0,0 \n\
    ORR R0,R0,#0x4   \n\
    MCR p15,0,R0,c1,c0,0");

#define ARM_ENABLE_IRQ  \
  asm(" \
    MRS  R0, CPSR   \n\
    BIC  R0, #0x80  \n\
    MSR  CPSR_c, R0");

#define ARM_DISABLE_IRQ  \
  asm(" \
    MRS  R0, CPSR   \n\
    ORR  R0, #0x80  \n\
    MSR  CPSR_c, R0");

#define ARM_ENABLE_FIQ  \
  asm(" \
    MRS  R0, CPSR   \n\
    BIC  R0, #0x40  \n\
    MSR  CPSR_c, R0");

#define ARM_DISABLE_FIQ  \
  asm(" \
    MRS  R0, CPSR   \n\
    ORR  R0, #0x40  \n\
    MSR  CPSR_c, R0");


//#define ARM_ENABLE_IRQ	asm("CPSIE i");

#define END_OF_INTERRUPT	asm("SUBS PC, R14, #4");

#define ARM_STANDBY	\
  asm("                     \n\
  start_arm_standby:        \n\
    MCR  p15,0,R0,c7,c0,4   \n\
  end_arm_standby:          \n\
  ");

#define TEST_OK			0xabcdef01

#define TEST_BAD		0x55555555

#define Write32( adr, data )	*((volatile int*)(adr))= data

#define Read32( adr )		(*(volatile int*)(adr))

#define Write8( adr, data )  *((volatile unsigned char *)(adr))= data
#define Read8( adr )        (*(volatile unsigned char *)(adr))

#define Write16( adr, data )  *((volatile short int *)(adr))= data
#define Read16( adr )        (*(volatile short int  *)(adr))

#define XSTR(x) STR(x)
#define STR(x) #x

#endif /* __ASM_ARCH_BOOT_ARM_HARD_H */