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Diffstat (limited to 'cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_gpio.h')
-rw-r--r--cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_gpio.h138
1 files changed, 0 insertions, 138 deletions
diff --git a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_gpio.h b/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_gpio.h
deleted file mode 100644
index 6270c3ae17..0000000000
--- a/cleopatre/u-boot-1.1.6/include/asm-arm/arch-spc300/arm_gpio.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * include/asm-arm/arch-spc300/arm_gpio.h
- *
- * Copyright (C) 2009 SPiDCOM Technologies
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_ARM_GPIO_H
-#define __ASM_ARCH_ARM_GPIO_H
-
-#ifndef ARM_GPIO_BASE
- #error "ARM_GPIO_BASE macro needs to be defined before including file arm_gpio.h"
-#endif
-
-#define GPIO_SWPORTA_DR_OFFSET 0x00
-#define GPIO_SWPORTA_DDR_OFFSET 0x04
-#define GPIO_SWPORTA_CTL_OFFSET 0x08
-#define GPIO_SWPORTB_DR_OFFSET 0x0C
-#define GPIO_SWPORTB_DDR_OFFSET 0x10
-#define GPIO_SWPORTB_CTL_OFFSET 0x14
-#define GPIO_SWPORTC_DR_OFFSET 0x18
-#define GPIO_SWPORTC_DDR_OFFSET 0x1C
-#define GPIO_SWPORTC_CTL_OFFSET 0x20
-#define GPIO_SWPORTD_DR_OFFSET 0x24
-#define GPIO_SWPORTD_DDR_OFFSET 0x28
-#define GPIO_SWPORTD_CTL_OFFSET 0x2C
-#define GPIO_INTEN_OFFSET 0x30
-#define GPIO_INTMASK_OFFSET 0x34
-#define GPIO_INTTYPE_LEVEL_OFFSET 0x38
-#define GPIO_INT_POLARITY_OFFSET 0x3C
-#define GPIO_INTSTATUS_OFFSET 0x40
-#define GPIO_RAW_INTSTATUS_OFFSET 0x44
-#define GPIO_DEBOUNCE_OFFSET 0x48
-#define GPIO_PORTA_EOI_OFFSET 0x4C
-#define GPIO_EXT_PORTA_OFFSET 0x50
-#define GPIO_EXT_PORTB_OFFSET 0x54
-#define GPIO_EXT_PORTC_OFFSET 0x58
-#define GPIO_EXT_PORTD_OFFSET 0x5C
-#define GPIO_LS_SYNC_OFFSET 0x60
-#define GPIO_ID_CODE_OFFSET 0x64
-#define GPIO_VER_ID_CODE_OFFSET 0x6C
-
-#define GPIO_CONFIGID_REG2_OFFSET 0x70
-
-#define GPIO_CONFIGID_REG1_OFFSET 0x74
-
-#define GPIO_SWPORTA_DR (ARM_GPIO_BASE + GPIO_SWPORTA_DR_OFFSET)
-#define GPIO_SWPORTA_DDR (ARM_GPIO_BASE + GPIO_SWPORTA_DDR_OFFSET)
-#define GPIO_SWPORTA_CTL (ARM_GPIO_BASE + GPIO_SWPORTA_CTL_OFFSET)
-#define GPIO_SWPORTB_DR (ARM_GPIO_BASE + GPIO_SWPORTB_DR_OFFSET)
-#define GPIO_SWPORTB_DDR (ARM_GPIO_BASE + GPIO_SWPORTB_DDR_OFFSET)
-#define GPIO_SWPORTB_CTL (ARM_GPIO_BASE + GPIO_SWPORTB_CTL_OFFSET)
-#define GPIO_SWPORTC_DR (ARM_GPIO_BASE + GPIO_SWPORTC_DR_OFFSET)
-#define GPIO_SWPORTC_DDR (ARM_GPIO_BASE + GPIO_SWPORTC_DDR_OFFSET)
-#define GPIO_SWPORTC_CTL (ARM_GPIO_BASE + GPIO_SWPORTC_CTL_OFFSET)
-#define GPIO_SWPORTD_DR (ARM_GPIO_BASE + GPIO_SWPORTD_DR_OFFSET)
-#define GPIO_SWPORTD_DDR (ARM_GPIO_BASE + GPIO_SWPORTD_DDR_OFFSET)
-#define GPIO_SWPORTD_CTL (ARM_GPIO_BASE + GPIO_SWPORTD_CTL_OFFSET)
-#define GPIO_INTEN (ARM_GPIO_BASE + GPIO_INTEN_OFFSET)
-#define GPIO_INTMASK (ARM_GPIO_BASE + GPIO_INTMASK_OFFSET)
-#define GPIO_INTTYPE_LEVEL (ARM_GPIO_BASE + GPIO_INTTYPE_LEVEL_OFFSET)
-#define GPIO_INT_POLARITY (ARM_GPIO_BASE + GPIO_INT_POLARITY_OFFSET)
-#define GPIO_INTSTATUS (ARM_GPIO_BASE + GPIO_INTSTATUS_OFFSET)
-#define GPIO_RAW_INTSTATUS (ARM_GPIO_BASE + GPIO_RAW_INTSTATUS_OFFSET)
-#define GPIO_DEBOUNCE (ARM_GPIO_BASE + GPIO_DEBOUNCE_OFFSET)
-#define GPIO_PORTA_EOI (ARM_GPIO_BASE + GPIO_PORTA_EOI_OFFSET)
-#define GPIO_EXT_PORTA (ARM_GPIO_BASE + GPIO_EXT_PORTA_OFFSET)
-#define GPIO_EXT_PORTB (ARM_GPIO_BASE + GPIO_EXT_PORTB_OFFSET)
-#define GPIO_EXT_PORTC (ARM_GPIO_BASE + GPIO_EXT_PORTC_OFFSET)
-#define GPIO_EXT_PORTD (ARM_GPIO_BASE + GPIO_EXT_PORTD_OFFSET)
-#define GPIO_LS_SYNC (ARM_GPIO_BASE + GPIO_LS_SYNC_OFFSET)
-#define GPIO_ID_CODE (ARM_GPIO_BASE + GPIO_ID_CODE_OFFSET)
-#define GPIO_VER_ID_CODE (ARM_GPIO_BASE + GPIO_VER_ID_CODE_OFFSET)
-
-#define GPIO_CONFIGID_REG2 (ARM_GPIO_BASE + GPIO_CONFIGID_REG2_OFFSET)
-
-#define GPIO_CONFIGID_REG1 (ARM_GPIO_BASE + GPIO_CONFIGID_REG1_OFFSET)
-
-#define GPIOPING_1BIT_WR (GPIO_SWPORTA_DR)
-
-#define CC_GPIO_ADD_ENCODED_PARAM 0x1
-#define CC_GPIO_APB_DATA_WIDTH 32
-#define CC_GPIO_NUM_PORTS 1
-#define CC_GPIO_ID 0
-#define CC_GPIO_DEBOUNCE 1
-#define CC_GPIO_ID_WIDTH 32
-#define CC_GPIO_ID_NUM 0x0
-#define CC_GPIO_REV_ID 0
-#define CC_GPIO_REV_ID_WIDTH 32
-#define CC_GPIO_REV_ID_NUM 0x0
-#define CC_GPIO_PWIDTH_A 16
-#define CC_GPIO_PORTA_SINGLE_CTL 1
-#define CC_GPIO_SWPORTA_RESET 0x0
-#define CC_GPIO_HW_PORTA 0
-#define CC_GPIO_DFLT_DIR_A 0
-#define CC_GPIO_DFLT_SRC_A 0
-#define CC_GPIO_PORTA_INTR 1
-#define CC_GPIO_INT_POL 1
-#define CC_GPIO_INTR_IO 1
-#define CC_GPIO_PA_SYNC_EXT_DATA 1
-#define CC_GPIO_PA_SYNC_INTERRUPTS 1
-#define CC_GPIO_PWIDTH_B 8
-#define CC_GPIO_PORTB_SINGLE_CTL 1
-#define CC_GPIO_SWPORTB_RESET 0x0
-#define CC_GPIO_HW_PORTB 0
-#define CC_GPIO_DFLT_DIR_B 0
-#define CC_GPIO_DFLT_SRC_B 0
-#define CC_GPIO_PB_SYNC_EXT_DATA 0
-#define CC_GPIO_PWIDTH_C 8
-#define CC_GPIO_PORTC_SINGLE_CTL 1
-#define CC_GPIO_SWPORTC_RESET 0x0
-#define CC_GPIO_HW_PORTC 0
-#define CC_GPIO_DFLT_DIR_C 0
-#define CC_GPIO_DFLT_SRC_C 0
-#define CC_GPIO_PC_SYNC_EXT_DATA 0
-#define CC_GPIO_PWIDTH_D 8
-#define CC_GPIO_PORTD_SINGLE_CTL 1
-#define CC_GPIO_SWPORTD_RESET 0x0
-#define CC_GPIO_HW_PORTD 0
-#define CC_GPIO_DFLT_DIR_D 0
-#define CC_GPIO_DFLT_SRC_D 0
-#define CC_GPIO_PD_SYNC_EXT_DATA 0
-
-#endif /* __ASM_ARCH_ARM_GPIO_H */