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/*
 * include/asm-arm/arch-spc300/sdram.h
 *
 * Copyright (C) 2009 SPiDCOM Technologies
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __ASM_ARCH_SDRAM_H
#define __ASM_ARCH_SDRAM_H

/* Register SCONR */
/* SDRAM configuration register */
#define SCONR 0x0
#define SCONR_RegisterSize 32
#define SCONR_RegisterResetValue 0xe5188
#define SCONR_RegisterResetMask 0x0

/* Register Field information for SCONR */

/* Register SCONR field s_bank_addr_width */
/* Number of bank address bits */
#define SCONR_s_bank_addr_width_BitAddressOffset 3
#define SCONR_s_bank_addr_width_RegisterSize 2
#define SCONR_s_bank_addr_width_RegisterMask (3<<SCONR_s_bank_addr_width_BitAddressOffset)

/* Register SCONR field s_row_addr_width */
/* Number of address bits for row address */
#define SCONR_s_row_addr_width_BitAddressOffset 5
#define SCONR_s_row_addr_width_RegisterSize 4
#define SCONR_s_row_addr_width_RegisterMask (0x0f<<SCONR_s_row_addr_width_BitAddressOffset)

/* Register SCONR field s_col_addr_width */
/* Number of address bits for column address */
#define SCONR_s_col_addr_width_BitAddressOffset 9
#define SCONR_s_col_addr_width_RegisterSize 4
#define SCONR_s_col_addr_width_RegisterMask (0x0f<<SCONR_s_col_addr_width_BitAddressOffset)

/* Register SCONR field s_data_width */
/* SDRAM data width */
#define SCONR_s_data_width_BitAddressOffset 13
#define SCONR_s_data_width_RegisterSize 2
#define SCONR_s_data_width_RegisterMask (3<<SCONR_s_data_width_BitAddressOffset)

/* Register SCONR field s_sa */
/* Serial presence detect address bits */
#define SCONR_s_sa_BitAddressOffset 15
#define SCONR_s_sa_RegisterSize 2

/* Register SCONR field s_scl */
/* Clock for serial presence detect logic */
#define SCONR_s_scl_BitAddressOffset 18
#define SCONR_s_scl_RegisterSize 1

/* Register SCONR field s_sd */
/* Bi-directional data for serial presence detect (SPD) logic */
#define SCONR_s_sd_BitAddressOffset 19
#define SCONR_s_sd_RegisterSize 1

/* Register SCONR field s_sda_oe_n */
/* Output enable for bi-directional data pin for I2C serial presence detect (SPD) logic */
#define SCONR_s_sda_oe_n_BitAddressOffset 20
#define SCONR_s_sda_oe_n_RegisterSize 1

/* End of Register Definition for SCONR */

/* Register STMG0R */
/* SDRAM timing register 0 */
#define STMG0R (0x0 + 0x4)
#define STMG0R_RegisterSize 32
#define STMG0R_RegisterResetValue 0x22e569a
#define STMG0R_RegisterResetMask 0x0

/* Register Field information for STMG0R */

/* Register STMG0R field cas_latency */
/* Delay in clock cycles between read command and availability of first data */
#define STMG0R_cas_latency_BitAddressOffset 0
#define STMG0R_cas_latency_RegisterSize 2

/* Register STMG0R field t_ras_min */
/* Minimum delay between active and precharge commands */
#define STMG0R_t_ras_min_BitAddressOffset 2
#define STMG0R_t_ras_min_RegisterSize 4

/* Register STMG0R field t_rcd */
/* Minimum delay between active and read/write commands */
#define STMG0R_t_rcd_BitAddressOffset 6
#define STMG0R_t_rcd_RegisterSize 3

/* Register STMG0R field t_rp */
/* Precharge period */
#define STMG0R_t_rp_BitAddressOffset 9
#define STMG0R_t_rp_RegisterSize 3

/* Register STMG0R field t_wr */
/* For writes, delay from last data in to next precharge command */
#define STMG0R_t_wr_BitAddressOffset 12
#define STMG0R_t_wr_RegisterSize 2

/* Register STMG0R field t_rcar */
/* Auto-refresh period; minimum time between two auto-refresh commands */
#define STMG0R_t_rcar_BitAddressOffset 14
#define STMG0R_t_rcar_RegisterSize 4

/* Register STMG0R field t_xsr */
/* Exit self-refresh to active or auto-refresh command time */
#define STMG0R_t_xsr_BitAddressOffset 18
#define STMG0R_t_xsr_RegisterSize 4

/* Register STMG0R field t_rc */
/* Active-to-active command period */
#define STMG0R_t_rc_BitAddressOffset 22
#define STMG0R_t_rc_RegisterSize 4

/* Register STMG0R field extended_cas_latency */
/* Bitfield extension for cas_latency (used for DDR) */
#define STMG0R_extended_cas_latency_BitAddressOffset 26
#define STMG0R_extended_cas_latency_RegisterSize 1

/* Register STMG0R field extended_t_xsr */
/* Bitfield extension for t_xsr */
#define STMG0R_extended_t_xsr_BitAddressOffset 27
#define STMG0R_extended_t_xsr_RegisterSize 5

/* End of Register Definition for STMG0R */

/* Register STMG1R */
/* SDRAM timing register 1 */
#define STMG1R (0x0 + 0x8)
#define STMG1R_RegisterSize 32
#define STMG1R_RegisterResetValue 0x70008
#define STMG1R_RegisterResetMask 0x0

/* Register Field information for STMG1R */

/* Register STMG1R field t_init */
/* Number of clock cycles to hold SDRAM inputs stable after power-up */
#define STMG1R_t_init_BitAddressOffset 0
#define STMG1R_t_init_RegisterSize 16

/* Register STMG1R field num_init_ref */
/* Number of auto-refreshes during initialization */
#define STMG1R_num_init_ref_BitAddressOffset 16
#define STMG1R_num_init_ref_RegisterSize 4

/* Register STMG1R field t_wtr */
/* Internal write-to-read delay for DDR-SDRAMs */
#define STMG1R_t_wtr_BitAddressOffset 20
#define STMG1R_t_wtr_RegisterSize 2

/* End of Register Definition for STMG1R */

/* Register SCTLR */
/* SDRAM control register */
#define SCTLR (0x0 + 0xc)
#define SCTLR_RegisterSize 32
#define SCTLR_RegisterResetValue 0x3089
#define SCTLR_RegisterResetMask 0x0

/* Register Field information for SCTLR */

/* Register SCTLR field initialize */
/* Forces initialization of SDRAM */
#define SCTLR_initialize_BitAddressOffset 0
#define SCTLR_initialize_RegisterSize 1

/* Register SCTLR field self_refresh */
/* Forces SDRAM into self-refresh mode */
#define SCTLR_self_refresh_BitAddressOffset 1
#define SCTLR_self_refresh_RegisterSize 1

/* Register SCTLR field power_down_mode */
/* Forces SDRAM into power-down mode */
#define SCTLR_power_down_mode_BitAddressOffset 2
#define SCTLR_power_down_mode_RegisterSize 1

/* Register SCTLR field precharge_algorithm */
/* Determines when row is precharged */
#define SCTLR_precharge_algorithm_BitAddressOffset 3
#define SCTLR_precharge_algorithm_RegisterSize 1

/* Register SCTLR field full_refresh_before_sr */
/* Controls number of refreshes done before putting SDRAM into self-refresh mode */
#define SCTLR_full_refresh_before_sr_BitAddressOffset 4
#define SCTLR_full_refresh_before_sr_RegisterSize 1

/* Register SCTLR field full_refresh_after_sr */
/* Controls number of refreshes done after SDRAM is taken out of self-refresh mode */
#define SCTLR_full_refresh_after_sr_BitAddressOffset 5
#define SCTLR_full_refresh_after_sr_RegisterSize 1

/* Register SCTLR field read_pipe */
/* Number of registers inserted in read data path for SDRAM in order to correctly latch data */
#define SCTLR_read_pipe_BitAddressOffset 6
#define SCTLR_read_pipe_RegisterSize 3

/* Register SCTLR field set_mode_reg */
/* Forces update of SDRAM mode register */
#define SCTLR_set_mode_reg_BitAddressOffset 9
#define SCTLR_set_mode_reg_RegisterSize 1

/* Register SCTLR field self_refresh_status */
/* Indicates SDRAM self-refresh mode status */
#define SCTLR_self_refresh_status_BitAddressOffset 11
#define SCTLR_self_refresh_status_RegisterSize 1

/* Register SCTLR field num_open_banks */
/* Number of SDRAM internal banks to be open at any time */
#define SCTLR_num_open_banks_BitAddressOffset 12
#define SCTLR_num_open_banks_RegisterSize 5

/* Register SCTLR field s_rd_ready_mode */
/* SDRAM read-data-ready mode */
#define SCTLR_s_rd_ready_mode_BitAddressOffset 17
#define SCTLR_s_rd_ready_mode_RegisterSize 1

/* Register SCTLR field exn_mode_reg_update */
/* Update Mobile-SDRAM extended-mode register */
#define SCTLR_exn_mode_reg_update_BitAddressOffset 18
#define SCTLR_exn_mode_reg_update_RegisterSize 1

/* Register SCTLR field mobile_sdram_dpd_en */
/* Mobile-SDRAM deep-power-down enable */
#define SCTLR_mobile_sdram_dpd_en_BitAddressOffset 19
#define SCTLR_mobile_sdram_dpd_en_RegisterSize 1

/* Register SCTLR field dpd_status */
/* Mobile-SDRAM deep-power-down mode status */
#define SCTLR_dpd_status_BitAddressOffset 20
#define SCTLR_dpd_status_RegisterSize 1

/* End of Register Definition for SCTLR */

/* Register SREFR */
/* SDRAM refresh register */
#define SREFR (0x0 + 0x10)
#define SREFR_RegisterSize 32
#define SREFR_RegisterResetValue 0x410
#define SREFR_RegisterResetMask 0x0

/* Register Field information for SREFR */

/* Register SREFR field t_ref */
/* Number of clock cycles between consecutive refresh cycles */
#define SREFR_t_ref_BitAddressOffset 0
#define SREFR_t_ref_RegisterSize 16

/* Register SREFR field gpo */
/* General purpose output signals */
#define SREFR_gpo_BitAddressOffset 16
#define SREFR_gpo_RegisterSize 8

/* Register SREFR field gpi */
/* General purpose input signals */
#define SREFR_gpi_BitAddressOffset 24
#define SREFR_gpi_RegisterSize 8

/* End of Register Definition for SREFR */

/* Register SCSLR0_LOW */
/* Chip select register 0 */
#define SCSLR0_LOW (0x0 + 0x14)
#define SCSLR0_LOW_RegisterSize 32
#define SCSLR0_LOW_RegisterResetValue 0x80000000
#define SCSLR0_LOW_RegisterResetMask 0x0

/* Register Field information for SCSLR0_LOW */

/* Register SCSLR0_LOW field addr */
/* Base address for chip select 0 */
#define SCSLR0_LOW_addr_BitAddressOffset 16
#define SCSLR0_LOW_addr_RegisterSize 16

/* End of Register Definition for SCSLR0_LOW */

/* Register SCSLR1_LOW */
/* Chip select register 1 */
#define SCSLR1_LOW (0x0 + 0x18)
#define SCSLR1_LOW_RegisterSize 32
#define SCSLR1_LOW_RegisterResetValue 0x10000000
#define SCSLR1_LOW_RegisterResetMask 0x0

/* Register Field information for SCSLR1_LOW */

/* Register SCSLR1_LOW field addr */
/* Base address for chip select 1 */
#define SCSLR1_LOW_addr_BitAddressOffset 16
#define SCSLR1_LOW_addr_RegisterSize 16

/* End of Register Definition for SCSLR1_LOW */

/* Register SCSLR2_LOW */
/* Chip select register 2 */
#define SCSLR2_LOW (0x0 + 0x1c)
#define SCSLR2_LOW_RegisterSize 32
#define SCSLR2_LOW_RegisterResetValue 0x20000000
#define SCSLR2_LOW_RegisterResetMask 0x0

/* Register Field information for SCSLR2_LOW */

/* Register SCSLR2_LOW field addr */
/* Base address for chip select 2 */
#define SCSLR2_LOW_addr_BitAddressOffset 16
#define SCSLR2_LOW_addr_RegisterSize 16

/* End of Register Definition for SCSLR2_LOW */

/* Register SCSLR3_LOW */
/* Chip select register 3 */
#define SCSLR3_LOW (0x0 + 0x20)
#define SCSLR3_LOW_RegisterSize 32
#define SCSLR3_LOW_RegisterResetValue 0x30000000
#define SCSLR3_LOW_RegisterResetMask 0x0

/* Register Field information for SCSLR3_LOW */

/* Register SCSLR3_LOW field addr */
/* Base address for chip select 3 */
#define SCSLR3_LOW_addr_BitAddressOffset 16
#define SCSLR3_LOW_addr_RegisterSize 16

/* End of Register Definition for SCSLR3_LOW */

/* Register SCSLR4_LOW */
/* Chip select register 4 */
#define SCSLR4_LOW (0x0 + 0x24)
#define SCSLR4_LOW_RegisterSize 32
#define SCSLR4_LOW_RegisterResetValue 0x40000000
#define SCSLR4_LOW_RegisterResetMask 0x0

/* Register Field information for SCSLR4_LOW */

/* Register SCSLR4_LOW field addr */
/* Base address for chip select 4 */
#define SCSLR4_LOW_addr_BitAddressOffset 16
#define SCSLR4_LOW_addr_RegisterSize 16

/* End of Register Definition for SCSLR4_LOW */

/* Register SCSLR5_LOW */
/* Chip select register 5 */
#define SCSLR5_LOW (0x0 + 0x28)
#define SCSLR5_LOW_RegisterSize 32
#define SCSLR5_LOW_RegisterResetValue 0x50000000
#define SCSLR5_LOW_RegisterResetMask 0x0

/* Register Field information for SCSLR5_LOW */

/* Register SCSLR5_LOW field addr */
/* Base address for chip select 5 */
#define SCSLR5_LOW_addr_BitAddressOffset 16
#define SCSLR5_LOW_addr_RegisterSize 16

/* End of Register Definition for SCSLR5_LOW */

/* Register SCSLR6_LOW */
/* Chip select register 6 */
#define SCSLR6_LOW (0x0 + 0x2c)
#define SCSLR6_LOW_RegisterSize 32
#define SCSLR6_LOW_RegisterResetValue 0x60000000
#define SCSLR6_LOW_RegisterResetMask 0x0

/* Register Field information for SCSLR6_LOW */

/* Register SCSLR6_LOW field addr */
/* Base address for chip select 6 */
#define SCSLR6_LOW_addr_BitAddressOffset 16
#define SCSLR6_LOW_addr_RegisterSize 16

/* End of Register Definition for SCSLR6_LOW */

/* Register SCSLR7_LOW */
/* Chip select register 7 */
#define SCSLR7_LOW (0x0 + 0x30)
#define SCSLR7_LOW_RegisterSize 32
#define SCSLR7_LOW_RegisterResetValue 0x70000000
#define SCSLR7_LOW_RegisterResetMask 0x0

/* Register Field information for SCSLR7_LOW */

/* Register SCSLR7_LOW field addr */
/* Base address for chip select 7 */
#define SCSLR7_LOW_addr_BitAddressOffset 16
#define SCSLR7_LOW_addr_RegisterSize 16

/* End of Register Definition for SCSLR7_LOW */

/* Register SMSKR0 */
/* Mask register 0 */
#define SMSKR0 (0x0 + 0x54)
#define SMSKR0_RegisterSize 32
#define SMSKR0_RegisterResetValue 0x20d
#define SMSKR0_RegisterResetMask 0x0

/* Register Field information for SMSKR0 */

/* Register SMSKR0 field mem_size */
/* Size of memory connected to chip select 0 */
#define SMSKR0_mem_size_BitAddressOffset 0
#define SMSKR0_mem_size_RegisterSize 5

/* Register SMSKR0 field mem_type */
/* Type of memory connected to chip select 0 */
#define SMSKR0_mem_type_BitAddressOffset 5
#define SMSKR0_mem_type_RegisterSize 3

/* Register SMSKR0 field reg_select */
/* Timing parameters to associate with chip select 0 */
#define SMSKR0_reg_select_BitAddressOffset 8
#define SMSKR0_reg_select_RegisterSize 3

/* End of Register Definition for SMSKR0 */

/* Register SMSKR1 */
/* Mask register 1 */
#define SMSKR1 (0x0 + 0x58)
#define SMSKR1_RegisterSize 32
#define SMSKR1_RegisterResetValue 0x207
#define SMSKR1_RegisterResetMask 0x0

/* Register Field information for SMSKR1 */

/* Register SMSKR1 field mem_size */
/* Size of memory connected to chip select 1 */
#define SMSKR1_mem_size_BitAddressOffset 0
#define SMSKR1_mem_size_RegisterSize 5

/* Register SMSKR1 field mem_type */
/* Type of memory connected to chip select 1 */
#define SMSKR1_mem_type_BitAddressOffset 5
#define SMSKR1_mem_type_RegisterSize 3

/* Register SMSKR1 field reg_select */
/* Timing parameters to associate with chip select 1 */
#define SMSKR1_reg_select_BitAddressOffset 8
#define SMSKR1_reg_select_RegisterSize 3

/* End of Register Definition for SMSKR1 */

/* Register SMSKR2 */
/* Mask register 2 */
#define SMSKR2 (0x0 + 0x5c)
#define SMSKR2_RegisterSize 32
#define SMSKR2_RegisterResetValue 0x21
#define SMSKR2_RegisterResetMask 0x0

/* Register Field information for SMSKR2 */

/* Register SMSKR2 field mem_size */
/* Size of memory connected to chip select 2 */
#define SMSKR2_mem_size_BitAddressOffset 0
#define SMSKR2_mem_size_RegisterSize 5

/* Register SMSKR2 field mem_type */
/* Type of memory connected to chip select 2 */
#define SMSKR2_mem_type_BitAddressOffset 5
#define SMSKR2_mem_type_RegisterSize 3

/* Register SMSKR2 field reg_select */
/* Timing parameters to associate with chip select 2 */
#define SMSKR2_reg_select_BitAddressOffset 8
#define SMSKR2_reg_select_RegisterSize 3

/* End of Register Definition for SMSKR2 */

/* Register SMSKR3 */
/* Mask register 3 */
#define SMSKR3 (0x0 + 0x60)
#define SMSKR3_RegisterSize 32
#define SMSKR3_RegisterResetValue 0x141
#define SMSKR3_RegisterResetMask 0x0

/* Register Field information for SMSKR3 */

/* Register SMSKR3 field mem_size */
/* Size of memory connected to chip select 3 */
#define SMSKR3_mem_size_BitAddressOffset 0
#define SMSKR3_mem_size_RegisterSize 5

/* Register SMSKR3 field mem_type */
/* Type of memory connected to chip select 3 */
#define SMSKR3_mem_type_BitAddressOffset 5
#define SMSKR3_mem_type_RegisterSize 3

/* Register SMSKR3 field reg_select */
/* Timing parameters to associate with chip select 3 */
#define SMSKR3_reg_select_BitAddressOffset 8
#define SMSKR3_reg_select_RegisterSize 3

/* End of Register Definition for SMSKR3 */

/* Register SMSKR4 */
/* Mask register 4 */
#define SMSKR4 (0x0 + 0x64)
#define SMSKR4_RegisterSize 32
#define SMSKR4_RegisterResetValue 0x261
#define SMSKR4_RegisterResetMask 0x0

/* Register Field information for SMSKR4 */

/* Register SMSKR4 field mem_size */
/* Size of memory connected to chip select 4 */
#define SMSKR4_mem_size_BitAddressOffset 0
#define SMSKR4_mem_size_RegisterSize 5

/* Register SMSKR4 field mem_type */
/* Type of memory connected to chip select 4 */
#define SMSKR4_mem_type_BitAddressOffset 5
#define SMSKR4_mem_type_RegisterSize 3

/* Register SMSKR4 field reg_select */
/* Timing parameters to associate with chip select 4 */
#define SMSKR4_reg_select_BitAddressOffset 8
#define SMSKR4_reg_select_RegisterSize 3

/* End of Register Definition for SMSKR4 */

/* Register SMSKR5 */
/* Mask register 5 */
#define SMSKR5 (0x0 + 0x68)
#define SMSKR5_RegisterSize 32
#define SMSKR5_RegisterResetValue 0x101
#define SMSKR5_RegisterResetMask 0x0

/* Register Field information for SMSKR5 */

/* Register SMSKR5 field mem_size */
/* Size of memory connected to chip select 5 */
#define SMSKR5_mem_size_BitAddressOffset 0
#define SMSKR5_mem_size_RegisterSize 5

/* Register SMSKR5 field mem_type */
/* Type of memory connected to chip select 5 */
#define SMSKR5_mem_type_BitAddressOffset 5
#define SMSKR5_mem_type_RegisterSize 3

/* Register SMSKR5 field reg_select */
/* Timing parameters to associate with chip select 5 */
#define SMSKR5_reg_select_BitAddressOffset 8
#define SMSKR5_reg_select_RegisterSize 3

/* End of Register Definition for SMSKR5 */

/* Register SMSKR6 */
/* Mask register 6 */
#define SMSKR6 (0x0 + 0x6c)
#define SMSKR6_RegisterSize 32
#define SMSKR6_RegisterResetValue 0x101
#define SMSKR6_RegisterResetMask 0x0

/* Register Field information for SMSKR6 */

/* Register SMSKR6 field mem_size */
/* Size of memory connected to chip select 6 */
#define SMSKR6_mem_size_BitAddressOffset 0
#define SMSKR6_mem_size_RegisterSize 5

/* Register SMSKR6 field mem_type */
/* Type of memory connected to chip select 6 */
#define SMSKR6_mem_type_BitAddressOffset 5
#define SMSKR6_mem_type_RegisterSize 3

/* Register SMSKR6 field reg_select */
/* Timing parameters to associate with chip select 6 */
#define SMSKR6_reg_select_BitAddressOffset 8
#define SMSKR6_reg_select_RegisterSize 3

/* End of Register Definition for SMSKR6 */

/* Register SMSKR7 */
/* Mask register 7 */
#define SMSKR7 (0x0 + 0x70)
#define SMSKR7_RegisterSize 32
#define SMSKR7_RegisterResetValue 0x101
#define SMSKR7_RegisterResetMask 0x0

/* Register Field information for SMSKR7 */

/* Register SMSKR7 field mem_size */
/* Size of memory connected to chip select 7 */
#define SMSKR7_mem_size_BitAddressOffset 0
#define SMSKR7_mem_size_RegisterSize 5

/* Register SMSKR7 field mem_type */
/* Type of memory connected to chip select 7 */
#define SMSKR7_mem_type_BitAddressOffset 5
#define SMSKR7_mem_type_RegisterSize 3

/* Register SMSKR7 field reg_select */
/* Timing parameters to associate with chip select 7 */
#define SMSKR7_reg_select_BitAddressOffset 8
#define SMSKR7_reg_select_RegisterSize 3

/* End of Register Definition for SMSKR7 */

/* Register CSALIAS0_LOW */
/* Alias register for chip select 0 */
#define CSALIAS0_LOW (0x0 + 0x74)
#define CSALIAS0_LOW_RegisterSize 32
#define CSALIAS0_LOW_RegisterResetValue 0x80000000
#define CSALIAS0_LOW_RegisterResetMask 0x0

/* Register Field information for CSALIAS0_LOW */

/* Register CSALIAS0_LOW field csalias0_low */
/* Lower aliasing register bits for chip select 0 */
#define CSALIAS0_LOW_csalias0_low_BitAddressOffset 16
#define CSALIAS0_LOW_csalias0_low_RegisterSize 16

/* End of Register Definition for CSALIAS0_LOW */

/* Register CSALIAS1_LOW */
/* Alias register for chip select 1 */
#define CSALIAS1_LOW (0x0 + 0x78)
#define CSALIAS1_LOW_RegisterSize 32
#define CSALIAS1_LOW_RegisterResetValue 0x18000000
#define CSALIAS1_LOW_RegisterResetMask 0x0

/* Register Field information for CSALIAS1_LOW */

/* Register CSALIAS1_LOW field csalias1_low */
/* Lower aliasing register bits for chip select 1 */
#define CSALIAS1_LOW_csalias1_low_BitAddressOffset 16
#define CSALIAS1_LOW_csalias1_low_RegisterSize 16

/* End of Register Definition for CSALIAS1_LOW */

/* Register CSREMAP0_LOW */
/* Remap register for chip select 0 */
#define CSREMAP0_LOW (0x0 + 0x84)
#define CSREMAP0_LOW_RegisterSize 32
#define CSREMAP0_LOW_RegisterResetValue 0x80000000
#define CSREMAP0_LOW_RegisterResetMask 0x0

/* Register Field information for CSREMAP0_LOW */

/* Register CSREMAP0_LOW field csremap0_low */
/* Lower remap register bits for chip select 0 */
#define CSREMAP0_LOW_csremap0_low_BitAddressOffset 16
#define CSREMAP0_LOW_csremap0_low_RegisterSize 16

/* End of Register Definition for CSREMAP0_LOW */

/* Register CSREMAP1_LOW */
/* Remap register for chip select 1 */
#define CSREMAP1_LOW (0x0 + 0x88)
#define CSREMAP1_LOW_RegisterSize 32
#define CSREMAP1_LOW_RegisterResetValue 0x12000000
#define CSREMAP1_LOW_RegisterResetMask 0x0

/* Register Field information for CSREMAP1_LOW */

/* Register CSREMAP1_LOW field csremap1_low */
/* Lower remap register bits for chip select 1 */
#define CSREMAP1_LOW_csremap1_low_BitAddressOffset 16
#define CSREMAP1_LOW_csremap1_low_RegisterSize 16

/* End of Register Definition for CSREMAP1_LOW */

/* Register SMTMGR_SET0 */
/* Static memory timing register set 0 */
#define SMTMGR_SET0 (0x0 + 0x94)
#define SMTMGR_SET0_RegisterSize 32
#define SMTMGR_SET0_RegisterResetValue 0x10441
#define SMTMGR_SET0_RegisterResetMask 0x0

/* Register Field information for SMTMGR_SET0 */

/* Register SMTMGR_SET0 field t_rc */
/* Read cycle time */
#define SMTMGR_SET0_t_rc_BitAddressOffset 0
#define SMTMGR_SET0_t_rc_RegisterSize 6

/* Register SMTMGR_SET0 field t_as */
/* Write address setup time */
#define SMTMGR_SET0_t_as_BitAddressOffset 6
#define SMTMGR_SET0_t_as_RegisterSize 2

/* Register SMTMGR_SET0 field t_wr */
/* Write address/data hold time */
#define SMTMGR_SET0_t_wr_BitAddressOffset 8
#define SMTMGR_SET0_t_wr_RegisterSize 2

/* Register SMTMGR_SET0 field t_wp */
/* Write pulse width */
#define SMTMGR_SET0_t_wp_BitAddressOffset 10
#define SMTMGR_SET0_t_wp_RegisterSize 6

/* Register SMTMGR_SET0 field t_bta */
/* Static memory idle cycles between "read to write", or "write to read", or "read to read when chip-select changes" for memory data bus turnaround time */
#define SMTMGR_SET0_t_bta_BitAddressOffset 16
#define SMTMGR_SET0_t_bta_RegisterSize 2

/* Register SMTMGR_SET0 field t_prc */
/* Page mode read cycle time */
#define SMTMGR_SET0_t_prc_BitAddressOffset 19
#define SMTMGR_SET0_t_prc_RegisterSize 4

/* Register SMTMGR_SET0 field page_mode */
/* Page mode support */
#define SMTMGR_SET0_page_mode_BitAddressOffset 23
#define SMTMGR_SET0_page_mode_RegisterSize 1

/* Register SMTMGR_SET0 field page_size */
/* Page size */
#define SMTMGR_SET0_page_size_BitAddressOffset 24
#define SMTMGR_SET0_page_size_RegisterSize 2

/* Register SMTMGR_SET0 field ready_mode */
/* Is memory a data-ready device? */
#define SMTMGR_SET0_ready_mode_BitAddressOffset 26
#define SMTMGR_SET0_ready_mode_RegisterSize 1

/* Register SMTMGR_SET0 field low_freq_sync_device */
/* Sample sm_clken before starting any static memory operation */
#define SMTMGR_SET0_low_freq_sync_device_BitAddressOffset 27
#define SMTMGR_SET0_low_freq_sync_device_RegisterSize 1

/* Register SMTMGR_SET0 field sm_read_pipe */
/* Number of registers inserted in the read data path */
#define SMTMGR_SET0_sm_read_pipe_BitAddressOffset 28
#define SMTMGR_SET0_sm_read_pipe_RegisterSize 2

/* End of Register Definition for SMTMGR_SET0 */

/* Register SMTMGR_SET1 */
/* Static memory timing register set 1 */
#define SMTMGR_SET1 (0x0 + 0x98)
#define SMTMGR_SET1_RegisterSize 32
#define SMTMGR_SET1_RegisterResetValue 0x7c4f5b
#define SMTMGR_SET1_RegisterResetMask 0x0

/* Register Field information for SMTMGR_SET1 */

/* Register SMTMGR_SET1 field t_rc */
/* Read cycle time */
#define SMTMGR_SET1_t_rc_BitAddressOffset 0
#define SMTMGR_SET1_t_rc_RegisterSize 6

/* Register SMTMGR_SET1 field t_as */
/* Write address setup time */
#define SMTMGR_SET1_t_as_BitAddressOffset 6
#define SMTMGR_SET1_t_as_RegisterSize 2

/* Register SMTMGR_SET1 field t_wr */
/* Write address/data hold time */
#define SMTMGR_SET1_t_wr_BitAddressOffset 8
#define SMTMGR_SET1_t_wr_RegisterSize 2

/* Register SMTMGR_SET1 field t_wp */
/* Write pulse width */
#define SMTMGR_SET1_t_wp_BitAddressOffset 10
#define SMTMGR_SET1_t_wp_RegisterSize 6

/* Register SMTMGR_SET1 field t_bta */
/* Static memory idle cycles between "read to write", or "write to read", or "read to read when chip-select changes" for memory data bus turnaround time */
#define SMTMGR_SET1_t_bta_BitAddressOffset 16
#define SMTMGR_SET1_t_bta_RegisterSize 2

/* Register SMTMGR_SET1 field t_prc */
/* Page mode read cycle time */
#define SMTMGR_SET1_t_prc_BitAddressOffset 19
#define SMTMGR_SET1_t_prc_RegisterSize 4

/* Register SMTMGR_SET1 field page_mode */
/* Page mode support */
#define SMTMGR_SET1_page_mode_BitAddressOffset 23
#define SMTMGR_SET1_page_mode_RegisterSize 1

/* Register SMTMGR_SET1 field page_size */
/* Page size */
#define SMTMGR_SET1_page_size_BitAddressOffset 24
#define SMTMGR_SET1_page_size_RegisterSize 2

/* Register SMTMGR_SET1 field ready_mode */
/* Is memory a data-ready device? */
#define SMTMGR_SET1_ready_mode_BitAddressOffset 26
#define SMTMGR_SET1_ready_mode_RegisterSize 1

/* Register SMTMGR_SET1 field low_freq_sync_device */
/* Sample sm_clken before starting any static memory operation */
#define SMTMGR_SET1_low_freq_sync_device_BitAddressOffset 27
#define SMTMGR_SET1_low_freq_sync_device_RegisterSize 1

/* Register SMTMGR_SET1 field sm_read_pipe */
/* Number of registers inserted in the read data path */
#define SMTMGR_SET1_sm_read_pipe_BitAddressOffset 28
#define SMTMGR_SET1_sm_read_pipe_RegisterSize 2

/* End of Register Definition for SMTMGR_SET1 */

/* Register SMTMGR_SET2 */
/* Static memory timing register set 2 */
#define SMTMGR_SET2 (0x0 + 0x9c)
#define SMTMGR_SET2_RegisterSize 32
#define SMTMGR_SET2_RegisterResetValue 0x1c4f5b
#define SMTMGR_SET2_RegisterResetMask 0x0

/* Register Field information for SMTMGR_SET2 */

/* Register SMTMGR_SET2 field t_rc */
/* Read cycle time */
#define SMTMGR_SET2_t_rc_BitAddressOffset 0
#define SMTMGR_SET2_t_rc_RegisterSize 6

/* Register SMTMGR_SET2 field t_as */
/* Write address setup time */
#define SMTMGR_SET2_t_as_BitAddressOffset 6
#define SMTMGR_SET2_t_as_RegisterSize 2

/* Register SMTMGR_SET2 field t_wr */
/* Write address/data hold time */
#define SMTMGR_SET2_t_wr_BitAddressOffset 8
#define SMTMGR_SET2_t_wr_RegisterSize 2

/* Register SMTMGR_SET2 field t_wp */
/* Write pulse width */
#define SMTMGR_SET2_t_wp_BitAddressOffset 10
#define SMTMGR_SET2_t_wp_RegisterSize 6

/* Register SMTMGR_SET2 field t_bta */
/* Static memory idle cycles between "read to write", or "write to read", or "read to read when chip-select changes" for memory data bus turnaround time */
#define SMTMGR_SET2_t_bta_BitAddressOffset 16
#define SMTMGR_SET2_t_bta_RegisterSize 2

/* Register SMTMGR_SET2 field t_prc */
/* Page mode read cycle time */
#define SMTMGR_SET2_t_prc_BitAddressOffset 19
#define SMTMGR_SET2_t_prc_RegisterSize 4

/* Register SMTMGR_SET2 field page_mode */
/* Page mode support */
#define SMTMGR_SET2_page_mode_BitAddressOffset 23
#define SMTMGR_SET2_page_mode_RegisterSize 1

/* Register SMTMGR_SET2 field page_size */
/* Page size */
#define SMTMGR_SET2_page_size_BitAddressOffset 24
#define SMTMGR_SET2_page_size_RegisterSize 2

/* Register SMTMGR_SET2 field ready_mode */
/* Is memory a data-ready device? */
#define SMTMGR_SET2_ready_mode_BitAddressOffset 26
#define SMTMGR_SET2_ready_mode_RegisterSize 1

/* Register SMTMGR_SET2 field low_freq_sync_device */
/* Sample sm_clken before starting any static memory operation */
#define SMTMGR_SET2_low_freq_sync_device_BitAddressOffset 27
#define SMTMGR_SET2_low_freq_sync_device_RegisterSize 1

/* Register SMTMGR_SET2 field sm_read_pipe */
/* Number of registers inserted in the read data path */
#define SMTMGR_SET2_sm_read_pipe_BitAddressOffset 28
#define SMTMGR_SET2_sm_read_pipe_RegisterSize 2

/* End of Register Definition for SMTMGR_SET2 */

/* Register FLASH_TRPDR */
/* FLASH memory tRPD timing register */
#define FLASH_TRPDR (0x0 + 0xa0)
#define FLASH_TRPDR_RegisterSize 32
#define FLASH_TRPDR_RegisterResetValue 0xc8
#define FLASH_TRPDR_RegisterResetMask 0x0

/* Register Field information for FLASH_TRPDR */

/* Register FLASH_TRPDR field t_rpd */
/* FLASH reset/power-down high to read/write delay */
#define FLASH_TRPDR_t_rpd_BitAddressOffset 0
#define FLASH_TRPDR_t_rpd_RegisterSize 12

/* End of Register Definition for FLASH_TRPDR */

/* Register SMCTLR */
/* Static memory control register */
#define SMCTLR (0x0 + 0xa4)
#define SMCTLR_RegisterSize 32
#define SMCTLR_RegisterResetValue 0x2481
#define SMCTLR_RegisterResetMask 0x0

/* Register Field information for SMCTLR */

/* Register SMCTLR field sm_rp_n */
/* FLASH reset/power-down mode */
#define SMCTLR_sm_rp_n_BitAddressOffset 0
#define SMCTLR_sm_rp_n_RegisterSize 1

/* Register SMCTLR field wp_n */
/* FLASH write-protection mode */
#define SMCTLR_wp_n_BitAddressOffset 1
#define SMCTLR_wp_n_RegisterSize 3

/* Register SMCTLR field sm_data_width_set0 */
/* Width of static meory data bus controlled by SMTMGR_SET0 */
#define SMCTLR_sm_data_width_set0_BitAddressOffset 7
#define SMCTLR_sm_data_width_set0_RegisterSize 3

/* Register SMCTLR field sm_data_width_set1 */
/* Width of static meory data bus controlled by SMTMGR_SET1 */
#define SMCTLR_sm_data_width_set1_BitAddressOffset 10
#define SMCTLR_sm_data_width_set1_RegisterSize 3

/* Register SMCTLR field sm_data_width_set2 */
/* Width of static meory data bus controlled by SMTMGR_SET2 */
#define SMCTLR_sm_data_width_set2_BitAddressOffset 13
#define SMCTLR_sm_data_width_set2_RegisterSize 3

/* End of Register Definition for SMCTLR */

/* Register EXN_MODE_REG */
/* DDR/Mobile-SDR, Mobile-DDR extension mode register */
#define EXN_MODE_REG (0x0 + 0xac)
#define EXN_MODE_REG_RegisterSize 32
#define EXN_MODE_REG_RegisterResetValue 0x0
#define EXN_MODE_REG_RegisterResetMask 0x0

/* End of Register Definition for EXN_MODE_REG */

#endif /* __ASM_ARCH_SDRAM_H */