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2013-02-05cleo/uboot/cpu/spc300: remove mode dependant PLL init, refs #3694Cyril Jourdan
Now that System PLL is set up in spidboot command, PLL init in msepll.S is only needed for uboot to work correctly. In this case, we can use the default value of 492 MHz.
2013-02-05cleo/uboot/cpu/spc300: remove DSP PLL init in msepll.S, refs #3694Cyril Jourdan
This is not needed anymore since it is done in spidboot command.
2013-01-25cleo/uboot/cpu/spc300: split serial setbrg, refs #1325Olivier Dufour
2013-01-25Revert "{cleo/uboot,common}: change system clock speed to 222 MHz", refs #1325Olivier Dufour
This reverts commit d2f7768afa5bbe4c4a40e9697a8939600a7e4a82.
2013-01-15cleo/uboot: configure ethernet MAC only if enabled in pkg_cfg, closes #3682Olivier Dufour
2012-12-10{cleo/uboot, common}: change system clock speed to 222 MHz, closes #3587Cyril Jourdan
In order to get ARM clock down to 444 MHz.
2012-11-06cleo/uboot/cpu/spc300: increase ICP and IBias current for PPLL, closes #3433Cyril Jourdan
2012-10-23cleo/uboot: use common watchdog API, closes #3296Jérémy Dufour
Changes introduced by commit 170f07194643 should have been reported to uboot too.
2012-09-20cleo/uboot/cpu/spc300: configure DSP PLL divider for 500 mode, closes #2961Jean-Philippe SAVE
2012-09-20common/inc/asm/arch/ips/hw: move DPLL regs to mseafe.h, refs #3318Jean-Philippe SAVE
2012-09-20cleo/uboot/cpu/spc300: make get_master_clock common, refs #2961Cyril Jourdan
2012-09-20cleo/uboot/cpu/spc300: handle MSE500 eth clocks config, refs #2961Cyril Jourdan
2012-09-20cleo/uboot/cpu/spc300: change SYNOP3504_FIXED_CLK feature, refs #2961Jean-Philippe SAVE
- change !SYNOP3504_FIXED_CLK feature into SPCETH - rename eth_init.S file into spceth.S
2012-09-20{cleo, common}: change eth prefix in NVRAM fields into eth1, refs #2961Cyril Jourdan
2012-09-20{cleo/uboot, common}: add IOMUX management, refs #2961Cyril Jourdan
2012-09-20cleo/uboot/cpu/spc300: move gpio_pio_init into a specific file, refs #2961Cyril Jourdan
2012-09-20cleo/u-boot/cpu/spc300: add timer clock for MSE500, refs #2961Jean-Philippe SAVE
- With a Xclk at 24MHz we cannot reach a timer_clk at 3,125MHz, so for MSE500 the timer_clk will be 4MHz.
2012-09-20cleo/u-boot/cpu/spc300: use CFG_HZ as timer clock define, refs #2961Jean-Philippe SAVE
2012-09-20common/tools/genNVRAM: add a MIU config for MSE500 simu model, refs #2961Cyril Jourdan
2012-09-20{common,cleo}: remove MIU_ATOP_REG_BASE, refs #2961Cyril Jourdan
As a consequence, MIU_REG_BASE is renamed into MIU_BASE.
2012-09-20cleo/uboot/cpu/spc300: add msepll.S, refs #2961Cyril Jourdan
2012-09-20cleo/uboot/cpu/spc300: rename pll_init.S into spcpll.S, refs #2961Cyril Jourdan
Change !CONFIG_CHIP_FEATURE_NO_PLL into CONFIG_CHIP_FEATURE_SPCPLL
2012-09-20cleo/uboot/cpu/spc300: move sdram init after PLL init, refs #2961Cyril Jourdan
In the case where you do not need to resync DSP and AFE clocks.
2012-09-20{cleo, common}: rename spc300_nvram into spidcom_nvram, refs #3119Cyril Jourdan
This is done to use common NVRAM structure and variable names with polux.
2012-09-20{cleo/u-boot, common}: use every file in common/include/asm/arch, refs #3119Cyril Jourdan
2012-09-20{cleo/u-boot, common}: use common/include/asm/arch/ips, refs #3119Cyril Jourdan
2012-06-19cleo/u-boot: enable spread spectrum, closes #2830Nélio Laranjeiro
Spread spectrum needs to be enable to reduces the peaks around the multiples of 75 MHz in CEM tests. See the documentation Spread_spectrum_SPC300_results.pdf by following the link in the ticket.
2012-05-09cleo/u-boot: adapt Ethernet driver to spc300dini, refs #2758MSE500 Team
2012-05-09cleo/u-boot: support spc300dini, refs #2758MSE500 Team
Support the SPC300c (MARIA2) prototype which is an FPGA based on DINI boards.
2012-05-09cleo/u-boot: add support for MIU controller, refs #2758MSE500 Team
2012-05-09cleo/u-boot: compute flash SPI speedNicolas Schodet
2012-05-09cleo/u-boot: switch to board/chip/feature configurationNicolas Schodet
2012-04-10cleopatre/u-boot: raise SPI speed to 18.375 MHz, closes #3067Nicolas Schodet
Speed computed for the maximum master clock, better setup will be done with mse500 commits.
2011-11-04cleo/u-boot: fix address of the data abort exception handlerYacine Belkadi
The problem was that the address of the handler for the data abort exception was not set correctly. As a consequence, on a data abort exception, the "not_used" handler was called instead of the "data_abort" handler.
2011-07-13cleo/u-boot: fix LEON start instructions in SDRAM, closes #2599Belkadi & Save
A side effect of the fix "clock synchronisation for PRP bug"(commit 13c535e), is that the LEON reset is released during boot. Despite of being configured to halt (debug mode), it actually fetches and executes a few instructions from a preconfigured location in SDRAM. The problem is that this preconfigured location is not initialized, so the LEON is executing random code that may corrupt the boot process (for example, lock the AHB Bus). The present commit initializes the prefconfigured location with NOP instructions. In order to do that, the SDRAM needs to be initialized sooner in the boot process. So the order is now: - SDRAM init - Clock synchro for PRP bug - PLL init
2011-07-13cleo/u-boot: move sdram controller config into its own fileBelkadi & Save
2011-04-12cleo/u-boot: clock synchronisation for PRP bug, second algorithm, closes #1774Jean-Philippe SAVE
This is the second algorithm implementation to correct PRP hardware bug. This algorithm is also to assert a DSP reset at a given and predictive clock cycle. But here we check all shift possibilities.
2011-04-12cleo/u-boot: clock synchronisation for PRP bug, first algorithm, refs #1774Jean-Philippe SAVE
This is the first algorithm implementation to correct PRP hardware bug. This algorithm is to assert a DSP reset at a given and predictive clock cycle. But it doesn't solve the bug in all cases.
2010-05-06cleo/u-boot: force PHY reset for 10ms after Eth clock enable, closes #1248save
git-svn-id: svn+ssh://pessac/svn/cesar/trunk@6982 017c9cb6-072f-447c-8318-d5b54f68fe89
2010-01-07cleo/u-boot: Corrected timer prescaler calculation, closes #1050save
Error in algorithm so prescaler was wrong for a xclk equal to 18.75. git-svn-id: svn+ssh://pessac/svn/cesar/trunk@6589 017c9cb6-072f-447c-8318-d5b54f68fe89
2009-10-29cleo/u-boot: use macro to access to nvram structure, refs #420save
Use macro to access to all nvram field In spite of using hardcoded offset. git-svn-id: svn+ssh://pessac/svn/cesar/trunk@6253 017c9cb6-072f-447c-8318-d5b54f68fe89
2009-10-28cleo/u-boot: implement watchdog, closes #592save
All watchdog standard functions are implemented but we use only restart one because it will be enabled just before uncompressing Linux kernel, so no refresh need to be called on u-boot. Refresh will be made by uncompressing kernel function. Watchdog timeout is fixed arbitrary to 2 seconds, Linux kernel will normally reprogram it this it own value. git-svn-id: svn+ssh://pessac/svn/cesar/trunk@6242 017c9cb6-072f-447c-8318-d5b54f68fe89
2009-10-12cleo/u-boot: add reset managementsave
git-svn-id: svn+ssh://pessac/svn/cesar/trunk@6071 017c9cb6-072f-447c-8318-d5b54f68fe89
2009-10-05cleo/u-boot, cleo/linux/drivers/eth: RMII 100M bug + Adapted Herve's patchsave
For RMII mode, after ETH PHY reset software choose 100M configuration as default one. Adapted Herve's patch: Now this patch is used only for GMII mode. git-svn-id: svn+ssh://pessac/svn/cesar/trunk@5914 017c9cb6-072f-447c-8318-d5b54f68fe89
2009-10-01[CLEO][U-BOOT] Fixed problem with inaccurate timer reading (reading in timer ↵draskovic
transition regions), saused by timer independent clock which is not synchronised with system clock. git-svn-id: svn+ssh://pessac/svn/cesar/trunk@5855 017c9cb6-072f-447c-8318-d5b54f68fe89
2009-09-29[CLEO][U-BOOT]Implement GMII/RMII/MII hot-plug modesave
git-svn-id: svn+ssh://pessac/svn/cesar/trunk@5809 017c9cb6-072f-447c-8318-d5b54f68fe89
2009-09-22[CLEO]Test Malika board at 147MHzsave
- Changed AHB_CLOCK under linux-kernel - Changed under u-boot : - serial baudrate generation : clock = 147 and not 150 - SPI frequency during start : spll_clock / 12 git-svn-id: svn+ssh://pessac/svn/cesar/trunk@5670 017c9cb6-072f-447c-8318-d5b54f68fe89
2009-09-18[CLEO][SPK300G][U-BOOT] Added functions for invalidating I and D caches ↵draskovic
individualy git-svn-id: svn+ssh://pessac/svn/cesar/trunk@5613 017c9cb6-072f-447c-8318-d5b54f68fe89
2009-09-09[CLEO][U-BOOT]Correction GPIO configsave
- corrected GPIO configuration error with offset calculation - updated NVRAM to set first 8 GPIO as PLC GPIOS and PLC UART git-svn-id: svn+ssh://pessac/svn/cesar/trunk@5477 017c9cb6-072f-447c-8318-d5b54f68fe89
2009-09-01[CLEO][U-BOOT] Changed Timer prescaler for spk300gsave
Timer depends on xclk but have a programmable prescaler U-boot manage prescaler to always have a timer clock eqaul to 3.125MHz git-svn-id: svn+ssh://pessac/svn/cesar/trunk@5387 017c9cb6-072f-447c-8318-d5b54f68fe89