summaryrefslogtreecommitdiff
path: root/cleopatre/u-boot-1.1.6/cpu
diff options
context:
space:
mode:
authorOlivier Dufour2012-12-24 11:30:00 +0100
committerOlivier Dufour2013-01-25 13:40:54 +0100
commitcd2ec2fa3ae541d7c6f60de1d22dd16b2e9d6392 (patch)
treeea0cead76c81c58eb75e4d7ec655a0dabf86d447 /cleopatre/u-boot-1.1.6/cpu
parent819365f32adee29f146e13387f17b686fd3f9150 (diff)
Revert "{cleo/uboot,common}: change system clock speed to 222 MHz", refs #1325
This reverts commit d2f7768afa5bbe4c4a40e9697a8939600a7e4a82.
Diffstat (limited to 'cleopatre/u-boot-1.1.6/cpu')
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/masterclk.c2
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S4
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/nvram_dyn_cfg.S8
3 files changed, 7 insertions, 7 deletions
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/masterclk.c b/cleopatre/u-boot-1.1.6/cpu/spc300/masterclk.c
index 4fdcff3933..1e843acc7e 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/masterclk.c
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/masterclk.c
@@ -51,7 +51,7 @@ ulong get_master_clock(void)
case NVRAM_MSE500_MODE_300:
case NVRAM_MSE500_MODE_500:
default:
- masterclk = 222000000;
+ masterclk = 246000000;
break;
}
#else
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S b/cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S
index 92f7a37e49..63d02dd9ba 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S
@@ -160,7 +160,7 @@ pll_init:
ldr r1, =MSEPLL_SPLL_BASE
regbitset r1, MSEPLL_SPPLL_CTRL_OFFSET, MSEPLL_SPPLL_CTRL_VCO_DIV2_DIS_SHIFT, \
MSEPLL_SPPLL_CTRL_VCO_DIV2_DIS_MASK, r2, r3
- /* Config to have an ouptut clock at 444 MHz */
+ /* Config to have an ouptut clock at 492 MHz */
mov r2, #0
mov r3, #MSEPLL_SPLL_CONF_INPUT_DIV_FIRST_4
add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_INPUT_DIV_FIRST_SHIFT
@@ -169,7 +169,7 @@ pll_init:
add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_OUTPUT_DIV_FIRST_SHIFT
mov r3, #MSEPLL_SPLL_CONF_LOOP_DIV_FIRST_2
add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_LOOP_DIV_FIRST_SHIFT
- mov r3, #37
+ mov r3, #41
add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_LOOP_DIV_SECOND_SHIFT
str r2, [r1, #MSEPLL_SPPLL_CONF_OFFSET]
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/nvram_dyn_cfg.S b/cleopatre/u-boot-1.1.6/cpu/spc300/nvram_dyn_cfg.S
index be05fe50dd..334505387c 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/nvram_dyn_cfg.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/nvram_dyn_cfg.S
@@ -82,13 +82,13 @@
/* Wait for a certain amount of time.
* We have to convert value in us to clock cycles with the following
* formula: (((time_to_wait * cpu_clk) / 1000000) / cpu_cycles_nb).
- * We make the calculus using a cpuclk of 444 MHz (max speed used). If
+ * We make the calculus using a cpuclk of 492 MHz (max speed used). If
* the actual speed is lower, wait will be longer but we consider that it
* is not a problem.
* The 3 instructions take 5 CPU cycles.
- * With cpu_clk = 444 MHz and cpu_cycles_nb = 5, we have to multiply the
- * initial value by (444000000 / 1000000) / 5 = 88.8, rounded to 89 */
- mov \tmp3, #89
+ * With cpu_clk = 492 MHz and cpu_cycles_nb = 5, we have to multiply the
+ * initial value by (492000000 / 1000000) / 5 = 98.4, rounded to 99 */
+ mov \tmp3, #99
mul \tmp3, \tmp4, \tmp3
1:
sub \tmp3, \tmp3, #1