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authorJean-Philippe SAVE2012-09-06 07:50:53 +0200
committerCyril Jourdan2012-09-20 17:00:20 +0200
commita7e0ca72f80dfb88db5bb081c5a04f027c164207 (patch)
tree1d157ded777207d191af85ed3dc1a6600e407129 /cleopatre/u-boot-1.1.6/cpu
parent01fb7f753c5defc1cc9268d97e818068013d6df6 (diff)
cleo/uboot/cpu/spc300: configure DSP PLL divider for 500 mode, closes #2961
Diffstat (limited to 'cleopatre/u-boot-1.1.6/cpu')
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S7
1 files changed, 7 insertions, 0 deletions
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S b/cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S
index 7b1575d894..be9f372051 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S
@@ -191,6 +191,13 @@ pll_init:
MSEAFE_DPLL_CONF_DAC_DIV_2, r3
bitinsert r2, MSEAFE_DPLL_CONF_ICP_MASK, MSEAFE_DPLL_CONF_ICP_SHIFT, 2, r3
str r2, [r1, #MSEAFE_DPLL_CONF_OFFSET]
+
+ /* Set DSP PLL divider only for mode 500. */
+ cmp r0, #NVRAM_MSE500_MODE_500
+ bne .Lendconf
+ ldr r1, =MARIA_REGBANK_BASE
+ mov r2, #CLK_DIV_DSP_1
+ str r2, [r1, #RB_CLK_DIV_DSP_OFFSET]
b .Lendconf
200: