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authorCyril Jourdan2013-01-29 11:07:29 +0100
committerCyril Jourdan2013-02-05 15:57:26 +0100
commit9a771e7e55a47620bd371c5741ef20980b713d19 (patch)
tree35d8a0952a80c4b1ee1c8e034d4b7a2636a0bba0 /cleopatre/u-boot-1.1.6/cpu
parentcfeadd2d973639a0e467c9d27bbd797231e2eafa (diff)
cleo/uboot/cpu/spc300: remove DSP PLL init in msepll.S, refs #3694
This is not needed anymore since it is done in spidboot command.
Diffstat (limited to 'cleopatre/u-boot-1.1.6/cpu')
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S92
1 files changed, 0 insertions, 92 deletions
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S b/cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S
index 63d02dd9ba..7e0e79ab67 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S
@@ -55,15 +55,6 @@
str \tmp1, [\base, #\offset]
.endm
- /* This macro is used to insert bits in an ARM register. */
- .macro bitinsert baseval, mask, shift, value, tmp
- mov \tmp, #\mask
- mov \tmp, \tmp, lsl #\shift
- bic \baseval, \baseval, \tmp
- mov \tmp, #\value
- add \baseval, \baseval, \tmp, lsl #\shift
- .endm
-
.macro waitstatus, base, offset, statval, tmp
1:
ldr \tmp, [\base, #\offset]
@@ -101,9 +92,6 @@ pll_init:
/* Peripheral PLL */
str r2, [r1, #RB_PPLL_BYPASS_OFFSET]
waitstatus r1, RB_PPLL_BYPASS_STAT_OFFSET, PLL_IS_BYPASS, r2
- /* DSP PLL */
- str r2, [r1, #RB_DPLL_BYPASS_OFFSET]
- waitstatus r1, RB_DPLL_BYPASS_STAT_OFFSET, PLL_IS_BYPASS, r2
/*
* Switch OFF PLLs (before doing configuration).
@@ -116,18 +104,6 @@ pll_init:
ldr r1, =MSEPLL_PPLL_BASE
regbitset r1, MSEPLL_SPPLL_CTRL_OFFSET, MSEPLL_SPPLL_CTRL_PD_SHIFT, \
MSEPLL_SPPLL_CTRL_PD_MASK, r2, r3
- /* DSP PLL */
- ldr r1, =MSEAFE_BASE
- regbitset r1, MSEAFE_DPLL_CONF_OFFSET, MSEAFE_DPLL_CONF_PD_SHIFT, \
- MSEAFE_DPLL_CONF_PD_MASK, r2, r3
- regbitset r1, MSEAFE_DPLL_CTRL_OFFSET, MSEAFE_DPLL_CTRL_PD_CLK_SHIFT, \
- MSEAFE_DPLL_CTRL_PD_CLK_MASK, r2, r3
- regbitset r1, MSEAFE_DPLL_CTRL_OFFSET, MSEAFE_DPLL_CTRL_PD_DAC_CLK_OUT_SHIFT, \
- MSEAFE_DPLL_CTRL_PD_DAC_CLK_OUT_MASK, r2, r3
- regbitset r1, MSEAFE_DPLL_CTRL_OFFSET, MSEAFE_DPLL_CTRL_PD_DAC_CLK_SHIFT, \
- MSEAFE_DPLL_CTRL_PD_DAC_CLK_MASK, r2, r3
- regbitset r1, MSEAFE_DPLL_CTRL_OFFSET, MSEAFE_DPLL_CTRL_PD_ADC_CLK_SHIFT, \
- MSEAFE_DPLL_CTRL_PD_ADC_CLK_MASK, r2, r3
/*
* Configure PLLs (while switched off).
@@ -173,35 +149,6 @@ pll_init:
add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_LOOP_DIV_SECOND_SHIFT
str r2, [r1, #MSEPLL_SPPLL_CONF_OFFSET]
- /* DSP PLL */
- ldr r1, =MSEAFE_BASE
- /* Config to have an ouptut clock at 300 MHz */
- ldr r2, [r1, #MSEAFE_DPLL_CTRL_OFFSET]
- bitinsert r2, MSEAFE_DPLL_CTRL_REF_DIV_MASK, MSEAFE_DPLL_CTRL_REF_DIV_SHIFT, \
- MSEAFE_DPLL_CTRL_REF_DIV_2, r3
- bitinsert r2, MSEAFE_DPLL_CTRL_ADC_DIV_MASK, MSEAFE_DPLL_CTRL_ADC_DIV_SHIFT, \
- MSEAFE_DPLL_CTRL_ADC_DIV_4, r3
- str r2, [r1, #MSEAFE_DPLL_CTRL_OFFSET]
- mov r2, #0
- mov r3, #MSEAFE_DPLL_LOOP_DIV_FIRST_2
- add r2, r2, r3, lsl #MSEAFE_DPLL_LOOP_DIV_FIRST_SHIFT
- mov r3, #25
- add r2, r2, r3, lsl #MSEAFE_DPLL_LOOP_DIV_SECOND_SHIFT
- str r2, [r1, #MSEAFE_DPLL_LOOP_DIV_OFFSET]
- ldr r2, [r1, #MSEAFE_DPLL_CONF_OFFSET]
- bitinsert r2, MSEAFE_DPLL_CONF_DSP_DIV_MASK, MSEAFE_DPLL_CONF_DSP_DIV_SHIFT, \
- MSEAFE_DPLL_CONF_DSP_DIV_2, r3
- bitinsert r2, MSEAFE_DPLL_CONF_DAC_DIV_MASK, MSEAFE_DPLL_CONF_DAC_DIV_SHIFT, \
- MSEAFE_DPLL_CONF_DAC_DIV_2, r3
- bitinsert r2, MSEAFE_DPLL_CONF_ICP_MASK, MSEAFE_DPLL_CONF_ICP_SHIFT, 2, r3
- str r2, [r1, #MSEAFE_DPLL_CONF_OFFSET]
-
- /* Set DSP PLL divider only for mode 500. */
- cmp r0, #NVRAM_MSE500_MODE_500
- bne .Lendconf
- ldr r1, =MARIA_REGBANK_BASE
- mov r2, #CLK_DIV_DSP_1
- str r2, [r1, #RB_CLK_DIV_DSP_OFFSET]
b .Lendconf
200:
@@ -223,29 +170,6 @@ pll_init:
add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_LOOP_DIV_SECOND_SHIFT
str r2, [r1, #MSEPLL_SPPLL_CONF_OFFSET]
- /* DSP PLL */
- ldr r1, =MSEAFE_BASE
- /* Config to have an ouptut clock at 256 MHz */
- ldr r2, [r1, #MSEAFE_DPLL_CTRL_OFFSET]
- bitinsert r2, MSEAFE_DPLL_CTRL_REF_DIV_MASK, MSEAFE_DPLL_CTRL_REF_DIV_SHIFT, \
- MSEAFE_DPLL_CTRL_REF_DIV_2, r3
- bitinsert r2, MSEAFE_DPLL_CTRL_ADC_DIV_MASK, MSEAFE_DPLL_CTRL_ADC_DIV_SHIFT, \
- MSEAFE_DPLL_CTRL_ADC_DIV_6, r3
- str r2, [r1, #MSEAFE_DPLL_CTRL_OFFSET]
- mov r2, #0
- mov r3, #MSEAFE_DPLL_LOOP_DIV_FIRST_2
- add r2, r2, r3, lsl #MSEAFE_DPLL_LOOP_DIV_FIRST_SHIFT
- mov r3, #32
- add r2, r2, r3, lsl #MSEAFE_DPLL_LOOP_DIV_SECOND_SHIFT
- str r2, [r1, #MSEAFE_DPLL_LOOP_DIV_OFFSET]
- ldr r2, [r1, #MSEAFE_DPLL_CONF_OFFSET]
- bitinsert r2, MSEAFE_DPLL_CONF_DSP_DIV_MASK, MSEAFE_DPLL_CONF_DSP_DIV_SHIFT, \
- MSEAFE_DPLL_CONF_DSP_DIV_3, r3
- bitinsert r2, MSEAFE_DPLL_CONF_DAC_DIV_MASK, MSEAFE_DPLL_CONF_DAC_DIV_SHIFT, \
- MSEAFE_DPLL_CONF_DAC_DIV_3, r3
- bitinsert r2, MSEAFE_DPLL_CONF_ICP_MASK, MSEAFE_DPLL_CONF_ICP_SHIFT, 3, r3
- str r2, [r1, #MSEAFE_DPLL_CONF_OFFSET]
-
.Lendconf:
/*
* Switch ON PLLs and wait 200uS (or more)
@@ -259,18 +183,6 @@ pll_init:
ldr r1, =MSEPLL_PPLL_BASE
regbitclear r1, MSEPLL_SPPLL_CTRL_OFFSET, MSEPLL_SPPLL_CTRL_PD_SHIFT, \
MSEPLL_SPPLL_CTRL_PD_MASK, r2, r3
- /* DSP PLL */
- ldr r1, =MSEAFE_BASE
- regbitclear r1, MSEAFE_DPLL_CTRL_OFFSET, MSEAFE_DPLL_CTRL_PD_ADC_CLK_SHIFT, \
- MSEAFE_DPLL_CTRL_PD_ADC_CLK_MASK, r2, r3
- regbitclear r1, MSEAFE_DPLL_CTRL_OFFSET, MSEAFE_DPLL_CTRL_PD_DAC_CLK_SHIFT, \
- MSEAFE_DPLL_CTRL_PD_DAC_CLK_MASK, r2, r3
- regbitclear r1, MSEAFE_DPLL_CTRL_OFFSET, MSEAFE_DPLL_CTRL_PD_DAC_CLK_OUT_SHIFT, \
- MSEAFE_DPLL_CTRL_PD_DAC_CLK_OUT_MASK, r2, r3
- regbitclear r1, MSEAFE_DPLL_CTRL_OFFSET, MSEAFE_DPLL_CTRL_PD_CLK_SHIFT, \
- MSEAFE_DPLL_CTRL_PD_CLK_MASK, r2, r3
- regbitclear r1, MSEAFE_DPLL_CONF_OFFSET, MSEAFE_DPLL_CONF_PD_SHIFT, \
- MSEAFE_DPLL_CONF_PD_MASK, r2, r3
/* active wait */
ldr r2, =PLL_WAIT_TIME
@@ -293,10 +205,6 @@ pll_init:
str r2, [r1, #RB_PPLL_BYPASS_OFFSET]
waitstatus r1, RB_PPLL_BYPASS_STAT_OFFSET, PLL_IS_PLL, r2
- /* DSP PLL */
- str r2, [r1, #RB_DPLL_BYPASS_OFFSET]
- waitstatus r1, RB_DPLL_BYPASS_STAT_OFFSET, PLL_IS_PLL, r2
-
/* back to my caller */
mov pc, lr