summaryrefslogtreecommitdiff
path: root/cleopatre/u-boot-1.1.6/cpu
diff options
context:
space:
mode:
authorJean-Philippe SAVE2011-03-31 11:48:11 +0200
committerJean-Philippe SAVE2011-04-12 18:15:00 +0200
commitd140e972edd62024daf5402c593affb923bcc78d (patch)
treead71caedec12355e9fb3f14a136f11231f352a19 /cleopatre/u-boot-1.1.6/cpu
parente242077273756001706c9c186c1f3713cd9f8e99 (diff)
cleo/u-boot: clock synchronisation for PRP bug, first algorithm, refs #1774
This is the first algorithm implementation to correct PRP hardware bug. This algorithm is to assert a DSP reset at a given and predictive clock cycle. But it doesn't solve the bug in all cases.
Diffstat (limited to 'cleopatre/u-boot-1.1.6/cpu')
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/Makefile2
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/dsp.S145
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/start.S7
3 files changed, 153 insertions, 1 deletions
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile b/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile
index 4056f174e3..cb4bf1243c 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile
@@ -23,7 +23,7 @@ LIB = lib$(CPU).a
START = start.o
OBJS = interrupts.o cpu.o timer.o serial.o wdt.o
-SOBJS = reset.o pll_init.o eth_init.o nvram.o
+SOBJS = reset.o pll_init.o eth_init.o nvram.o dsp.o
all: .depend $(START) $(LIB)
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/dsp.S b/cleopatre/u-boot-1.1.6/cpu/spc300/dsp.S
new file mode 100644
index 0000000000..936d3c8931
--- /dev/null
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/dsp.S
@@ -0,0 +1,145 @@
+/*
+ * cpu/spc300/dsp.S
+ *
+ * Copyright (C) 2010 SPiDCOM Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/hardware.h>
+
+ .file "dsp.S"
+
+ .text
+ .arm @ This is ARM code; performs the same action as .code 32
+ .align 2 @ Align to word boundary; "2" means the number of bits that must be zero
+ .globl dsp_init
+ .type dsp_init, %function
+
+
+/* WARNING : Assume that for macros r0=REGBANK_BASE and r1 is not used */
+ .macro cmdoff, offset
+ ldr r1, =CLK_CMD_OFF
+ str r1, [r0, #\offset]
+ .endm
+
+ .macro cmdon, offset
+ ldr r1, =CLK_CMD_ON
+ str r1, [r0, #\offset]
+ .endm
+
+ .macro setreg, offset, val
+ ldr r1, =\val
+ str r1, [r0, #\offset]
+ .endm
+
+ .macro checkreg, offset, val
+1: ldr r1, [r0, #\offset]
+ cmp r1, #\val
+ bne 1b
+ .endm
+
+ .macro setbit, regoffset, bitpos
+ ldr r1, [r0, #\regoffset]
+ orr r1, r1, #\bitpos
+ str r1, [r0, #\regoffset]
+ .endm
+
+ .macro clrbit, regoffset, bitpos
+ ldr r1, [r0, #\regoffset]
+ bic r1, r1, #\bitpos
+ str r1, [r0, #\regoffset]
+ .endm
+
+dsp_init:
+ ldr r0, =REGBANK_BASE
+
+ /* Assert DSP reset, Normally already done */
+ setbit RB_RST_GROUP, RST_DSP
+
+ /* Disable DSP clock, Normally already done */
+ cmdoff RB_CLK_CMD_DSP
+ checkreg RB_CLK_STAT_DSP, CLK_IS_OFF
+
+ /* Disable AFE clock, Normally already done */
+ cmdoff RB_CLK_CMD_AFE
+ checkreg RB_CLK_STAT_AFE, CLK_IS_OFF
+
+ /* Enable AFE clock */
+ cmdon RB_CLK_CMD_AFE
+ checkreg RB_CLK_STAT_AFE, CLK_IS_ON
+
+ /* De-Assert DSP reset */
+ setreg RB_RST_GROUP, RST_LEONSS
+
+
+ /*
+ * Synchronise DSP Clock and Reset for PRS patch.
+ * Each cycle is important so forget macro using.
+ */
+ /* We need to run this code twice because each instruction need to be
+ * executed in cache so the first excecution is for cache filling */
+ mov r4, #2
+ /* We prepare RST_GROUP values when DSP is asserted and de-asserted */
+ ldr r2, [r0, #RB_RST_GROUP]
+ mov r3, r2
+ orr r2, r2, #RST_DSP
+ bic r3, r3, #RST_DSP
+
+ ldr r5, =RB_CLK_CMD_DSP
+ add r5, r5, r0
+ ldr r6, =RB_RST_GROUP
+ add r6, r6, r0
+
+.Lsyncdsp:
+ /* Disable DSP clock */
+ mov r1, #0
+ str r1, [r5]
+ /* Enable DSP clock */
+ mov r1, #1
+ str r1, [r5]
+ /* Ensure synchronization of clock enable */
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ /* Assert DSP reset */
+ mov r1, r2
+ str r1, [r6]
+ /* Ensure synchronization of reset assertion */
+ nop
+ nop
+ nop
+ nop
+
+ /* De-assert DSP reset */
+ mov r1, r3
+ str r1, [r6]
+ /* Ensure synchronization of reset de-assertion */
+ nop
+ nop
+ nop
+
+ sub r4, r4, #1
+ cmp r4, #0
+ bne .Lsyncdsp
+
+ /* back to my caller */
+ mov pc, lr
+
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
index 261249081b..fdaa7d5fd9 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
@@ -355,6 +355,13 @@ poll_RB_CLK_DIV_STAT_ARM:
cmp r1, #CLK_DIV_ARM_2
bne poll_RB_CLK_DIV_STAT_ARM
+ /*
+ * Synchronise DSP
+ */
+ mov ip, lr
+ bl dsp_init
+ mov lr, ip
+
/*
* Detect NVRAM address
*/