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authorCyril Jourdan2012-08-23 14:21:18 +0200
committerCyril Jourdan2012-09-20 11:23:15 +0200
commit6a5e70d7bfaf614706501b843b27ca06e9b1f725 (patch)
treeb60b03dc8ab163983f75b5ffa1cf9792bb201d48 /cleopatre/u-boot-1.1.6/cpu
parenta788ca277ca3e0840eaf2183331ade318dd62cce (diff)
cleo/uboot/cpu/spc300: handle MSE500 eth clocks config, refs #2961
Diffstat (limited to 'cleopatre/u-boot-1.1.6/cpu')
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/Makefile4
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/mseeth.S263
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/start.S22
3 files changed, 277 insertions, 12 deletions
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile b/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile
index d695aa42cc..01ae45a5d1 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile
@@ -23,8 +23,8 @@ LIB = lib$(CPU).a
START = start.o
OBJS = interrupts.o cpu.o timer.o serial.o wdt.o
-SOBJS = reset.o spcpll.o msepll.o spceth.o nvram.o dsp.o sdram.o miu.o \
- spcpio.o iomux.o
+SOBJS = reset.o spcpll.o msepll.o spceth.o mseeth.o nvram.o dsp.o sdram.o \
+ miu.o spcpio.o iomux.o
all: .depend $(START) $(LIB)
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/mseeth.S b/cleopatre/u-boot-1.1.6/cpu/spc300/mseeth.S
new file mode 100644
index 0000000000..26d513ceaf
--- /dev/null
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/mseeth.S
@@ -0,0 +1,263 @@
+/*
+ * cpu/spc300/mseeth.S
+ *
+ * Copyright (C) 2012 SPiDCOM Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+#ifdef CONFIG_CHIP_FEATURE_MSEETH
+
+#include <asm/hardware.h>
+#include <asm/arch/nvram.h>
+
+/* We want to be able to loop over every eth interface clocks to configure,
+ * whatever the number of interfaces.
+ * But with maria_reg_bank file, there is no way to get clock registers offset
+ * without the eth interface number offset.
+ * We must make a special case for eth config registers, because they are in
+ * another part of the regbank, and the offset between them is different.
+ * If you did not understand this comment (and I apologize if so), please read
+ * the source, Luke. */
+#define ETH_1_TO_ETH_2_CLK_OFFSET (RB_CLK_CMD_ETH2_RMII - RB_CLK_CMD_ETH1_RMII)
+#define ETH_1_TO_ETH_2_CFG_OFFSET (RB_ETH2_CONFIG - RB_ETH1_CONFIG)
+
+ .file "mseeth.S"
+
+ .text
+ .arm @ This is ARM code; performs the same action as .code 32
+ .align 2 @ Align to word boundary; "2" means the number of bits that must be zero
+ .globl ethernet_config
+ .type ethernet_config, %function
+
+ .macro setreg, offset, val, base, tmp
+ ldr \tmp, =\val
+ str \tmp, [\base, #\offset]
+ .endm
+
+ .macro checkreg, offset, val, base, tmp
+1: ldr \tmp, [\base, #\offset]
+ cmp \tmp, #\val
+ bne 1b
+ .endm
+
+ /*
+ * Find Ethernet Mode from NVRAM
+ * we assume that r10 = NVRAM Base Address
+ */
+ .macro getmode, mode, shift, mask
+ ldr \mode, [r10, #NVRAM_PKG_CFG_OFFSET]
+ lsr \mode, \mode, #\shift
+ and \mode, \mode, #\mask
+ .endm
+
+ /* Branch to selected mode configuration. */
+ .macro modebranch, mode
+ cmp \mode, #NVRAM_ETH_MODE_MII
+ beq .Lmii /* eth_mode = MII */
+ cmp \mode, #NVRAM_ETH_MODE_RMII
+ beq .Lrmii /* eth_mode = RMII */
+ cmp \mode, #NVRAM_ETH_MODE_GMII
+ beq .Lgmii /* eth_mode = GMII */
+ cmp \mode, #NVRAM_ETH_MODE_RGMII
+ beq .Lrgmii /* eth_mode = RGMII */
+ .endm
+
+ /* Set regbank offset for ETH2 management. See defines above. */
+ .macro rboffset, base, offset, ethcount
+ cmp \ethcount, #1
+ ldreq \base, =(MARIA_REGBANK_BASE+\offset)
+ .endm
+
+ /* Config loop management. */
+ .macro endconfig ethcount, tmp
+ add \ethcount, \ethcount, #1
+ adr \tmp, .Lethmodetable
+ add pc, \tmp, \ethcount, lsl #2
+ .endm
+
+ethernet_config:
+ ldr r0, =MARIA_REGBANK_BASE
+
+ /*
+ * Switch off all Ethernet clock commands
+ */
+ setreg RB_CLK_CMD_ETH1_TX_OFFSET, CLK_CMD_OFF, r0, r1
+ checkreg RB_CLK_STAT_ETH1_TX_OFFSET, CLK_ETH_TX_RX_IS_OFF, r0, r1
+ setreg RB_CLK_CMD_ETH1_RX_OFFSET, CLK_CMD_OFF, r0, r1
+ checkreg RB_CLK_STAT_ETH1_RX_OFFSET, CLK_ETH_TX_RX_IS_OFF, r0, r1
+ setreg RB_CLK_CMD_ETH1_RMII_OFFSET, CLK_CMD_OFF, r0, r1
+ checkreg RB_CLK_STAT_ETH1_RMII_OFFSET, CLK_ETH_RMII_IS_OFF, r0, r1
+
+ setreg RB_CLK_CMD_ETH2_TX_OFFSET, CLK_CMD_OFF, r0, r1
+ checkreg RB_CLK_STAT_ETH2_TX_OFFSET, CLK_ETH_TX_RX_IS_OFF, r0, r1
+ setreg RB_CLK_CMD_ETH2_RX_OFFSET, CLK_CMD_OFF, r0, r1
+ checkreg RB_CLK_STAT_ETH2_RX_OFFSET, CLK_ETH_TX_RX_IS_OFF, r0, r1
+ setreg RB_CLK_CMD_ETH2_RMII_OFFSET, CLK_CMD_OFF, r0, r1
+ checkreg RB_CLK_STAT_ETH2_RMII_OFFSET, CLK_ETH_RMII_IS_OFF, r0, r1
+
+ /*
+ * Enable PHY Clock
+ */
+ /* release EXT reset for ETH PHY clock */
+ ldr r1, [r0, #RB_RST_MODULE_OFFSET]
+ bic r1, r1, #RST_EXT /* clear bit 12 of RB_RST_MODULE, sw_rst_ext -> 0 */
+ str r1, [r0, #RB_RST_MODULE_OFFSET]
+ /* Enable PHY Clock */
+ setreg RB_CLK_CMD_OUT25_OFFSET, CLK_CMD_ON, r0, r1
+ checkreg RB_CLK_STAT_OUT25_OFFSET, CLK_IS_ON, r0, r1
+
+ /* Initialise eth config counter. */
+ mov r1, #0
+
+.Lethone:
+ getmode r2, NVRAM_ETH1_MODE_SHIFT, NVRAM_ETH1_MODE_MASK
+ modebranch r2
+
+.Lethtwo:
+ getmode r2, NVRAM_ETH2_MODE_SHIFT, NVRAM_ETH2_MODE_MASK
+ modebranch r2
+
+.Lmii:
+ /* MII mode */
+ /* Ethernet Config for MII mode */
+ rboffset r0, ETH_1_TO_ETH_2_CFG_OFFSET, r1
+ setreg RB_ETH1_CONFIG_OFFSET, 0, r0, r2
+ rboffset r0, ETH_1_TO_ETH_2_CLK_OFFSET, r1
+
+ /* Enable TX clock */
+ setreg RB_CLK_SEL_ETH1_TX_OFFSET, CLK_SEL_ETH_TX_RX_MII_CLK, r0, r2
+ checkreg RB_CLK_SEL_STAT_ETH1_TX_OFFSET, CLK_SEL_ETH_TX_RX_MII_CLK, r0, r2
+
+ setreg RB_CLK_CMD_ETH1_TX_OFFSET, CLK_CMD_MII_ON, r0, r2
+ checkreg RB_CLK_STAT_ETH1_TX_OFFSET, CLK_ETH_TX_RX_MII_IS_ON, r0, r2
+
+ /* Enable RX clock */
+ setreg RB_CLK_SEL_ETH1_RX_OFFSET, CLK_SEL_ETH_TX_RX_MII_CLK, r0, r2
+ checkreg RB_CLK_SEL_STAT_ETH1_RX_OFFSET, CLK_SEL_ETH_TX_RX_MII_CLK, r0, r2
+
+ setreg RB_CLK_CMD_ETH1_RX_OFFSET, CLK_CMD_MII_ON, r0, r2
+ checkreg RB_CLK_STAT_ETH1_RX_OFFSET, CLK_ETH_TX_RX_MII_IS_ON, r0, r2
+
+ endconfig r1, r2
+
+.Lrmii:
+ /*
+ * RMII mode
+ * Default config is for 100 Mb/s.
+ */
+ /* Ethernet Config for RMII mode */
+ rboffset r0, ETH_1_TO_ETH_2_CFG_OFFSET, r1
+ setreg RB_ETH1_CONFIG_OFFSET, (ETH_CFG_RMII|ETH_CFG_RMII_100), r0, r2
+ rboffset r0, ETH_1_TO_ETH_2_CLK_OFFSET, r1
+
+ /* Set PLL dividers. */
+ setreg RB_CLK_DIV_ETH1_TX_PLL_OFFSET, CLK_ETH_DIV_TX_PLL_10, r0, r2
+ setreg RB_CLK_DIV_ETH1_RX_PLL_OFFSET, CLK_ETH_DIV_RX_PLL_10, r0, r2
+
+ /* Enable TX clock */
+ setreg RB_CLK_SEL_ETH1_TX_OFFSET, CLK_SEL_ETH_TX_RX_PLL_CLK, r0, r2
+ checkreg RB_CLK_SEL_STAT_ETH1_TX_OFFSET, CLK_SEL_ETH_TX_RX_PLL_CLK, r0, r2
+
+ setreg RB_CLK_CMD_ETH1_TX_OFFSET, CLK_CMD_PLL_ON, r0, r2
+ checkreg RB_CLK_STAT_ETH1_TX_OFFSET, CLK_ETH_TX_RX_PLL_IS_ON, r0, r2
+
+ /* Enable RX clock */
+ setreg RB_CLK_SEL_ETH1_RX_OFFSET, CLK_SEL_ETH_TX_RX_PLL_CLK, r0, r2
+ checkreg RB_CLK_SEL_STAT_ETH1_RX_OFFSET, CLK_SEL_ETH_TX_RX_PLL_CLK, r0, r2
+
+ setreg RB_CLK_CMD_ETH1_RX_OFFSET, CLK_CMD_PLL_ON, r0, r2
+ checkreg RB_CLK_STAT_ETH1_RX_OFFSET, CLK_ETH_TX_RX_PLL_IS_ON, r0, r2
+
+ /* Enable RMII clock */
+ setreg RB_CLK_SEL_ETH1_RMII_OFFSET, CLK_SEL_ETH_RMII_PLL_CLK, r0, r2
+ checkreg RB_CLK_SEL_STAT_ETH1_RMII_OFFSET, CLK_SEL_ETH_RMII_PLL_CLK, r0, r2
+
+ setreg RB_CLK_CMD_ETH1_RMII_OFFSET, CLK_CMD_RMII_PLL_ON, r0, r2
+ checkreg RB_CLK_STAT_ETH1_RMII_OFFSET, CLK_ETH_RMII_PLL_IS_ON, r0, r2
+
+ endconfig r1, r2
+
+.Lgmii:
+ /*
+ * GMII mode
+ * Default config is for 1000 Mb/s.
+ */
+ /* Ethernet Config for GMII mode */
+ rboffset r0, ETH_1_TO_ETH_2_CFG_OFFSET, r1
+ setreg RB_ETH1_CONFIG_OFFSET, 0, r0, r2
+ rboffset r0, ETH_1_TO_ETH_2_CLK_OFFSET, r1
+
+ /* Set PLL divider. */
+ setreg RB_CLK_DIV_ETH1_TX_PLL_OFFSET, CLK_ETH_DIV_TX_PLL_2, r0, r2
+
+ /* Enable TX clock */
+ setreg RB_CLK_SEL_ETH1_TX_OFFSET, CLK_SEL_ETH_TX_RX_PLL_CLK, r0, r2
+ checkreg RB_CLK_SEL_STAT_ETH1_TX_OFFSET, CLK_SEL_ETH_TX_RX_PLL_CLK, r0, r2
+
+ setreg RB_CLK_CMD_ETH1_TX_OFFSET, CLK_CMD_PLL_ON, r0, r2
+ checkreg RB_CLK_STAT_ETH1_TX_OFFSET, CLK_ETH_TX_RX_PLL_IS_ON, r0, r2
+
+ /* Enable RX clock */
+ setreg RB_CLK_SEL_ETH1_RX_OFFSET, CLK_SEL_ETH_TX_RX_MII_CLK, r0, r2
+ checkreg RB_CLK_SEL_STAT_ETH1_RX_OFFSET, CLK_SEL_ETH_TX_RX_MII_CLK, r0, r2
+
+ setreg RB_CLK_CMD_ETH1_RX_OFFSET, CLK_CMD_MII_ON, r0, r2
+ checkreg RB_CLK_STAT_ETH1_RX_OFFSET, CLK_ETH_TX_RX_MII_IS_ON, r0, r2
+
+ endconfig r1, r2
+
+.Lrgmii:
+ /*
+ * RGMII mode
+ * Default config is for 1000 Mb/s.
+ */
+ /* Ethernet Config for GMII mode */
+ rboffset r0, ETH_1_TO_ETH_2_CFG_OFFSET, r1
+ setreg RB_ETH1_CONFIG_OFFSET, ETH_CFG_RGMII, r0, r2
+ rboffset r0, ETH_1_TO_ETH_2_CLK_OFFSET, r1
+
+ /* Set PLL divider. */
+ setreg RB_CLK_DIV_ETH1_TX_PLL_OFFSET, CLK_ETH_DIV_TX_PLL_2, r0, r2
+
+ /* Enable TX clock */
+ setreg RB_CLK_SEL_ETH1_TX_OFFSET, CLK_SEL_ETH_TX_RX_PLL_CLK, r0, r2
+ checkreg RB_CLK_SEL_STAT_ETH1_TX_OFFSET, CLK_SEL_ETH_TX_RX_PLL_CLK, r0, r2
+
+ setreg RB_CLK_CMD_ETH1_TX_OFFSET, CLK_CMD_PLL_ON, r0, r2
+ checkreg RB_CLK_STAT_ETH1_TX_OFFSET, CLK_ETH_TX_RX_PLL_IS_ON, r0, r2
+
+ /* Enable RX clock */
+ setreg RB_CLK_SEL_ETH1_RX_OFFSET, CLK_SEL_ETH_TX_RX_MII_CLK, r0, r2
+ checkreg RB_CLK_SEL_STAT_ETH1_RX_OFFSET, CLK_SEL_ETH_TX_RX_MII_CLK, r0, r2
+
+ setreg RB_CLK_CMD_ETH1_RX_OFFSET, CLK_CMD_MII_ON, r0, r2
+ checkreg RB_CLK_STAT_ETH1_RX_OFFSET, CLK_ETH_TX_RX_MII_IS_ON, r0, r2
+
+ endconfig r1, r2
+
+.Lreturn:
+ /* back to my caller */
+ mov pc, lr
+
+.Lethmodetable:
+ b .Lethone
+ b .Lethtwo
+ b .Lreturn
+
+#endif /* CONFIG_CHIP_FEATURE_SPCETH */
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
index 4fc9064bb2..b6d75574a7 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
@@ -280,7 +280,7 @@ in_sdram:
bl gpio_pio_init /* we pass NVRAM addr in r10; do not corrupt r10 in this function */
#endif
-#if defined(CONFIG_CHIP_FEATURE_SPCETH)
+#if defined(CONFIG_CHIP_FEATURE_SPCETH) || defined(CONFIG_CHIP_FEATURE_MSEETH)
/*
* Configure Ethernet IP
@@ -289,10 +289,6 @@ in_sdram:
bl ethernet_config /* we pass NVRAM addr in r10; do not corrupt r10 in this function */
mov lr, ip /* restore link */
-#endif
-
-#ifndef CONFIG_CHIP_FEATURE_NO_RESET
-
/*
* Release the resets
*/
@@ -321,19 +317,25 @@ in_sdram:
cmp r0, #0
bne .Lwaitrst
-#endif /* CONFIG_CHIP_FEATURE_NO_RESET */
+#endif /* CONFIG_CHIP_FEATURE_SPCETH || CONFIG_CHIP_FEATURE_MSEETH */
bl_no_nvram:
-#ifndef CONFIG_CHIP_FEATURE_NO_RESET
-
- /* EXT reset */
+#if defined(CONFIG_CHIP_FEATURE_SPCETH)
+ /* EXT and ETH reset */
ldr r0, =MARIA_REGBANK_BASE
ldr r1, [r0, #RB_RST_MODULE_OFFSET]
bic r1, r1, #RST_ETH /* clear bit 8 of RB_RST_MODULE, sw_rst_eth -> 0 */
bic r1, r1, #RST_EXT /* clear bit 12 of RB_RST_MODULE, sw_rst_ext -> 0 */
str r1, [r0, #RB_RST_MODULE_OFFSET]
-
+#elif defined(CONFIG_CHIP_FEATURE_MSEETH)
+ /* EXT and ETH reset */
+ ldr r0, =MARIA_REGBANK_BASE
+ ldr r1, [r0, #RB_RST_MODULE_OFFSET]
+ bic r1, r1, #RST_ETH1 /* clear bit 8 of RB_RST_MODULE, sw_rst_eth1 -> 0 */
+ bic r1, r1, #RST_ETH2 /* clear bit 13 of RB_RST_MODULE, sw_rst_eth2 -> 0 */
+ bic r1, r1, #RST_EXT /* clear bit 12 of RB_RST_MODULE, sw_rst_ext -> 0 */
+ str r1, [r0, #RB_RST_MODULE_OFFSET]
#endif
/*