summaryrefslogtreecommitdiff
path: root/cleopatre/u-boot-1.1.6/cpu
diff options
context:
space:
mode:
authorMSE500 Team2012-03-22 16:35:00 +0100
committerNicolas Schodet2012-05-09 10:41:11 +0200
commitf90d1c90f65217429e0f585dd8104a58a9c3974e (patch)
tree1a153feedf78f0bd271cfa06b79a969a40713dfd /cleopatre/u-boot-1.1.6/cpu
parentfa87405fb517806231ed85234c1c11e8a2ff3cbc (diff)
cleo/u-boot: add support for MIU controller, refs #2758
Diffstat (limited to 'cleopatre/u-boot-1.1.6/cpu')
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/Makefile2
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/miu.S66
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/nvram.S9
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/sdram.S5
4 files changed, 81 insertions, 1 deletions
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile b/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile
index 6c4ccc9b1f..ab0922d72b 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile
@@ -23,7 +23,7 @@ LIB = lib$(CPU).a
START = start.o
OBJS = interrupts.o cpu.o timer.o serial.o wdt.o
-SOBJS = reset.o pll_init.o eth_init.o nvram.o dsp.o sdram.o
+SOBJS = reset.o pll_init.o eth_init.o nvram.o dsp.o sdram.o miu.o
all: .depend $(START) $(LIB)
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/miu.S b/cleopatre/u-boot-1.1.6/cpu/spc300/miu.S
new file mode 100644
index 0000000000..ce69ae6892
--- /dev/null
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/miu.S
@@ -0,0 +1,66 @@
+/*
+ * cpu/spc300/miu.S
+ *
+ * Copyright (C) 2012 SPiDCOM Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/nvram.h>
+
+/* Skip file if not using MIU controller. */
+#ifdef CONFIG_CHIP_FEATURE_MIU_CTRL
+
+ .file "miu.S"
+
+ .text
+ .arm @ This is ARM code; performs the same action as .code 32
+ .align 2 @ Align to word boundary; "2" means the number of bits that must be zero
+ .globl sdram_init
+ .type sdram_init, %function
+
+
+sdram_init:
+ ldr r0, =MIU_REG_BASE
+ ldr r1, [r10, #NVRAM_MIU_CONFIG_OFFSET]
+ lsr r2, r1, #16 /* r2: config size. */
+ lsl r1, r1, #16
+ lsrs r1, r1, #16 /* r1: offset in nvram. */
+1: beq 1b /* Infinite loop of death if no MIU config. */
+
+1: /* Write registers according to config words.
+ * Each config word is composed of:
+ * - bit 31 to 16: an offset in word to add to MIU_REG_BASE,
+ * - bit 15 to 0: the value to write at this address. */
+ ldr r3, [r10, r1, lsl #2]
+ lsr r4, r3, #16 /* r4: offset. */
+ lsl r3, r3, #16
+ lsr r3, r3, #16 /* r3: value to write. */
+ str r3, [r0, r4, lsl #2]
+ add r1, r1, #1
+ subs r2, r2, #1
+ bne 1b
+
+1: /* Wait until init done. */
+ ldr r3, [r0, #MIU_INIT_DONE_REG]
+ tst r3, #(1 << MIU_INIT_DONE_BIT)
+ beq 1b
+
+ /* Back to my caller. */
+ mov pc, lr
+
+#endif /* CONFIG_CHIP_FEATURE_MIU_CTRL */
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/nvram.S b/cleopatre/u-boot-1.1.6/cpu/spc300/nvram.S
index 92c4a3b28d..f21a751025 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/nvram.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/nvram.S
@@ -107,10 +107,19 @@ nvram_dft:
.word 0x00000000 /* gpio_0_7_cfg */
.word 0x00000000 /* gpio_8_15_cfg */
.word 0xffffffff /* gpio_allow_dir*/
+#if defined (CONFIG_CHIP_FEATURE_SDRAM_CTRL)
.word 0x001c3168 /* sdram_config */
.word 0x022a569a /* sdram_timing0 */
.word 0x00070008 /* sdram_timing1 */
.word 0x00000410 /* sdram_refresh */
+#elif defined (CONFIG_CHIP_FEATURE_MIU_CTRL)
+ .word 0 /* miu_config */
+ .word 0 /* miu_ram_size */
+ .word 0
+ .word 0
+#else
+# error "Unknown DRAM controller"
+#endif
.word 0x00000007 /* flash_org */
.word 0x00140000 /* img_0_offset */
.word 0x00000001 /* nb_images */
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/sdram.S b/cleopatre/u-boot-1.1.6/cpu/spc300/sdram.S
index 364cfde74a..a61bb8fbc0 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/sdram.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/sdram.S
@@ -22,6 +22,9 @@
#include <config.h>
#include <asm/arch/nvram.h>
+/* Skip file if not using SDRAM controller. */
+#ifdef CONFIG_CHIP_FEATURE_SDRAM_CTRL
+
.file "sdram.S"
.text
@@ -87,3 +90,5 @@ sdram_init:
/* Back to my caller. */
mov pc, lr
+
+#endif /* CONFIG_CHIP_FEATURE_SDRAM_CTRL */