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-rw-r--r--2004/n/fpga/src/gpio/ISE_bch/gpio_direction_tbw.tbw37
-rw-r--r--2004/n/fpga/src/gpio/ISE_bch/gpio_direction_tbw.vhd118
-rw-r--r--2004/n/fpga/src/gpio/ISE_bch/gpio_it_detect_tbw.tbw44
-rw-r--r--2004/n/fpga/src/gpio/ISE_bch/gpio_it_detect_tbw.vhd149
-rw-r--r--2004/n/fpga/src/gpio/ISE_bch/gpio_tbw.tbw70
-rw-r--r--2004/n/fpga/src/gpio/ISE_bch/gpio_tbw.vhd285
-rw-r--r--2004/n/fpga/src/registre/ISE_bch/reg_rw_tbw.tbw47
-rw-r--r--2004/n/fpga/src/registre/ISE_bch/reg_rw_tbw.vhd174
-rw-r--r--2004/n/fpga/src/registre/registre.sws157
-rw-r--r--2004/n/fpga/src/three-state/ISE_bch/tristate_tbw.tbw40
-rw-r--r--2004/n/fpga/src/three-state/ISE_bch/tristate_tbw.vhd127
11 files changed, 1091 insertions, 157 deletions
diff --git a/2004/n/fpga/src/gpio/ISE_bch/gpio_direction_tbw.tbw b/2004/n/fpga/src/gpio/ISE_bch/gpio_direction_tbw.tbw
new file mode 100644
index 0000000..fa37948
--- /dev/null
+++ b/2004/n/fpga/src/gpio/ISE_bch/gpio_direction_tbw.tbw
@@ -0,0 +1,37 @@
+info x 27 510 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VHDL
+col x 257 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+radix x 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+entity name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gpio_direction
+term mark 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+vlib save 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+library work;
+use work.isa_const.all;
+use work.nono_const.all;
+
+var add 1 7 0 36 21 0 257 100 0 0 0 0 0 50 50 0 direction_maskInstd_logic_vectorRISING_EDGENone
+var add 2 7 0 36 22 0 257 100 0 0 0 0 0 50 50 0 data_inInstd_logic_vectorRISING_EDGENone
+var add 3 7 0 36 23 0 257 100 0 0 0 0 0 50 50 0 data_outOutstd_logic_vectorRISING_EDGENone
+vdone xxx 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+npos xxx 160 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+cell fill 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000100
+cell fill 1 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000111
+cell fill 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000001
+cell fill 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000010
+cell fill 2 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000111
+time info 50 50 10 10 50 50 0 1 0 0 0 0 0 0 0 0 ns
+font save -14 0 400 49 0 0 0 0 0 0 0 0 0 0 0 0 Times New Roman
+src mod 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f:\cours\i2\electronique\vhdl\projet\carte_fpga\src\gpio\gpio_direction.vhd
+utd false 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+cellenab on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+grid on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+com add 1 1 0 514 5 0 -79 0 0 0 0 0 0 0 0 0 Waveform created by
+HDL Bencher 6.1i
+Source = f:\cours\i2\electronique\vhdl\projet\carte_fpga\src\gpio\gpio_direction.vhd
+Wed Mar 17 10:48:32 2004
+type info 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clkBITDOWNTO
+opt vhdl87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+NumClocks x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+Zoom_level x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1.00000000000000
diff --git a/2004/n/fpga/src/gpio/ISE_bch/gpio_direction_tbw.vhd b/2004/n/fpga/src/gpio/ISE_bch/gpio_direction_tbw.vhd
new file mode 100644
index 0000000..f313d4b
--- /dev/null
+++ b/2004/n/fpga/src/gpio/ISE_bch/gpio_direction_tbw.vhd
@@ -0,0 +1,118 @@
+-- F:\COURS\I2\ELECTRONIQUE\VHDL\PROJET\CARTE_FPGA\GPIO
+-- VHDL Test Bench created by
+-- HDL Bencher 6.1i
+-- Wed Mar 17 10:54:56 2004
+--
+-- Notes:
+-- 1) This testbench has been automatically generated from
+-- your Test Bench Waveform
+-- 2) To use this as a user modifiable testbench do the following:
+-- - Save it as a file with a .vhd extension (i.e. File->Save As...)
+-- - Add it to your project as a testbench source (i.e. Project->Add Source...)
+--
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+LIBRARY WORK;
+USE WORK.ISA_CONST.ALL;
+USE WORK.NONO_CONST.ALL;
+USE IEEE.STD_LOGIC_TEXTIO.ALL;
+USE STD.TEXTIO.ALL;
+
+ENTITY gpio_direction_tbw IS
+END gpio_direction_tbw;
+
+ARCHITECTURE testbench_arch OF gpio_direction_tbw IS
+-- If you get a compiler error on the following line,
+-- from the menu do Options->Configuration select VHDL 87
+FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
+ COMPONENT gpio_direction
+ PORT (
+ direction_mask : In std_logic_vector (7 DOWNTO 0);
+ data_in : In std_logic_vector (7 DOWNTO 0);
+ data_out : Out std_logic_vector (7 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ SIGNAL direction_mask : std_logic_vector (7 DOWNTO 0);
+ SIGNAL data_in : std_logic_vector (7 DOWNTO 0);
+ SIGNAL data_out : std_logic_vector (7 DOWNTO 0);
+
+BEGIN
+ UUT : gpio_direction
+ PORT MAP (
+ direction_mask => direction_mask,
+ data_in => data_in,
+ data_out => data_out
+ );
+
+ PROCESS
+ VARIABLE TX_OUT : LINE;
+ VARIABLE TX_ERROR : INTEGER := 0;
+
+ PROCEDURE CHECK_data_out(
+ next_data_out : std_logic_vector (7 DOWNTO 0);
+ TX_TIME : INTEGER
+ ) IS
+ VARIABLE TX_STR : String(1 to 4096);
+ VARIABLE TX_LOC : LINE;
+ BEGIN
+ -- If compiler error ("/=" is ambiguous) occurs in the next line of code
+ -- change compiler settings to use explicit declarations only
+ IF (data_out /= next_data_out) THEN
+ STD.TEXTIO.write(TX_LOC,string'("Error at time="));
+ STD.TEXTIO.write(TX_LOC, TX_TIME);
+ STD.TEXTIO.write(TX_LOC,string'("ns data_out="));
+ IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, data_out);
+ STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
+ IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_data_out);
+ STD.TEXTIO.write(TX_LOC, string'(" "));
+ TX_STR(TX_LOC.all'range) := TX_LOC.all;
+ STD.TEXTIO.writeline(results, TX_LOC);
+ STD.TEXTIO.Deallocate(TX_LOC);
+ ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
+ TX_ERROR := TX_ERROR + 1;
+ END IF;
+ END;
+
+ BEGIN
+ -- --------------------
+ direction_mask <= transport std_logic_vector'("00000100"); --4
+ data_in <= transport std_logic_vector'("00000001"); --1
+ -- --------------------
+ WAIT FOR 200 ns; -- Time=200 ns
+ data_in <= transport std_logic_vector'("00000010"); --2
+ -- --------------------
+ WAIT FOR 200 ns; -- Time=400 ns
+ data_in <= transport std_logic_vector'("00000111"); --7
+ -- --------------------
+ WAIT FOR 200 ns; -- Time=600 ns
+ direction_mask <= transport std_logic_vector'("00000111"); --7
+ -- --------------------
+ WAIT FOR 300 ns; -- Time=900 ns
+ -- --------------------
+
+ IF (TX_ERROR = 0) THEN
+ STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
+ STD.TEXTIO.writeline(results, TX_OUT);
+ ASSERT (FALSE) REPORT
+ "Simulation successful (not a failure). No problems detected. "
+ SEVERITY FAILURE;
+ ELSE
+ STD.TEXTIO.write(TX_OUT, TX_ERROR);
+ STD.TEXTIO.write(TX_OUT, string'(
+ " errors found in simulation"));
+ STD.TEXTIO.writeline(results, TX_OUT);
+ ASSERT (FALSE) REPORT
+ "Errors found during simulation"
+ SEVERITY FAILURE;
+ END IF;
+ END PROCESS;
+END testbench_arch;
+
+CONFIGURATION gpio_direction_cfg OF gpio_direction_tbw IS
+ FOR testbench_arch
+ END FOR;
+END gpio_direction_cfg;
diff --git a/2004/n/fpga/src/gpio/ISE_bch/gpio_it_detect_tbw.tbw b/2004/n/fpga/src/gpio/ISE_bch/gpio_it_detect_tbw.tbw
new file mode 100644
index 0000000..7e61c83
--- /dev/null
+++ b/2004/n/fpga/src/gpio/ISE_bch/gpio_it_detect_tbw.tbw
@@ -0,0 +1,44 @@
+info x 36 510 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VHDL
+col x 257 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+radix x 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+entity name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gpio_it_detect
+term mark 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+vlib save 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 library ieee;
+use ieee.std_logic_1164.all;
+library work;
+use work.isa_const.all;
+use work.nono_const.all;
+
+var add 1 0 0 226 26 0 257 100 50 50 10 10 0 0 0 0 clkInstd_logicDUAL_EDGEclk
+var add 2 0 0 98 27 0 257 50 25 25 10 10 0 0 0 0 rstInstd_logicDUAL_EDGEclk
+var add 3 7 0 100 28 0 257 50 25 25 10 10 0 0 0 0 data_inInstd_logic_vectorDUAL_EDGEclk
+var add 4 7 0 100 29 0 257 50 25 25 10 10 0 0 0 0 it_maskInstd_logic_vectorDUAL_EDGEclk
+var add 5 0 0 98 30 0 257 50 25 25 10 10 0 0 0 0 it_detectedOutstd_logicDUAL_EDGEclk
+vdone xxx 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+npos xxx 114 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+cell fill 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
+cell fill 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 2 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 2 44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
+cell fill 2 48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000010
+cell fill 3 28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00001000
+cell fill 3 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000001
+cell fill 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000010
+cell fill 4 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000010
+cell fill 4 28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000001
+time info 50 50 10 10 50 50 1 1 0 0 0 0 0 0 0 0 nsclk
+font save -14 0 400 49 0 0 0 0 0 0 0 0 0 0 0 0 Times New Roman
+src mod 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f:\cours\i2\electronique\vhdl\projet\carte_fpga\src\gpio\gpio_it_detect.vhd
+utd false 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+cellenab on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+grid on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+com add 1 0 10 523 7 0 -79 0 0 0 0 0 0 0 0 0 Waveform created by
+HDL Bencher 6.1i
+Source = f:\cours\i2\electronique\vhdl\projet\carte_fpga\src\gpio\gpio_it_detect.vhd
+Wed Mar 17 10:57:35 2004
+type info 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clkBITDOWNTO
+opt vhdl87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+NumClocks x 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+clock_1 name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clk
+Zoom_level x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0.66666666666667
diff --git a/2004/n/fpga/src/gpio/ISE_bch/gpio_it_detect_tbw.vhd b/2004/n/fpga/src/gpio/ISE_bch/gpio_it_detect_tbw.vhd
new file mode 100644
index 0000000..9b1fc14
--- /dev/null
+++ b/2004/n/fpga/src/gpio/ISE_bch/gpio_it_detect_tbw.vhd
@@ -0,0 +1,149 @@
+-- F:\COURS\I2\ELECTRONIQUE\VHDL\PROJET\CARTE_FPGA\GPIO
+-- VHDL Test Bench created by
+-- HDL Bencher 6.1i
+-- Thu Mar 18 10:28:20 2004
+--
+-- Notes:
+-- 1) This testbench has been automatically generated from
+-- your Test Bench Waveform
+-- 2) To use this as a user modifiable testbench do the following:
+-- - Save it as a file with a .vhd extension (i.e. File->Save As...)
+-- - Add it to your project as a testbench source (i.e. Project->Add Source...)
+--
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+LIBRARY WORK;
+USE WORK.ISA_CONST.ALL;
+USE WORK.NONO_CONST.ALL;
+USE IEEE.STD_LOGIC_TEXTIO.ALL;
+USE STD.TEXTIO.ALL;
+
+ENTITY gpio_it_detect_tbw IS
+END gpio_it_detect_tbw;
+
+ARCHITECTURE testbench_arch OF gpio_it_detect_tbw IS
+-- If you get a compiler error on the following line,
+-- from the menu do Options->Configuration select VHDL 87
+FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
+ COMPONENT gpio_it_detect
+ PORT (
+ clk : In std_logic;
+ rst : In std_logic;
+ data_in : In std_logic_vector (7 DOWNTO 0);
+ it_mask : In std_logic_vector (7 DOWNTO 0);
+ it_detected : Out std_logic
+ );
+ END COMPONENT;
+
+ SIGNAL clk : std_logic;
+ SIGNAL rst : std_logic;
+ SIGNAL data_in : std_logic_vector (7 DOWNTO 0);
+ SIGNAL it_mask : std_logic_vector (7 DOWNTO 0);
+ SIGNAL it_detected : std_logic;
+
+BEGIN
+ UUT : gpio_it_detect
+ PORT MAP (
+ clk => clk,
+ rst => rst,
+ data_in => data_in,
+ it_mask => it_mask,
+ it_detected => it_detected
+ );
+
+ PROCESS -- clock process for clk,
+ BEGIN
+ CLOCK_LOOP : LOOP
+ clk <= transport '0';
+ WAIT FOR 10 ns;
+ clk <= transport '1';
+ WAIT FOR 10 ns;
+ WAIT FOR 40 ns;
+ clk <= transport '0';
+ WAIT FOR 40 ns;
+ END LOOP CLOCK_LOOP;
+ END PROCESS;
+
+ PROCESS -- Process for clk
+ VARIABLE TX_OUT : LINE;
+ VARIABLE TX_ERROR : INTEGER := 0;
+
+ PROCEDURE CHECK_it_detected(
+ next_it_detected : std_logic;
+ TX_TIME : INTEGER
+ ) IS
+ VARIABLE TX_STR : String(1 to 4096);
+ VARIABLE TX_LOC : LINE;
+ BEGIN
+ -- If compiler error ("/=" is ambiguous) occurs in the next line of code
+ -- change compiler settings to use explicit declarations only
+ IF (it_detected /= next_it_detected) THEN
+ STD.TEXTIO.write(TX_LOC,string'("Error at time="));
+ STD.TEXTIO.write(TX_LOC, TX_TIME);
+ STD.TEXTIO.write(TX_LOC,string'("ns it_detected="));
+ IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, it_detected);
+ STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
+ IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_it_detected);
+ STD.TEXTIO.write(TX_LOC, string'(" "));
+ TX_STR(TX_LOC.all'range) := TX_LOC.all;
+ STD.TEXTIO.writeline(results, TX_LOC);
+ STD.TEXTIO.Deallocate(TX_LOC);
+ ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
+ TX_ERROR := TX_ERROR + 1;
+ END IF;
+ END;
+
+ BEGIN
+ -- --------------------
+ rst <= transport '1';
+ data_in <= transport std_logic_vector'("00000010"); --2
+ it_mask <= transport std_logic_vector'("00000010"); --2
+ -- --------------------
+ WAIT FOR 50 ns; -- Time=50 ns
+ rst <= transport '0';
+ -- --------------------
+ WAIT FOR 50 ns; -- Time=100 ns
+ rst <= transport '0';
+ -- --------------------
+ WAIT FOR 50 ns; -- Time=150 ns
+ it_mask <= transport std_logic_vector'("00000010"); --2
+ -- --------------------
+ WAIT FOR 200 ns; -- Time=350 ns
+ data_in <= transport std_logic_vector'("00001000"); --8
+ it_mask <= transport std_logic_vector'("00000001"); --1
+ -- --------------------
+ WAIT FOR 100 ns; -- Time=450 ns
+ data_in <= transport std_logic_vector'("00000001"); --1
+ -- --------------------
+ WAIT FOR 100 ns; -- Time=550 ns
+ rst <= transport '1';
+ -- --------------------
+ WAIT FOR 50 ns; -- Time=600 ns
+ rst <= transport '0';
+ -- --------------------
+ WAIT FOR 250 ns; -- Time=850 ns
+ -- --------------------
+
+ IF (TX_ERROR = 0) THEN
+ STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
+ STD.TEXTIO.writeline(results, TX_OUT);
+ ASSERT (FALSE) REPORT
+ "Simulation successful (not a failure). No problems detected. "
+ SEVERITY FAILURE;
+ ELSE
+ STD.TEXTIO.write(TX_OUT, TX_ERROR);
+ STD.TEXTIO.write(TX_OUT, string'(
+ " errors found in simulation"));
+ STD.TEXTIO.writeline(results, TX_OUT);
+ ASSERT (FALSE) REPORT
+ "Errors found during simulation"
+ SEVERITY FAILURE;
+ END IF;
+ END PROCESS;
+END testbench_arch;
+
+CONFIGURATION gpio_it_detect_cfg OF gpio_it_detect_tbw IS
+ FOR testbench_arch
+ END FOR;
+END gpio_it_detect_cfg;
diff --git a/2004/n/fpga/src/gpio/ISE_bch/gpio_tbw.tbw b/2004/n/fpga/src/gpio/ISE_bch/gpio_tbw.tbw
new file mode 100644
index 0000000..d08ba0c
--- /dev/null
+++ b/2004/n/fpga/src/gpio/ISE_bch/gpio_tbw.tbw
@@ -0,0 +1,70 @@
+info x 61 510 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VHDL
+col x 257 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+radix x 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+entity name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gpio
+term mark 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+vlib save 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+library work;
+use work.nono_const.all;
+
+var add 2 0 0 226 16 0 257 200 100 100 10 10 0 0 0 0 clk_iInstd_logicDUAL_EDGEclk_i
+var add 1 0 0 98 15 0 257 100 50 50 10 10 0 0 0 0 rstInstd_logicDUAL_EDGEclk_i
+var add 4 0 0 98 18 0 257 100 50 50 10 10 0 0 0 0 rwInstd_logicDUAL_EDGEclk_i
+var add 9 0 0 98 24 0 257 100 50 50 10 10 0 0 0 0 cs_reg_directionInstd_logicDUAL_EDGEclk_i
+var add 10 0 0 98 25 0 257 100 50 50 10 10 0 0 0 0 cs_reg_it_maskInstd_logicDUAL_EDGEclk_i
+var add 8 0 0 98 23 0 257 100 50 50 10 10 0 0 0 0 cs_reg_dataInstd_logicDUAL_EDGEclk_i
+var add 11 0 0 98 26 0 257 100 50 50 10 10 0 0 0 0 cs_read_outputInstd_logicDUAL_EDGEclk_i
+var add 6 7 0 100 20 0 257 100 50 50 10 10 0 0 0 0 bus_dataInOutstd_logic_vectorDUAL_EDGEclk_i
+var add 7 7 0 100 21 0 257 100 50 50 10 10 0 0 0 0 io_outputInOutstd_logic_vectorDUAL_EDGEclk_i
+var add 3 0 0 226 17 0 257 100 50 50 10 10 0 0 0 0 clk_mInstd_logicRISING_EDGEclk_m
+var add 5 0 0 98 19 0 257 100 50 50 10 10 0 0 0 0 interruptOutstd_logicRISING_EDGEclk_m
+vdone xxx 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+npos xxx 139 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+cell fill 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
+cell fill 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 3 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
+cell fill 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 4 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
+cell fill 4 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 4 48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
+cell fill 4 56 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 5 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
+cell fill 5 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 5 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
+cell fill 5 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 6 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
+cell fill 6 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 6 64 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
+cell fill 6 72 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 7 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
+cell fill 7 88 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000000
+cell fill 8 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000111
+cell fill 8 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11111000
+cell fill 8 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000001
+cell fill 8 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ZZZZZZZZ
+cell fill 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00001ZZZ
+cell fill 9 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00100ZZZ
+time info 50 50 10 10 100 100 1 0 0 0 0 0 0 0 0 0 ns
+font save -14 0 400 49 0 0 0 0 0 0 0 0 0 0 0 0 Times New Roman
+src mod 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f:\cours\i2\electronique\vhdl\projet\carte_fpga\src\gpio\gpio.vhd
+utd false 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+cellenab on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+grid on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+com add 1 0 10 461 13 0 -79 0 0 0 0 0 0 0 0 0 Waveform created by
+HDL Bencher 6.1i
+Source = f:\cours\i2\electronique\vhdl\projet\carte_fpga\src\gpio\gpio.vhd
+Wed Mar 17 16:59:37 2004
+type info 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clkBITDOWNTO
+opt vhdl87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+NumClocks x 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+clock_1 name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clk_i
+clock_2 name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clk_m
+Zoom_level x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1.50000000000002
diff --git a/2004/n/fpga/src/gpio/ISE_bch/gpio_tbw.vhd b/2004/n/fpga/src/gpio/ISE_bch/gpio_tbw.vhd
new file mode 100644
index 0000000..a2ba527
--- /dev/null
+++ b/2004/n/fpga/src/gpio/ISE_bch/gpio_tbw.vhd
@@ -0,0 +1,285 @@
+-- F:\COURS\I2\ELECTRONIQUE\VHDL\PROJET\CARTE_FPGA\GPIO
+-- VHDL Test Bench created by
+-- HDL Bencher 6.1i
+-- Thu Mar 18 10:17:36 2004
+--
+-- Notes:
+-- 1) This testbench has been automatically generated from
+-- your Test Bench Waveform
+-- 2) To use this as a user modifiable testbench do the following:
+-- - Save it as a file with a .vhd extension (i.e. File->Save As...)
+-- - Add it to your project as a testbench source (i.e. Project->Add Source...)
+--
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+LIBRARY WORK;
+USE WORK.NONO_CONST.ALL;
+USE IEEE.STD_LOGIC_TEXTIO.ALL;
+USE STD.TEXTIO.ALL;
+
+ENTITY gpio_tbw IS
+END gpio_tbw;
+
+ARCHITECTURE testbench_arch OF gpio_tbw IS
+-- If you get a compiler error on the following line,
+-- from the menu do Options->Configuration select VHDL 87
+FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
+ COMPONENT gpio
+ PORT (
+ rst : In std_logic;
+ clk_i : In std_logic;
+ clk_m : In std_logic;
+ rw : In std_logic;
+ interrupt : Out std_logic;
+ bus_data : InOut std_logic_vector (7 DOWNTO 0);
+ io_output : InOut std_logic_vector (7 DOWNTO 0);
+ cs_reg_data : In std_logic;
+ cs_reg_direction : In std_logic;
+ cs_reg_it_mask : In std_logic;
+ cs_read_output : In std_logic
+ );
+ END COMPONENT;
+
+ SIGNAL rst : std_logic;
+ SIGNAL clk_i : std_logic;
+ SIGNAL clk_m : std_logic;
+ SIGNAL rw : std_logic;
+ SIGNAL interrupt : std_logic;
+ SIGNAL bus_data : std_logic_vector (7 DOWNTO 0);
+ SIGNAL io_output : std_logic_vector (7 DOWNTO 0);
+ SIGNAL cs_reg_data : std_logic;
+ SIGNAL cs_reg_direction : std_logic;
+ SIGNAL cs_reg_it_mask : std_logic;
+ SIGNAL cs_read_output : std_logic;
+
+BEGIN
+ UUT : gpio
+ PORT MAP (
+ rst => rst,
+ clk_i => clk_i,
+ clk_m => clk_m,
+ rw => rw,
+ interrupt => interrupt,
+ bus_data => bus_data,
+ io_output => io_output,
+ cs_reg_data => cs_reg_data,
+ cs_reg_direction => cs_reg_direction,
+ cs_reg_it_mask => cs_reg_it_mask,
+ cs_read_output => cs_read_output
+ );
+
+ PROCESS -- clock process for clk_i,
+ BEGIN
+ CLOCK_LOOP : LOOP
+ clk_i <= transport '1';
+ WAIT FOR 10 ns;
+ clk_i <= transport '0';
+ WAIT FOR 10 ns;
+ WAIT FOR 90 ns;
+ clk_i <= transport '1';
+ WAIT FOR 90 ns;
+ END LOOP CLOCK_LOOP;
+ END PROCESS;
+
+ PROCESS -- clock process for clk_m,
+ BEGIN
+ CLOCK_LOOP : LOOP
+ clk_m <= transport '1';
+ WAIT FOR 10 ns;
+ clk_m <= transport '0';
+ WAIT FOR 10 ns;
+ WAIT FOR 40 ns;
+ clk_m <= transport '1';
+ WAIT FOR 40 ns;
+ END LOOP CLOCK_LOOP;
+ END PROCESS;
+
+ PROCESS -- Process for clk_i
+ VARIABLE TX_OUT : LINE;
+ VARIABLE TX_ERROR : INTEGER := 0;
+
+ PROCEDURE CHECK_bus_data(
+ next_bus_data : std_logic_vector (7 DOWNTO 0);
+ TX_TIME : INTEGER
+ ) IS
+ VARIABLE TX_STR : String(1 to 4096);
+ VARIABLE TX_LOC : LINE;
+ BEGIN
+ -- If compiler error ("/=" is ambiguous) occurs in the next line of code
+ -- change compiler settings to use explicit declarations only
+ IF (bus_data /= next_bus_data) THEN
+ STD.TEXTIO.write(TX_LOC,string'("Error at time="));
+ STD.TEXTIO.write(TX_LOC, TX_TIME);
+ STD.TEXTIO.write(TX_LOC,string'("ns bus_data="));
+ IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, bus_data);
+ STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
+ IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_bus_data);
+ STD.TEXTIO.write(TX_LOC, string'(" "));
+ TX_STR(TX_LOC.all'range) := TX_LOC.all;
+ STD.TEXTIO.writeline(results, TX_LOC);
+ STD.TEXTIO.Deallocate(TX_LOC);
+ ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
+ TX_ERROR := TX_ERROR + 1;
+ END IF;
+ END;
+
+ PROCEDURE CHECK_io_output(
+ next_io_output : std_logic_vector (7 DOWNTO 0);
+ TX_TIME : INTEGER
+ ) IS
+ VARIABLE TX_STR : String(1 to 4096);
+ VARIABLE TX_LOC : LINE;
+ BEGIN
+ -- If compiler error ("/=" is ambiguous) occurs in the next line of code
+ -- change compiler settings to use explicit declarations only
+ IF (io_output /= next_io_output) THEN
+ STD.TEXTIO.write(TX_LOC,string'("Error at time="));
+ STD.TEXTIO.write(TX_LOC, TX_TIME);
+ STD.TEXTIO.write(TX_LOC,string'("ns io_output="));
+ IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, io_output);
+ STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
+ IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_io_output);
+ STD.TEXTIO.write(TX_LOC, string'(" "));
+ TX_STR(TX_LOC.all'range) := TX_LOC.all;
+ STD.TEXTIO.writeline(results, TX_LOC);
+ STD.TEXTIO.Deallocate(TX_LOC);
+ ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
+ TX_ERROR := TX_ERROR + 1;
+ END IF;
+ END;
+
+ BEGIN
+ -- --------------------
+ rst <= transport '1';
+ rw <= transport '0';
+ cs_reg_direction <= transport '0';
+ cs_reg_it_mask <= transport '0';
+ cs_reg_data <= transport '0';
+ cs_read_output <= transport '0';
+ bus_data <= transport std_logic_vector'("00000000"); --0
+ io_output <= transport std_logic_vector'("00001ZZZ"); --?
+ -- --------------------
+ WAIT FOR 100 ns; -- Time=100 ns
+ rst <= transport '0';
+ bus_data <= transport std_logic_vector'("00000111"); --7
+ -- --------------------
+ WAIT FOR 100 ns; -- Time=200 ns
+ cs_reg_direction <= transport '1';
+ -- --------------------
+ WAIT FOR 200 ns; -- Time=400 ns
+ cs_reg_direction <= transport '0';
+ cs_reg_it_mask <= transport '1';
+ bus_data <= transport std_logic_vector'("11111000"); --F8
+ -- --------------------
+ WAIT FOR 200 ns; -- Time=600 ns
+ cs_reg_it_mask <= transport '0';
+ cs_reg_data <= transport '1';
+ bus_data <= transport std_logic_vector'("00000001"); --1
+ -- --------------------
+ WAIT FOR 200 ns; -- Time=800 ns
+ rw <= transport '1';
+ cs_reg_it_mask <= transport '1';
+ cs_reg_data <= transport '0';
+ bus_data <= transport std_logic_vector'("ZZZZZZZZ"); --Z
+ -- --------------------
+ WAIT FOR 200 ns; -- Time=1000 ns
+ cs_reg_it_mask <= transport '0';
+ io_output <= transport std_logic_vector'("00100ZZZ"); --2?
+ -- --------------------
+ WAIT FOR 200 ns; -- Time=1200 ns
+ cs_reg_direction <= transport '1';
+ -- --------------------
+ WAIT FOR 200 ns; -- Time=1400 ns
+ cs_reg_direction <= transport '0';
+ -- --------------------
+ WAIT FOR 200 ns; -- Time=1600 ns
+ cs_reg_data <= transport '1';
+ -- --------------------
+ WAIT FOR 200 ns; -- Time=1800 ns
+ cs_reg_data <= transport '0';
+ -- --------------------
+ WAIT FOR 200 ns; -- Time=2000 ns
+ cs_read_output <= transport '1';
+ -- --------------------
+ WAIT FOR 200 ns; -- Time=2200 ns
+ cs_read_output <= transport '0';
+ -- --------------------
+ WAIT FOR 320 ns; -- Time=2520 ns
+ -- --------------------
+
+ IF (TX_ERROR = 0) THEN
+ STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
+ STD.TEXTIO.writeline(results, TX_OUT);
+ ASSERT (FALSE) REPORT
+ "Simulation successful (not a failure). No problems detected. "
+ SEVERITY FAILURE;
+ ELSE
+ STD.TEXTIO.write(TX_OUT, TX_ERROR);
+ STD.TEXTIO.write(TX_OUT, string'(
+ " errors found in simulation"));
+ STD.TEXTIO.writeline(results, TX_OUT);
+ ASSERT (FALSE) REPORT
+ "Errors found during simulation"
+ SEVERITY FAILURE;
+ END IF;
+ END PROCESS;
+ PROCESS -- Process for clk_m
+ VARIABLE TX_OUT : LINE;
+ VARIABLE TX_ERROR : INTEGER := 0;
+
+ PROCEDURE CHECK_interrupt(
+ next_interrupt : std_logic;
+ TX_TIME : INTEGER
+ ) IS
+ VARIABLE TX_STR : String(1 to 4096);
+ VARIABLE TX_LOC : LINE;
+ BEGIN
+ -- If compiler error ("/=" is ambiguous) occurs in the next line of code
+ -- change compiler settings to use explicit declarations only
+ IF (interrupt /= next_interrupt) THEN
+ STD.TEXTIO.write(TX_LOC,string'("Error at time="));
+ STD.TEXTIO.write(TX_LOC, TX_TIME);
+ STD.TEXTIO.write(TX_LOC,string'("ns interrupt="));
+ IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, interrupt);
+ STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
+ IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_interrupt);
+ STD.TEXTIO.write(TX_LOC, string'(" "));
+ TX_STR(TX_LOC.all'range) := TX_LOC.all;
+ STD.TEXTIO.writeline(results, TX_LOC);
+ STD.TEXTIO.Deallocate(TX_LOC);
+ ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
+ TX_ERROR := TX_ERROR + 1;
+ END IF;
+ END;
+
+ BEGIN
+ -- --------------------
+ -- --------------------
+ WAIT FOR 2510 ns; -- Time=2510 ns
+ -- --------------------
+
+ IF (TX_ERROR = 0) THEN
+ STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
+ STD.TEXTIO.writeline(results, TX_OUT);
+ ASSERT (FALSE) REPORT
+ "Simulation successful (not a failure). No problems detected. "
+ SEVERITY FAILURE;
+ ELSE
+ STD.TEXTIO.write(TX_OUT, TX_ERROR);
+ STD.TEXTIO.write(TX_OUT, string'(
+ " errors found in simulation"));
+ STD.TEXTIO.writeline(results, TX_OUT);
+ ASSERT (FALSE) REPORT
+ "Errors found during simulation"
+ SEVERITY FAILURE;
+ END IF;
+ END PROCESS;
+END testbench_arch;
+
+CONFIGURATION gpio_cfg OF gpio_tbw IS
+ FOR testbench_arch
+ END FOR;
+END gpio_cfg;
diff --git a/2004/n/fpga/src/registre/ISE_bch/reg_rw_tbw.tbw b/2004/n/fpga/src/registre/ISE_bch/reg_rw_tbw.tbw
new file mode 100644
index 0000000..c4ec12e
--- /dev/null
+++ b/2004/n/fpga/src/registre/ISE_bch/reg_rw_tbw.tbw
@@ -0,0 +1,47 @@
+info x 37 510 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VHDL
+col x 257 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+radix x 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+entity name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reg_rw
+term mark 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+vlib save 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+library work;
+use work.isa_const.all;
+use work.nono_const.all;
+
+var add 1 0 0 226 23 0 257 100 50 50 10 10 0 0 0 0 clkInstd_logicFALLING_EDGEclk
+var add 2 0 0 98 24 0 257 100 50 50 10 10 0 0 0 0 rstInstd_logicFALLING_EDGEclk
+var add 3 0 0 98 25 0 257 100 50 50 10 10 0 0 0 0 rwInstd_logicFALLING_EDGEclk
+var add 4 0 0 98 26 0 257 100 50 50 10 10 0 0 0 0 enableInstd_logicFALLING_EDGEclk
+var add 6 7 0 100 28 0 257 100 50 50 10 10 0 0 0 0 data_outOutstd_logic_vectorFALLING_EDGEclk
+var add 5 7 0 100 27 0 257 100 50 50 10 10 0 0 0 0 dataInOutstd_logic_vectorFALLING_EDGEclk
+vdone xxx 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+npos xxx 120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+cell fill 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
+cell fill 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 3 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
+cell fill 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
+cell fill 4 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 4 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
+cell fill 4 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000001
+cell fill 6 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000010
+cell fill 6 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ZZZZZZZZ
+time info 50 50 10 10 50 50 1 0 0 0 0 0 0 0 0 0 nsclk
+font save -14 0 400 49 0 0 0 0 0 0 0 0 0 0 0 0 Times New Roman
+src mod 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f:\cours\i2\electronique\vhdl\projet\carte_fpga\src\registre\reg_rw.vhd
+utd false 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+cellenab on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+grid on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+com add 1 1 16 499 11 -16 -95 0 0 0 0 0 0 0 0 0 Waveform created by
+HDL Bencher 6.1i
+Source = f:\cours\i2\electronique\vhdl\projet\carte_fpga\src\registre\reg_rw.vhd
+Sat Mar 13 17:10:47 2004
+opt vhdl87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+NumClocks x 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+clock_1 name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clk
+Zoom_level x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0.66666666666667
diff --git a/2004/n/fpga/src/registre/ISE_bch/reg_rw_tbw.vhd b/2004/n/fpga/src/registre/ISE_bch/reg_rw_tbw.vhd
new file mode 100644
index 0000000..2a78156
--- /dev/null
+++ b/2004/n/fpga/src/registre/ISE_bch/reg_rw_tbw.vhd
@@ -0,0 +1,174 @@
+-- F:\COURS\I2\ELECTRONIQUE\VHDL\PROJET\CARTE_FPGA\REG_RW
+-- VHDL Test Bench created by
+-- HDL Bencher 6.1i
+-- Tue Mar 16 09:26:23 2004
+--
+-- Notes:
+-- 1) This testbench has been automatically generated from
+-- your Test Bench Waveform
+-- 2) To use this as a user modifiable testbench do the following:
+-- - Save it as a file with a .vhd extension (i.e. File->Save As...)
+-- - Add it to your project as a testbench source (i.e. Project->Add Source...)
+--
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+LIBRARY WORK;
+USE WORK.ISA_CONST.ALL;
+USE WORK.NONO_CONST.ALL;
+USE IEEE.STD_LOGIC_TEXTIO.ALL;
+USE STD.TEXTIO.ALL;
+
+ENTITY reg_rw_tbw IS
+END reg_rw_tbw;
+
+ARCHITECTURE testbench_arch OF reg_rw_tbw IS
+-- If you get a compiler error on the following line,
+-- from the menu do Options->Configuration select VHDL 87
+FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
+ COMPONENT reg_rw
+ PORT (
+ clk : In std_logic;
+ rst : In std_logic;
+ rw : In std_logic;
+ enable : In std_logic;
+ data : InOut std_logic_vector (7 DOWNTO 0);
+ data_out : Out std_logic_vector (7 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ SIGNAL clk : std_logic;
+ SIGNAL rst : std_logic;
+ SIGNAL rw : std_logic;
+ SIGNAL enable : std_logic;
+ SIGNAL data : std_logic_vector (7 DOWNTO 0);
+ SIGNAL data_out : std_logic_vector (7 DOWNTO 0);
+
+BEGIN
+ UUT : reg_rw
+ PORT MAP (
+ clk => clk,
+ rst => rst,
+ rw => rw,
+ enable => enable,
+ data => data,
+ data_out => data_out
+ );
+
+ PROCESS -- clock process for clk,
+ BEGIN
+ CLOCK_LOOP : LOOP
+ clk <= transport '1';
+ WAIT FOR 10 ns;
+ clk <= transport '0';
+ WAIT FOR 10 ns;
+ WAIT FOR 40 ns;
+ clk <= transport '1';
+ WAIT FOR 40 ns;
+ END LOOP CLOCK_LOOP;
+ END PROCESS;
+
+ PROCESS -- Process for clk
+ VARIABLE TX_OUT : LINE;
+ VARIABLE TX_ERROR : INTEGER := 0;
+
+ PROCEDURE CHECK_data_out(
+ next_data_out : std_logic_vector (7 DOWNTO 0);
+ TX_TIME : INTEGER
+ ) IS
+ VARIABLE TX_STR : String(1 to 4096);
+ VARIABLE TX_LOC : LINE;
+ BEGIN
+ -- If compiler error ("/=" is ambiguous) occurs in the next line of code
+ -- change compiler settings to use explicit declarations only
+ IF (data_out /= next_data_out) THEN
+ STD.TEXTIO.write(TX_LOC,string'("Error at time="));
+ STD.TEXTIO.write(TX_LOC, TX_TIME);
+ STD.TEXTIO.write(TX_LOC,string'("ns data_out="));
+ IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, data_out);
+ STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
+ IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_data_out);
+ STD.TEXTIO.write(TX_LOC, string'(" "));
+ TX_STR(TX_LOC.all'range) := TX_LOC.all;
+ STD.TEXTIO.writeline(results, TX_LOC);
+ STD.TEXTIO.Deallocate(TX_LOC);
+ ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
+ TX_ERROR := TX_ERROR + 1;
+ END IF;
+ END;
+
+ PROCEDURE CHECK_data(
+ next_data : std_logic_vector (7 DOWNTO 0);
+ TX_TIME : INTEGER
+ ) IS
+ VARIABLE TX_STR : String(1 to 4096);
+ VARIABLE TX_LOC : LINE;
+ BEGIN
+ -- If compiler error ("/=" is ambiguous) occurs in the next line of code
+ -- change compiler settings to use explicit declarations only
+ IF (data /= next_data) THEN
+ STD.TEXTIO.write(TX_LOC,string'("Error at time="));
+ STD.TEXTIO.write(TX_LOC, TX_TIME);
+ STD.TEXTIO.write(TX_LOC,string'("ns data="));
+ IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, data);
+ STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
+ IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_data);
+ STD.TEXTIO.write(TX_LOC, string'(" "));
+ TX_STR(TX_LOC.all'range) := TX_LOC.all;
+ STD.TEXTIO.writeline(results, TX_LOC);
+ STD.TEXTIO.Deallocate(TX_LOC);
+ ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
+ TX_ERROR := TX_ERROR + 1;
+ END IF;
+ END;
+
+ BEGIN
+ -- --------------------
+ rst <= transport '1';
+ rw <= transport '0';
+ enable <= transport '0';
+ data <= transport std_logic_vector'("00000001"); --1
+ -- --------------------
+ WAIT FOR 100 ns; -- Time=100 ns
+ rst <= transport '0';
+ enable <= transport '1';
+ -- --------------------
+ WAIT FOR 100 ns; -- Time=200 ns
+ rw <= transport '1';
+ enable <= transport '0';
+ data <= transport std_logic_vector'("00000010"); --2
+ -- --------------------
+ WAIT FOR 200 ns; -- Time=400 ns
+ enable <= transport '1';
+ data <= transport std_logic_vector'("ZZZZZZZZ"); --Z
+ -- --------------------
+ WAIT FOR 100 ns; -- Time=500 ns
+ enable <= transport '0';
+ -- --------------------
+ WAIT FOR 320 ns; -- Time=820 ns
+ -- --------------------
+
+ IF (TX_ERROR = 0) THEN
+ STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
+ STD.TEXTIO.writeline(results, TX_OUT);
+ ASSERT (FALSE) REPORT
+ "Simulation successful (not a failure). No problems detected. "
+ SEVERITY FAILURE;
+ ELSE
+ STD.TEXTIO.write(TX_OUT, TX_ERROR);
+ STD.TEXTIO.write(TX_OUT, string'(
+ " errors found in simulation"));
+ STD.TEXTIO.writeline(results, TX_OUT);
+ ASSERT (FALSE) REPORT
+ "Errors found during simulation"
+ SEVERITY FAILURE;
+ END IF;
+ END PROCESS;
+END testbench_arch;
+
+CONFIGURATION reg_rw_cfg OF reg_rw_tbw IS
+ FOR testbench_arch
+ END FOR;
+END reg_rw_cfg;
diff --git a/2004/n/fpga/src/registre/registre.sws b/2004/n/fpga/src/registre/registre.sws
deleted file mode 100644
index 07969d3..0000000
--- a/2004/n/fpga/src/registre/registre.sws
+++ /dev/null
@@ -1,157 +0,0 @@
-#
-# This file has been automatically generated by the Symphony EDA IDE
-# Please do NOT modify this file manually. If you do, do it with
-# extreme care. This file represents your project settings. Corrupting
-# this file can render this file useless!!!
-#
-# Begin version identification section
-[version]
- version = 1
-[]
-# Begin libraries section (used by all tools)
-[libraries]
- ieee = $SYMPHONYEDA/lib/ieee/ieee.sym
- registre = registre.sym
-[]
-# End of libraries section
- [options]
- [booloption]
- name = -strict
- value = 0
- invert = 0
- []
- [booloption]
- name = -s
- value = 0
- invert = 0
- []
- [stringoption]
- name = -breakon
- value = FAILURE
- []
- [stringoption]
- name = -stdin
- value = ""
- []
- [stringoption]
- name = -stdout
- value = ""
- []
- [stringoption]
- name = -coverage
- value = ""
- []
- [multistringoption]
- name = -nowarn
- []
- [multistringoption]
- name = -noaccel
- []
- [multistringoption]
- name = -sdftyp
- []
- [multistringoption]
- name = -sdfmin
- []
- [multistringoption]
- name = -sdfmax
- []
- []
-# Begin description of library ieee
-[library]
- name = ieee
- [options]
- [booloption]
- name = -87
- value = 0
- invert = 0
- []
- [booloption]
- name = -x
- value = 0
- invert = 0
- []
- [booloption]
- name = -s
- value = 1
- invert = 0
- []
- [booloption]
- name = -strict
- value = 0
- invert = 0
- []
- [intoption]
- name = -maxerrors
- value = 10
- []
- [booloption]
- name = -autoorder
- value = 1
- invert = 0
- []
- []
-[]
-# End description of library ieee
-# Begin description of library registre
-[library]
- name = registre
- toplevel = testreg(sim1)
- [options]
- [booloption]
- name = -87
- value = 0
- invert = 0
- []
- [booloption]
- name = -x
- value = 0
- invert = 0
- []
- [booloption]
- name = -s
- value = 1
- invert = 0
- []
- [booloption]
- name = -strict
- value = 0
- invert = 0
- []
- [intoption]
- name = -maxerrors
- value = 10
- []
- [booloption]
- name = -autoorder
- value = 1
- invert = 0
- []
- []
- [file]
- name = ../modele/isa_const.vhd
- [options]
- []
- []
- [file]
- name = ../modele/nono_const.vhd
- [options]
- []
- []
- [file]
- name = registre.vhd
- [options]
- []
- []
- [file]
- name = test_reg.vhd
- [options]
- []
- []
-[]
-# End description of library registre
-# Begin various workspace properties
-[properties]
- work =registre
-[]
-# End workspace properties
diff --git a/2004/n/fpga/src/three-state/ISE_bch/tristate_tbw.tbw b/2004/n/fpga/src/three-state/ISE_bch/tristate_tbw.tbw
new file mode 100644
index 0000000..cd25e78
--- /dev/null
+++ b/2004/n/fpga/src/three-state/ISE_bch/tristate_tbw.tbw
@@ -0,0 +1,40 @@
+info x 30 510 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VHDL
+col x 257 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+radix x 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+entity name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tristate
+term mark 19 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+vlib save 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+library work;
+use work.isa_const.all;
+use work.nono_const.all;
+
+var add 1 0 0 34 23 0 257 100 0 0 0 0 0 50 50 0 enableInstd_logicRISING_EDGENone
+var add 2 7 0 36 24 0 257 100 0 0 0 0 0 50 50 0 data_inInstd_logic_vectorRISING_EDGENone
+var add 3 7 0 36 25 0 257 100 0 0 0 0 0 50 50 0 data_outOutstd_logic_vectorRISING_EDGENone
+vdone xxx 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+npos xxx 120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+cell fill 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 1 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
+cell fill 1 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 1 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
+cell fill 1 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11111111
+cell fill 2 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000001
+cell fill 2 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000110
+time info 50 50 10 10 50 50 0 1 0 0 0 0 0 0 0 0 ns
+font save -14 0 400 49 0 0 0 0 0 0 0 0 0 0 0 0 Times New Roman
+src mod 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f:\cours\i2\electronique\vhdl\projet\carte_fpga\src\three-state\tristate.vhd
+utd false 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+cellenab on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+grid on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+com add 1 2 -20 480 9 -9 -88 0 0 0 0 0 0 0 0 0 Waveform created by
+HDL Bencher 6.1i
+Source = f:\cours\i2\electronique\vhdl\projet\carte_fpga\src\three-state\tristate.vhd
+Tue Mar 16 11:13:51 2004
+type info 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clkBITDOWNTO
+opt vhdl87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+NumClocks x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+Zoom_level x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1.00000000000000
diff --git a/2004/n/fpga/src/three-state/ISE_bch/tristate_tbw.vhd b/2004/n/fpga/src/three-state/ISE_bch/tristate_tbw.vhd
new file mode 100644
index 0000000..45d7ad5
--- /dev/null
+++ b/2004/n/fpga/src/three-state/ISE_bch/tristate_tbw.vhd
@@ -0,0 +1,127 @@
+-- F:\COURS\I2\ELECTRONIQUE\VHDL\PROJET\CARTE_FPGA\GPIO
+-- VHDL Test Bench created by
+-- HDL Bencher 6.1i
+-- Wed Mar 17 10:43:07 2004
+--
+-- Notes:
+-- 1) This testbench has been automatically generated from
+-- your Test Bench Waveform
+-- 2) To use this as a user modifiable testbench do the following:
+-- - Save it as a file with a .vhd extension (i.e. File->Save As...)
+-- - Add it to your project as a testbench source (i.e. Project->Add Source...)
+--
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+LIBRARY WORK;
+USE WORK.ISA_CONST.ALL;
+USE WORK.NONO_CONST.ALL;
+USE IEEE.STD_LOGIC_TEXTIO.ALL;
+USE STD.TEXTIO.ALL;
+
+ENTITY tristate_tbw IS
+END tristate_tbw;
+
+ARCHITECTURE testbench_arch OF tristate_tbw IS
+-- If you get a compiler error on the following line,
+-- from the menu do Options->Configuration select VHDL 87
+FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
+ COMPONENT tristate
+ PORT (
+ enable : In std_logic;
+ data_in : In std_logic_vector (7 DOWNTO 0);
+ data_out : Out std_logic_vector (7 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ SIGNAL enable : std_logic;
+ SIGNAL data_in : std_logic_vector (7 DOWNTO 0);
+ SIGNAL data_out : std_logic_vector (7 DOWNTO 0);
+
+BEGIN
+ UUT : tristate
+ PORT MAP (
+ enable => enable,
+ data_in => data_in,
+ data_out => data_out
+ );
+
+ PROCESS
+ VARIABLE TX_OUT : LINE;
+ VARIABLE TX_ERROR : INTEGER := 0;
+
+ PROCEDURE CHECK_data_out(
+ next_data_out : std_logic_vector (7 DOWNTO 0);
+ TX_TIME : INTEGER
+ ) IS
+ VARIABLE TX_STR : String(1 to 4096);
+ VARIABLE TX_LOC : LINE;
+ BEGIN
+ -- If compiler error ("/=" is ambiguous) occurs in the next line of code
+ -- change compiler settings to use explicit declarations only
+ IF (data_out /= next_data_out) THEN
+ STD.TEXTIO.write(TX_LOC,string'("Error at time="));
+ STD.TEXTIO.write(TX_LOC, TX_TIME);
+ STD.TEXTIO.write(TX_LOC,string'("ns data_out="));
+ IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, data_out);
+ STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
+ IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_data_out);
+ STD.TEXTIO.write(TX_LOC, string'(" "));
+ TX_STR(TX_LOC.all'range) := TX_LOC.all;
+ STD.TEXTIO.writeline(results, TX_LOC);
+ STD.TEXTIO.Deallocate(TX_LOC);
+ ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
+ TX_ERROR := TX_ERROR + 1;
+ END IF;
+ END;
+
+ BEGIN
+ -- --------------------
+ enable <= transport '0';
+ data_in <= transport std_logic_vector'("11111111"); --FF
+ -- --------------------
+ WAIT FOR 200 ns; -- Time=200 ns
+ enable <= transport '1';
+ -- --------------------
+ WAIT FOR 200 ns; -- Time=400 ns
+ enable <= transport '0';
+ -- --------------------
+ WAIT FOR 100 ns; -- Time=500 ns
+ data_in <= transport std_logic_vector'("00000001"); --1
+ -- --------------------
+ WAIT FOR 100 ns; -- Time=600 ns
+ enable <= transport '1';
+ -- --------------------
+ WAIT FOR 200 ns; -- Time=800 ns
+ enable <= transport '0';
+ -- --------------------
+ WAIT FOR 100 ns; -- Time=900 ns
+ data_in <= transport std_logic_vector'("00000110"); --6
+ -- --------------------
+ WAIT FOR 150 ns; -- Time=1050 ns
+ -- --------------------
+
+ IF (TX_ERROR = 0) THEN
+ STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
+ STD.TEXTIO.writeline(results, TX_OUT);
+ ASSERT (FALSE) REPORT
+ "Simulation successful (not a failure). No problems detected. "
+ SEVERITY FAILURE;
+ ELSE
+ STD.TEXTIO.write(TX_OUT, TX_ERROR);
+ STD.TEXTIO.write(TX_OUT, string'(
+ " errors found in simulation"));
+ STD.TEXTIO.writeline(results, TX_OUT);
+ ASSERT (FALSE) REPORT
+ "Errors found during simulation"
+ SEVERITY FAILURE;
+ END IF;
+ END PROCESS;
+END testbench_arch;
+
+CONFIGURATION tristate_cfg OF tristate_tbw IS
+ FOR testbench_arch
+ END FOR;
+END tristate_cfg;