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-- F:\COURS\I2\ELECTRONIQUE\VHDL\PROJET\CARTE_FPGA\GPIO
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Mar 18 10:17:36 2004
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY WORK;
USE WORK.NONO_CONST.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY gpio_tbw IS
END gpio_tbw;

ARCHITECTURE testbench_arch OF gpio_tbw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT gpio
		PORT (
			rst : In  std_logic;
			clk_i : In  std_logic;
			clk_m : In  std_logic;
			rw : In  std_logic;
			interrupt : Out  std_logic;
			bus_data : InOut  std_logic_vector (7 DOWNTO 0);
			io_output : InOut  std_logic_vector (7 DOWNTO 0);
			cs_reg_data : In  std_logic;
			cs_reg_direction : In  std_logic;
			cs_reg_it_mask : In  std_logic;
			cs_read_output : In  std_logic
		);
	END COMPONENT;

	SIGNAL rst : std_logic;
	SIGNAL clk_i : std_logic;
	SIGNAL clk_m : std_logic;
	SIGNAL rw : std_logic;
	SIGNAL interrupt : std_logic;
	SIGNAL bus_data : std_logic_vector (7 DOWNTO 0);
	SIGNAL io_output : std_logic_vector (7 DOWNTO 0);
	SIGNAL cs_reg_data : std_logic;
	SIGNAL cs_reg_direction : std_logic;
	SIGNAL cs_reg_it_mask : std_logic;
	SIGNAL cs_read_output : std_logic;

BEGIN
	UUT : gpio
	PORT MAP (
		rst => rst,
		clk_i => clk_i,
		clk_m => clk_m,
		rw => rw,
		interrupt => interrupt,
		bus_data => bus_data,
		io_output => io_output,
		cs_reg_data => cs_reg_data,
		cs_reg_direction => cs_reg_direction,
		cs_reg_it_mask => cs_reg_it_mask,
		cs_read_output => cs_read_output
	);

	PROCESS -- clock process for clk_i,
	BEGIN
		CLOCK_LOOP : LOOP
		clk_i <= transport '1';
		WAIT FOR 10 ns;
		clk_i <= transport '0';
		WAIT FOR 10 ns;
		WAIT FOR 90 ns;
		clk_i <= transport '1';
		WAIT FOR 90 ns;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS -- clock process for clk_m,
	BEGIN
		CLOCK_LOOP : LOOP
		clk_m <= transport '1';
		WAIT FOR 10 ns;
		clk_m <= transport '0';
		WAIT FOR 10 ns;
		WAIT FOR 40 ns;
		clk_m <= transport '1';
		WAIT FOR 40 ns;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk_i
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_bus_data(
			next_bus_data : std_logic_vector (7 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (bus_data /= next_bus_data) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns bus_data="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, bus_data);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_bus_data);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_io_output(
			next_io_output : std_logic_vector (7 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (io_output /= next_io_output) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns io_output="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, io_output);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_io_output);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		rst <= transport '1';
		rw <= transport '0';
		cs_reg_direction <= transport '0';
		cs_reg_it_mask <= transport '0';
		cs_reg_data <= transport '0';
		cs_read_output <= transport '0';
		bus_data <= transport std_logic_vector'("00000000"); --0
		io_output <= transport std_logic_vector'("00001ZZZ"); --?
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		rst <= transport '0';
		bus_data <= transport std_logic_vector'("00000111"); --7
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		cs_reg_direction <= transport '1';
		-- --------------------
		WAIT FOR 200 ns; -- Time=400 ns
		cs_reg_direction <= transport '0';
		cs_reg_it_mask <= transport '1';
		bus_data <= transport std_logic_vector'("11111000"); --F8
		-- --------------------
		WAIT FOR 200 ns; -- Time=600 ns
		cs_reg_it_mask <= transport '0';
		cs_reg_data <= transport '1';
		bus_data <= transport std_logic_vector'("00000001"); --1
		-- --------------------
		WAIT FOR 200 ns; -- Time=800 ns
		rw <= transport '1';
		cs_reg_it_mask <= transport '1';
		cs_reg_data <= transport '0';
		bus_data <= transport std_logic_vector'("ZZZZZZZZ"); --Z
		-- --------------------
		WAIT FOR 200 ns; -- Time=1000 ns
		cs_reg_it_mask <= transport '0';
		io_output <= transport std_logic_vector'("00100ZZZ"); --2?
		-- --------------------
		WAIT FOR 200 ns; -- Time=1200 ns
		cs_reg_direction <= transport '1';
		-- --------------------
		WAIT FOR 200 ns; -- Time=1400 ns
		cs_reg_direction <= transport '0';
		-- --------------------
		WAIT FOR 200 ns; -- Time=1600 ns
		cs_reg_data <= transport '1';
		-- --------------------
		WAIT FOR 200 ns; -- Time=1800 ns
		cs_reg_data <= transport '0';
		-- --------------------
		WAIT FOR 200 ns; -- Time=2000 ns
		cs_read_output <= transport '1';
		-- --------------------
		WAIT FOR 200 ns; -- Time=2200 ns
		cs_read_output <= transport '0';
		-- --------------------
		WAIT FOR 320 ns; -- Time=2520 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
	PROCESS   -- Process for clk_m
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_interrupt(
			next_interrupt : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (interrupt /= next_interrupt) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns interrupt="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, interrupt);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_interrupt);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		-- --------------------
		WAIT FOR 2510 ns; -- Time=2510 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION gpio_cfg OF gpio_tbw IS
	FOR testbench_arch
	END FOR;
END gpio_cfg;