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Diffstat (limited to '2004/n/fpga/src/gpio/ISE_bch/gpio_it_detect_tbw.tbw')
-rw-r--r--2004/n/fpga/src/gpio/ISE_bch/gpio_it_detect_tbw.tbw44
1 files changed, 44 insertions, 0 deletions
diff --git a/2004/n/fpga/src/gpio/ISE_bch/gpio_it_detect_tbw.tbw b/2004/n/fpga/src/gpio/ISE_bch/gpio_it_detect_tbw.tbw
new file mode 100644
index 0000000..7e61c83
--- /dev/null
+++ b/2004/n/fpga/src/gpio/ISE_bch/gpio_it_detect_tbw.tbw
@@ -0,0 +1,44 @@
+info x 36 510 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VHDL
+col x 257 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+radix x 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+entity name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gpio_it_detect
+term mark 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+vlib save 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 library ieee;
+use ieee.std_logic_1164.all;
+library work;
+use work.isa_const.all;
+use work.nono_const.all;
+
+var add 1 0 0 226 26 0 257 100 50 50 10 10 0 0 0 0 clkInstd_logicDUAL_EDGEclk
+var add 2 0 0 98 27 0 257 50 25 25 10 10 0 0 0 0 rstInstd_logicDUAL_EDGEclk
+var add 3 7 0 100 28 0 257 50 25 25 10 10 0 0 0 0 data_inInstd_logic_vectorDUAL_EDGEclk
+var add 4 7 0 100 29 0 257 50 25 25 10 10 0 0 0 0 it_maskInstd_logic_vectorDUAL_EDGEclk
+var add 5 0 0 98 30 0 257 50 25 25 10 10 0 0 0 0 it_detectedOutstd_logicDUAL_EDGEclk
+vdone xxx 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+npos xxx 114 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+cell fill 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
+cell fill 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 2 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 2 44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
+cell fill 2 48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+cell fill 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000010
+cell fill 3 28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00001000
+cell fill 3 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000001
+cell fill 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000010
+cell fill 4 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000010
+cell fill 4 28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000001
+time info 50 50 10 10 50 50 1 1 0 0 0 0 0 0 0 0 nsclk
+font save -14 0 400 49 0 0 0 0 0 0 0 0 0 0 0 0 Times New Roman
+src mod 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f:\cours\i2\electronique\vhdl\projet\carte_fpga\src\gpio\gpio_it_detect.vhd
+utd false 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+cellenab on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+grid on 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+com add 1 0 10 523 7 0 -79 0 0 0 0 0 0 0 0 0 Waveform created by
+HDL Bencher 6.1i
+Source = f:\cours\i2\electronique\vhdl\projet\carte_fpga\src\gpio\gpio_it_detect.vhd
+Wed Mar 17 10:57:35 2004
+type info 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clkBITDOWNTO
+opt vhdl87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+NumClocks x 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
+clock_1 name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clk
+Zoom_level x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0.66666666666667