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path: root/2004/n/fpga/src/gpio/ISE_bch/gpio_direction_tbw.vhd
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-- F:\COURS\I2\ELECTRONIQUE\VHDL\PROJET\CARTE_FPGA\GPIO
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Wed Mar 17 10:54:56 2004
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY WORK;
USE WORK.ISA_CONST.ALL;
USE WORK.NONO_CONST.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY gpio_direction_tbw IS
END gpio_direction_tbw;

ARCHITECTURE testbench_arch OF gpio_direction_tbw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT gpio_direction
		PORT (
			direction_mask : In  std_logic_vector (7 DOWNTO 0);
			data_in : In  std_logic_vector (7 DOWNTO 0);
			data_out : Out  std_logic_vector (7 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL direction_mask : std_logic_vector (7 DOWNTO 0);
	SIGNAL data_in : std_logic_vector (7 DOWNTO 0);
	SIGNAL data_out : std_logic_vector (7 DOWNTO 0);

BEGIN
	UUT : gpio_direction
	PORT MAP (
		direction_mask => direction_mask,
		data_in => data_in,
		data_out => data_out
	);

	PROCESS
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_data_out(
			next_data_out : std_logic_vector (7 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (data_out /= next_data_out) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns data_out="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, data_out);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_data_out);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		direction_mask <= transport std_logic_vector'("00000100"); --4
		data_in <= transport std_logic_vector'("00000001"); --1
		-- --------------------
		WAIT FOR 200 ns; -- Time=200 ns
		data_in <= transport std_logic_vector'("00000010"); --2
		-- --------------------
		WAIT FOR 200 ns; -- Time=400 ns
		data_in <= transport std_logic_vector'("00000111"); --7
		-- --------------------
		WAIT FOR 200 ns; -- Time=600 ns
		direction_mask <= transport std_logic_vector'("00000111"); --7
		-- --------------------
		WAIT FOR 300 ns; -- Time=900 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION gpio_direction_cfg OF gpio_direction_tbw IS
	FOR testbench_arch
	END FOR;
END gpio_direction_cfg;