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authorprot2004-02-24 21:08:51 +0000
committerprot2004-02-24 21:08:51 +0000
commitf8ee5b24be92c6709781e17c6f8ff358f5986558 (patch)
treeefe560a4f0e7f93da82dc6b00fb808b8c2680f5e /2004/n
parentcadaee918c25d2d5dcdc37410594fdb67635326f (diff)
Testbench ajouté
Diffstat (limited to '2004/n')
-rw-r--r--2004/n/fpga/src/portserie/bch_txserie.vhd86
-rw-r--r--2004/n/fpga/src/portserie/decoder.vhd3
-rw-r--r--2004/n/fpga/src/portserie/fifo.vhd3
-rw-r--r--2004/n/fpga/src/portserie/portserie.sws16
-rw-r--r--2004/n/fpga/src/portserie/txserie.vhd36
5 files changed, 116 insertions, 28 deletions
diff --git a/2004/n/fpga/src/portserie/bch_txserie.vhd b/2004/n/fpga/src/portserie/bch_txserie.vhd
new file mode 100644
index 0000000..42c9f9b
--- /dev/null
+++ b/2004/n/fpga/src/portserie/bch_txserie.vhd
@@ -0,0 +1,86 @@
+-- modele.vhd
+-- Eurobot 2004 : APB Team
+-- Auteur : Pierre-André Galmes
+-- Fichier modèle pour la déclaration de module.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+use work.nono_const.all;
+
+
+entity bch_txserie is
+end bch_txserie;
+
+architecture sim1 of bch_txserie is
+
+ component txserie
+ generic (
+ -- adresses des différents registres du module.
+ A_DATA : T_ADDRESS ;
+ A_CONFIG : T_ADDRESS ;
+ A_FLAG : T_ADDRESS
+ -- si autre choses à déclarer...
+ );
+ port (
+ rst : in std_logic;
+ clk : in std_logic;
+ rw : in std_logic; -- read (0) / write (1)
+ bus_data : inout T_DATA;
+ bus_address : in T_ADDRESS;
+ masterck: in std_logic;
+ txout: out std_logic;
+ minIRQ: out std_logic
+ );
+ end component;
+
+
+-- définiton des signaux
+signal rst : std_logic;
+signal clk : std_logic := '0';
+signal rw : std_logic; -- read / write
+signal bus_data : T_DATA:="00000000";
+signal bus_address : T_ADDRESS;
+signal masterck: std_logic:='0';
+signal txout: std_logic;
+signal minIRQ: std_logic;
+
+begin
+ U1 : txserie
+ generic map (
+ -- Définition des addresses.
+ A_DATA => "0000000011",
+ A_CONFIG => "0000000100",
+ A_FLAG => "0000000010"
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ rw => rw,
+ bus_data => bus_data,
+ bus_address => bus_address,
+ masterck=> masterck,
+ txout=> txout,
+ minIRQ=> minIRQ
+ );
+
+ rst <= '1', '0' after CK_PERIOD;
+ clk <= not clk after (CK_PERIOD/2);
+ rw <= '0';
+ bus_address <= "0000000011",
+ "0000000100" after 3*CK_PERIOD,
+ "0000000010" after 5*CK_PERIOD;
+ bus_data <= bus_data + 1 after 10 ns;
+ masterck<= not masterck after (CK_PERIOD/3);
+end sim1;
+
+
+configuration cf1_bch_txserie of bch_txserie is
+ for sim1
+ for all : txserie use entity work.txserie(rtl); end for;
+ end for;
+end cf1_bch_txserie;
+
+
diff --git a/2004/n/fpga/src/portserie/decoder.vhd b/2004/n/fpga/src/portserie/decoder.vhd
index 219f308..8ca3a67 100644
--- a/2004/n/fpga/src/portserie/decoder.vhd
+++ b/2004/n/fpga/src/portserie/decoder.vhd
@@ -13,7 +13,7 @@ use work.nono_const.all;
entity decoder is
generic(adr : T_ADDRESS);
port(
- bus_address : in T_ADDRESS
+ bus_address : in T_ADDRESS;
cs: out std_logic
);
end decoder;
@@ -31,3 +31,4 @@ begin
end process;
end rtl;
+
diff --git a/2004/n/fpga/src/portserie/fifo.vhd b/2004/n/fpga/src/portserie/fifo.vhd
index 79303f4..925dbf0 100644
--- a/2004/n/fpga/src/portserie/fifo.vhd
+++ b/2004/n/fpga/src/portserie/fifo.vhd
@@ -14,7 +14,7 @@ use work.nono_const.all;
entity fifo is
port(
data_in: in T_DATA;
- data_out: out T_ADDRESS;
+ data_out: out T_DATA;
ck: in std_logic;
ck_in: in std_logic;
ck_out: in std_logic;
@@ -100,3 +100,4 @@ end rtl;
+
diff --git a/2004/n/fpga/src/portserie/portserie.sws b/2004/n/fpga/src/portserie/portserie.sws
index 3b951b0..8762f0d 100644
--- a/2004/n/fpga/src/portserie/portserie.sws
+++ b/2004/n/fpga/src/portserie/portserie.sws
@@ -96,6 +96,7 @@
# Begin description of library portserie
[library]
name = portserie
+ toplevel = bch_txserie
[options]
[booloption]
name = -87
@@ -128,17 +129,17 @@
[]
[]
[file]
- name = ../registre/registre.vhd
+ name = ../modele/isa_const.vhd
[options]
[]
[]
[file]
- name = clockgene.vhd
+ name = ../modele/nono_const.vhd
[options]
[]
[]
[file]
- name = decoder.vhd
+ name = ../registre/registre.vhd
[options]
[]
[]
@@ -158,12 +159,12 @@
[]
[]
[file]
- name = isa_const.vhd
+ name = decoder.vhd
[options]
[]
[]
[file]
- name = nono_const.vhd
+ name = clockgene.vhd
[options]
[]
[]
@@ -172,6 +173,11 @@
[options]
[]
[]
+ [file]
+ name = bch_txserie.vhd
+ [options]
+ []
+ []
[]
# End description of library portserie
# Begin various workspace properties
diff --git a/2004/n/fpga/src/portserie/txserie.vhd b/2004/n/fpga/src/portserie/txserie.vhd
index 997a60d..3b483b9 100644
--- a/2004/n/fpga/src/portserie/txserie.vhd
+++ b/2004/n/fpga/src/portserie/txserie.vhd
@@ -49,8 +49,7 @@ entity txserie is
clk : in std_logic;
rw : in std_logic; -- read (0) / write (1)
bus_data : inout T_DATA;
- bus_address : in T_ADDRESS
-
+ bus_address : in T_ADDRESS;
masterck: in std_logic;
txout: out std_logic;
minIRQ: out std_logic
@@ -59,7 +58,7 @@ end txserie;
architecture rtl of txserie is
-component registre
+component regIO
generic(adr : T_ADDRESS);
port(
bus_address: in T_ADDRESS;
@@ -105,7 +104,7 @@ component clockgene
end component;
component decoder
- generic(adr : unsigned);
+ generic(adr : T_ADDRESS);
port(
bus_address: in T_DATA;
cs: out std_logic
@@ -113,12 +112,12 @@ component decoder
end component;
-signal fifoEmpty: std_logic;
-signal fifoFull: std_logic;
-signal fifoLI1: std_logic;
-signal fifoLI0: std_logic;
-signal BdR1: std_logic;
-signal BdR0: std_logic;
+--signal fifoEmpty: std_logic;
+--signal fifoFull: std_logic;
+--signal fifoLI1: std_logic;
+--signal fifoLI0: std_logic;
+--signal BdR1: std_logic;
+--signal BdR0: std_logic;
signal purge: std_logic;
signal geneck: std_logic;
signal txck: std_logic;
@@ -166,11 +165,11 @@ CLOCK1 : clockgene
param=>"11" --confreg(1 downto 0)
);
-geneck<='1'; --confreg(4) and masterck; -- On/Off et masterck
+--geneck<='1'; --confreg(4) and masterck; -- On/Off et masterck
-- Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0)
-RCONF : registre
+RCONF : regIO
generic map(adr=>A_DATA)
port map(
bus_address=>bus_address,
@@ -183,8 +182,8 @@ RCONF : registre
rst=>'0'
);
--- Flag : (x ! x ! x ! x ! Empty ! Full/Int ! FLI1 ! FLI0)
-RFLAG : registre
+-- Flag : (x ! x ! Empty ! Full/Int ! FLI3 ! FLI2 ! FLI1 ! FLI0)
+RFLAG : regIO
generic map(adr=>A_FLAG)
port map(
bus_address=>bus_address,
@@ -197,15 +196,9 @@ RFLAG : registre
rst=>'0'
);
-flagreg(7 downto 3)<=(others => '0');
-flagreg(3)<=txempty;
-flagreg(2)<=fifoFull;
-flagreg(1)<=fifoLI1;
-flagreg(0)<=fifoLI0;
-
-- la sortie intout est active si la pile est pleine ET si le bit de conf est
-- activé
-minIRQ<=fifoFull and confreg(2); -- IntEn et fifoFull
+minIRQ<=flagreg(4) and confreg(2); -- IntEn et fifoFull
DECOD : decoder
generic map(adr=>A_DATA)
@@ -216,3 +209,4 @@ DECOD : decoder
end rtl;
+