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authorgalmes2004-03-12 15:37:15 +0000
committergalmes2004-03-12 15:37:15 +0000
commit0633b192515a68393c0adec67b9c79d7d0de6988 (patch)
tree2e3ce9e43965f3b998f92d1794a92c055e1120b8 /2004/n
parent6c1e42f741e1b0d599cb5a9c96165ce4e8d10422 (diff)
- Dans les fichiers .vhd : Changement d'un nom cs_reg_read_output en
cs_read_output. - Ajout du fig de l'architecture physique pour les gpio
Diffstat (limited to '2004/n')
-rw-r--r--2004/n/fpga/doc/dcd/gpio/images/archi_phy.fig289
-rw-r--r--2004/n/fpga/src/gpio/bch_gpio.vhd30
-rw-r--r--2004/n/fpga/src/gpio/gpio.vhd8
-rw-r--r--2004/n/fpga/src/gpio/gpio_it_detect.vhd2
-rw-r--r--2004/n/fpga/src/packages/isa_const.vhd4
5 files changed, 311 insertions, 22 deletions
diff --git a/2004/n/fpga/doc/dcd/gpio/images/archi_phy.fig b/2004/n/fpga/doc/dcd/gpio/images/archi_phy.fig
new file mode 100644
index 0000000..4021fa9
--- /dev/null
+++ b/2004/n/fpga/doc/dcd/gpio/images/archi_phy.fig
@@ -0,0 +1,289 @@
+#FIG 3.2 Produced by xfig version 3.2.5-alpha4
+Landscape
+Center
+Metric
+A4
+100.00
+Single
+-2
+1200 2
+6 5850 1800 7650 2925
+6 6075 2025 7425 2700
+4 1 0 50 -1 0 12 0.0000 4 135 1035 6750 2250 Gestionnaire\001
+4 1 0 50 -1 0 12 0.0000 4 150 1050 6750 2505 de directions\001
+-6
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+ 5850 1800 7650 1800 7650 2925 5850 2925 5850 1800
+-6
+6 2250 3825 4050 6750
+6 2250 5850 3150 6750
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 1 2
+ 1 1 1.00 60.00 120.00
+ 2700 5850 2700 6300
+4 1 0 50 -1 0 12 0.0000 4 180 660 2700 6525 clk_ISA\001
+-6
+6 2250 3825 4050 6525
+6 3375 5850 3825 6525
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 1 2
+ 1 1 1.00 60.00 120.00
+ 3600 5850 3600 6300
+4 1 0 50 -1 0 12 0.0000 4 135 270 3600 6525 Rst\001
+-6
+6 2475 4050 2925 4725
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 1.00 60.00 120.00
+ 2700 4275 2700 4725
+4 1 0 50 -1 0 12 0.0000 4 135 315 2700 4275 RW\001
+-6
+6 2250 4725 4050 5850
+6 2475 4950 3825 5625
+4 1 0 50 -1 0 12 0.0000 4 180 720 3150 5175 Registre \001
+4 1 0 50 -1 0 12 0.0000 4 180 1185 3150 5400 d'interruptions\001
+-6
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+ 2250 4725 4050 4725 4050 5850 2250 5850 2250 4725
+-6
+6 3150 3825 4050 4725
+6 3150 3825 4050 4500
+4 1 0 50 -1 0 12 0.0000 4 180 645 3600 4275 it_mask\001
+4 1 0 50 -1 0 12 0.0000 4 150 525 3600 4050 cs_reg\001
+-6
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 1.00 60.00 120.00
+ 3600 4275 3600 4725
+-6
+-6
+-6
+6 2250 900 4050 3825
+6 3375 2925 3825 3600
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 1 2
+ 1 1 1.00 60.00 120.00
+ 3600 2925 3600 3375
+4 1 0 50 -1 0 12 0.0000 4 135 270 3600 3600 Rst\001
+-6
+6 2475 1125 2925 1800
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 1.00 60.00 120.00
+ 2700 1350 2700 1800
+4 1 0 50 -1 0 12 0.0000 4 135 315 2700 1350 RW\001
+-6
+6 3150 900 4050 1800
+6 3150 900 4050 1350
+4 1 0 50 -1 0 12 0.0000 4 135 345 3600 1350 data\001
+4 1 0 50 -1 0 12 0.0000 4 150 525 3600 1125 cs_reg\001
+-6
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 1.00 60.00 120.00
+ 3600 1350 3600 1800
+-6
+6 2250 1800 4050 2925
+6 2475 2025 3825 2475
+4 1 0 50 -1 0 12 0.0000 4 180 915 3150 2250 Registre de\001
+4 1 0 50 -1 0 12 0.0000 4 135 705 3150 2475 Donn\351es\001
+-6
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+ 2250 1800 4050 1800 4050 2925 2250 2925 2250 1800
+-6
+6 2250 2925 3150 3825
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 1 2
+ 1 1 1.00 60.00 120.00
+ 2700 2925 2700 3375
+4 1 0 50 -1 0 12 0.0000 4 180 660 2700 3600 clk_ISA\001
+-6
+-6
+6 2250 -2025 4050 900
+6 3375 0 3825 675
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 1 2
+ 1 1 1.00 60.00 120.00
+ 3600 0 3600 450
+4 1 0 50 -1 0 12 0.0000 4 135 270 3600 675 Rst\001
+-6
+6 3150 -2025 4050 -1125
+6 3150 -2025 4050 -1575
+4 1 0 50 -1 0 12 0.0000 4 135 735 3600 -1575 direction\001
+4 1 0 50 -1 0 12 0.0000 4 150 525 3600 -1800 cs_reg\001
+-6
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 1.00 60.00 120.00
+ 3600 -1575 3600 -1125
+-6
+6 2475 -1800 2925 -1125
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 1.00 60.00 120.00
+ 2700 -1575 2700 -1125
+4 1 0 50 -1 0 12 0.0000 4 135 315 2700 -1575 RW\001
+-6
+6 2250 -1125 4050 0
+6 2475 -900 3825 -225
+4 1 0 50 -1 0 12 0.0000 4 180 915 3150 -675 Registre de\001
+4 1 0 50 -1 0 12 0.0000 4 135 765 3150 -420 Direction\001
+-6
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+ 2250 -1125 4050 -1125 4050 0 2250 0 2250 -1125
+-6
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 1 2
+ 1 1 1.00 60.00 120.00
+ 2700 0 2700 450
+4 1 0 50 -1 0 12 0.0000 4 180 660 2700 675 clk_ISA\001
+-6
+6 -675 4725 675 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 1 2
+ 2 1 1.00 60.00 120.00
+ 675 4950 -225 4950
+4 2 0 50 -1 0 12 0.0000 4 180 975 450 5175 cs_reg_data\001
+-6
+6 -675 6525 6750 7200
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 2 1 1.00 60.00 120.00
+ 6750 6750 -450 6750
+4 2 0 50 -1 0 12 0.0000 4 180 975 450 6975 Interruption\001
+-6
+6 -900 5625 675 6300
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 1 2
+ 2 1 1.00 60.00 120.00
+ 675 5850 -225 5850
+4 2 0 50 -1 0 12 0.0000 4 195 1275 450 6075 cs_reg_it_mask\001
+-6
+6 -900 2925 675 3600
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 1 2
+ 2 1 1.00 60.00 120.00
+ 675 3150 -225 3150
+4 2 0 50 -1 0 12 0.0000 4 180 1260 450 3375 cs_read_output\001
+-6
+6 -1125 3825 675 4500
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 1 2
+ 2 1 1.00 60.00 120.00
+ 675 4050 -225 4050
+4 2 0 50 -1 0 12 0.0000 4 180 1365 450 4275 cs_reg_direction\001
+-6
+6 -675 2025 900 2700
+2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 1 1 2
+ 2 1 2.00 75.00 120.00
+ 2 1 2.00 75.00 120.00
+ 675 2250 -225 2250
+4 2 0 50 -1 0 12 0.0000 4 180 1005 450 2475 Data Bus (8)\001
+-6
+6 -450 1125 675 1800
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 1 2
+ 2 1 1.00 60.00 120.00
+ 675 1350 -225 1350
+4 2 0 50 -1 0 12 0.0000 4 180 885 450 1575 clk_master\001
+-6
+6 -225 225 675 900
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 1 2
+ 2 1 1.00 60.00 120.00
+ 675 450 -225 450
+4 2 0 50 -1 0 12 0.0000 4 180 585 450 675 clk_isa\001
+-6
+6 -225 -675 675 -225
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 1 2
+ 2 1 1.00 60.00 120.00
+ 675 -450 -225 -450
+4 2 0 50 -1 0 12 0.0000 4 135 315 450 -225 RW\001
+-6
+6 -225 -1575 675 -1125
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 1 2
+ 2 1 1.00 60.00 120.00
+ 675 -1350 -225 -1350
+4 2 0 50 -1 0 12 0.0000 4 135 270 450 -1125 Rst\001
+-6
+6 4050 5175 5850 5850
+4 1 0 50 -1 0 12 0.0000 4 150 615 4950 5400 masque\001
+4 1 0 50 -1 0 12 0.0000 4 180 1380 4950 5625 d'interruption (8)\001
+-6
+6 3825 2025 6075 2475
+2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 2 1 2.00 75.00 120.00
+ 4050 2250 5850 2250
+4 2 0 50 -1 0 12 0.0000 4 135 105 4950 2475 8\001
+-6
+6 5850 -2025 7650 0
+6 5850 -1125 7650 0
+6 6300 -900 7200 -225
+4 1 0 50 -1 0 12 0.0000 4 165 885 6750 -675 Bloc haute\001
+4 1 0 50 -1 0 12 0.0000 4 180 885 6750 -420 imp\351dance\001
+-6
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+ 5850 -1125 7650 -1125 7650 0 5850 0 5850 -1125
+-6
+6 6300 -2025 7200 -1125
+6 6300 -2025 7200 -1350
+4 1 0 50 -1 0 12 0.0000 4 165 615 6750 -1800 cs_read\001
+4 1 0 50 -1 0 12 0.0000 4 165 540 6750 -1545 output\001
+-6
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 1.00 60.00 120.00
+ 6750 -1575 6750 -1125
+-6
+-6
+6 8775 1575 10125 2475
+6 9225 1575 10125 2250
+4 0 0 50 -1 0 12 0.0000 4 180 435 9225 1800 Input\001
+4 0 0 50 -1 0 12 0.0000 4 180 840 9225 2055 Output (8)\001
+-6
+2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 1 1 2
+ 2 1 2.00 75.00 120.00
+ 2 1 2.00 75.00 120.00
+ 9000 2250 9900 2250
+-6
+6 5850 4050 7650 5850
+6 5850 4725 7650 5850
+6 6075 4950 7425 5625
+4 1 0 50 -1 0 12 0.0000 4 135 1035 6750 5175 Gestionnaire\001
+4 1 0 50 -1 0 12 0.0000 4 180 1185 6750 5400 d'interruptions\001
+-6
+2 2 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+ 5850 4725 7650 4725 7650 5850 5850 5850 5850 4725
+-6
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 6300 4725 6300 4275
+4 1 0 50 -1 0 12 0.0000 4 180 885 6300 4275 clk_master\001
+-6
+2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 2 1 2.00 75.00 120.00
+ 4050 5175 5850 5175
+2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 1 0 5
+ 2 1 2.00 75.00 120.00
+ 4050 -675 4725 -675 4725 1350 6750 1350 6750 1800
+2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 1 1 2
+ 2 1 2.00 75.00 120.00
+ 2 1 2.00 75.00 120.00
+ 2250 2250 1350 2250
+2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 1350 -675 1350 5175
+2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+ 2 1 2.00 75.00 120.00
+ 8325 2250 8325 5175 7650 5175
+2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 0 1 2
+ 2 1 2.00 75.00 120.00
+ 5175 -675 5850 -675
+2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
+ 1350 -675 1350 -2250 5175 -2250 5175 -675
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 1.00 60.00 120.00
+ 6750 5850 6750 6750
+2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 8325 2250 9000 2250
+2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 2 1 2.00 75.00 120.00
+ 7650 2250 8325 2250
+2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+ 2 1 2.00 75.00 120.00
+ 8325 2250 8325 -675 7650 -675
+2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 1350 2250 675 2250
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 6
+ 675 -3150 9000 -3150 9000 6975 9000 7200 675 7200 675 -3150
+2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 1 1 2
+ 2 1 2.00 75.00 120.00
+ 2 1 2.00 75.00 120.00
+ 1350 -675 2250 -675
+2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 1 1 2
+ 2 1 2.00 75.00 120.00
+ 2 1 2.00 75.00 120.00
+ 2250 5175 1350 5175
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 7200 4725 7200 4275
+4 0 0 50 -1 0 16 0.0000 4 255 3240 1125 -2700 Genral Purpose Input Output\001
+4 2 0 50 -1 0 12 0.0000 4 180 1905 6750 1125 masque de direction (8)\001
+4 1 0 50 -1 0 12 0.0000 4 135 270 7200 4275 Rst\001
diff --git a/2004/n/fpga/src/gpio/bch_gpio.vhd b/2004/n/fpga/src/gpio/bch_gpio.vhd
index bf142e8..12939c8 100644
--- a/2004/n/fpga/src/gpio/bch_gpio.vhd
+++ b/2004/n/fpga/src/gpio/bch_gpio.vhd
@@ -29,10 +29,10 @@ architecture sim1 of bch_gpio is
bus_data : inout T_DATA;
io_output : inout T_DATA;
-- chip select
- cs_reg_data_write : in std_logic;
+ cs_reg_data : in std_logic;
cs_reg_direction : in std_logic;
cs_reg_it_mask : in std_logic;
- cs_reg_read_output : in std_logic
+ cs_read_output : in std_logic
);
end component;
@@ -45,10 +45,10 @@ architecture sim1 of bch_gpio is
signal bus_data : T_DATA := x"00";
signal io_output : T_DATA;
-- chip select
- signal cs_reg_data_write : std_logic := '0';
+ signal cs_reg_data : std_logic := '0';
signal cs_reg_direction : std_logic := '0';
signal cs_reg_it_mask : std_logic := '0';
- signal cs_reg_read_output : std_logic := '0';
+ signal cs_read_output : std_logic := '0';
constant REG_DATA : std_logic_vector(1 downto 0) := "00";
constant REG_DIRECTION : std_logic_vector(1 downto 0) := "01";
@@ -68,10 +68,10 @@ begin
interrupt => interrupt,
bus_data => bus_data,
io_output => io_output,
- cs_reg_read_output => cs_reg_read_output,
+ cs_read_output => cs_read_output,
cs_reg_it_mask => cs_reg_it_mask,
cs_reg_direction => cs_reg_direction,
- cs_reg_data_write => cs_reg_data_write
+ cs_reg_data => cs_reg_data
);
-- ---------------------------------
@@ -86,13 +86,13 @@ begin
procedure do_read (action : in std_logic_vector(1 downto 0)) is
begin
-- sélection du registre
- cs_reg_data_write <= '0';
+ cs_reg_data <= '0';
cs_reg_direction <= '0';
cs_reg_it_mask <= '0';
- cs_reg_read_output <= '0';
+ cs_read_output <= '0';
if (action = REG_DATA) then
- cs_reg_data_write <= '1';
+ cs_reg_data <= '1';
end if;
if (action = REG_DIRECTION) then
cs_reg_direction <= '1';
@@ -101,7 +101,7 @@ begin
cs_reg_it_mask <= '1';
end if;
if (action = READ_OUTPUT) then
- cs_reg_read_output <= '1';
+ cs_read_output <= '1';
end if;
-- on lit.
rw <= ISA_READ;
@@ -113,13 +113,13 @@ begin
T_DATA) is
begin
-- sélection du registre
- cs_reg_data_write <= '0';
+ cs_reg_data <= '0';
cs_reg_direction <= '0';
cs_reg_it_mask <= '0';
- cs_reg_read_output <= '0';
+ cs_read_output <= '0';
if (action = REG_DATA) then
- cs_reg_data_write <= '1';
+ cs_reg_data <= '1';
end if;
if (action = REG_DIRECTION) then
cs_reg_direction <= '1';
@@ -128,7 +128,7 @@ begin
cs_reg_it_mask <= '1';
end if;
if (action = READ_OUTPUT) then
- cs_reg_read_output <= '1';
+ cs_read_output <= '1';
end if;
-- On écrit.
rw <= ISA_WRITE;
@@ -152,7 +152,7 @@ begin
do_write (REG_IT, "11111000");
wait for (ISA_CK_PERIOD);
do_write (REG_DATA, x"01"); -- 3 bits poid faible : in.
--- cs_reg_data_write <= '0';
+-- cs_reg_data <= '0';
-- interruption sur les 5 bits de poid faible.
-- wait for (3*CK_PERIOD);
diff --git a/2004/n/fpga/src/gpio/gpio.vhd b/2004/n/fpga/src/gpio/gpio.vhd
index 88c1651..b85d5da 100644
--- a/2004/n/fpga/src/gpio/gpio.vhd
+++ b/2004/n/fpga/src/gpio/gpio.vhd
@@ -20,10 +20,10 @@ entity gpio is
bus_data : inout T_DATA;
io_output : inout T_DATA;
-- chip select
- cs_reg_data_write : in std_logic;
+ cs_reg_data : in std_logic;
cs_reg_direction : in std_logic;
cs_reg_it_mask : in std_logic;
- cs_reg_read_output : in std_logic
+ cs_read_output : in std_logic
);
end entity;
@@ -100,7 +100,7 @@ port map (
clk_i,
rst,
rw,
- cs_reg_data_write,
+ cs_reg_data,
bus_data,
bus_reg_data
);
@@ -119,7 +119,7 @@ port map (
--
read_output : tristate
port map (
- cs_reg_read_output,
+ cs_read_output,
io_output,
bus_data
);
diff --git a/2004/n/fpga/src/gpio/gpio_it_detect.vhd b/2004/n/fpga/src/gpio/gpio_it_detect.vhd
index 2e21970..003c00d 100644
--- a/2004/n/fpga/src/gpio/gpio_it_detect.vhd
+++ b/2004/n/fpga/src/gpio/gpio_it_detect.vhd
@@ -29,7 +29,7 @@ end entity;
architecture RTL of gpio_it_detect is
-- Constantes
- constant IT_ENABLE : std_logic := '1';
+ -- constant IT_ENABLE : std_logic := '1';
-- Signal interne
signal state_p : T_DATA; -- etat passe
diff --git a/2004/n/fpga/src/packages/isa_const.vhd b/2004/n/fpga/src/packages/isa_const.vhd
index 8db9836..88f558d 100644
--- a/2004/n/fpga/src/packages/isa_const.vhd
+++ b/2004/n/fpga/src/packages/isa_const.vhd
@@ -21,8 +21,8 @@ package isa_const is
constant ISA_CK_PERIOD : time := 50 ns;
-- Ligne RW : lecture et écriture
- constant ISA_READ : std_logic := '0';
- constant ISA_WRITE : std_logic := '1';
+ constant ISA_READ : std_logic := '1';
+ constant ISA_WRITE : std_logic := '0';
-- Comportement de la ligne IRQ.
constant IRQ_ON : std_logic := '0';