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authorCyril Jourdan2012-08-08 11:12:36 +0200
committerCyril Jourdan2012-09-20 09:42:56 +0200
commite701858bceda0cb76d58f947b0fe68cb6323c96e (patch)
tree3247cb17c4283a2ec88b30bb45997c225f22542f /common/include/asm/arch/ips
parent0b7839300e7022376c9237d2edab4e4f0ee5ec61 (diff)
{cleo/u-boot, common}: use common/include/asm/arch/ips, refs #3119
Diffstat (limited to 'common/include/asm/arch/ips')
-rw-r--r--common/include/asm/arch/ips/gic.h4
-rw-r--r--common/include/asm/arch/ips/gpio.h3
-rw-r--r--common/include/asm/arch/ips/hardware/bus_sys.h9
-rw-r--r--common/include/asm/arch/ips/hardware/dsp.h31
-rw-r--r--common/include/asm/arch/ips/hardware/ethernet_ctrl.h14
-rw-r--r--common/include/asm/arch/ips/hardware/gpdma.h1
-rw-r--r--common/include/asm/arch/ips/hardware/miu.h27
-rw-r--r--common/include/asm/arch/ips/hardware/mpeg_ts.h37
-rw-r--r--common/include/asm/arch/ips/hardware/pcm.h2
-rw-r--r--common/include/asm/arch/ips/hardware/pkg_maria_regbank.h21
-rw-r--r--common/include/asm/arch/ips/hardware/sdram.h4
-rw-r--r--common/include/asm/arch/ips/hardware/sys_apb.h1
-rw-r--r--common/include/asm/arch/ips/ips_access.h9
-rw-r--r--common/include/asm/arch/ips/regbank.h2
-rw-r--r--common/include/asm/arch/ips/spi.h2
-rw-r--r--common/include/asm/arch/ips/timer.h2
-rw-r--r--common/include/asm/arch/ips/wdt.h6
17 files changed, 170 insertions, 5 deletions
diff --git a/common/include/asm/arch/ips/gic.h b/common/include/asm/arch/ips/gic.h
index ed7474980d..5b2448b31a 100644
--- a/common/include/asm/arch/ips/gic.h
+++ b/common/include/asm/arch/ips/gic.h
@@ -22,6 +22,7 @@
#include <asm/arch/ips/ips_access.h>
+#ifndef __ASSEMBLY__
/** Virtual Address for gic */
#define IRQ_INTEN_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_INTEN_OFFSET)))
#define IRQ_INTMASK_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_INTMASK_OFFSET)))
@@ -70,6 +71,7 @@
#define IRQ_P29_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P29_OFFSET)))
#define IRQ_P30_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P30_OFFSET)))
#define IRQ_P31_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P31_OFFSET)))
-
#define IRQ_PRIO_ADDR_VA ((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P0_OFFSET))
+#endif /* __ASSEMBLY__ */
+
#endif /* __ASM_ARCH_IPS_GIC_H */
diff --git a/common/include/asm/arch/ips/gpio.h b/common/include/asm/arch/ips/gpio.h
index d821e8b9e5..ceecd3fc93 100644
--- a/common/include/asm/arch/ips/gpio.h
+++ b/common/include/asm/arch/ips/gpio.h
@@ -22,8 +22,8 @@
#include <asm/arch/ips/ips_access.h>
+#ifndef __ASSEMBLY__
/** Virtual Address for gpios */
-
#define GPIO_SWPORTA_DR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_GPIO_BASE) + GPIO_SWPORTA_DR_OFFSET)))
#define GPIO_SWPORTA_DDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_GPIO_BASE) + GPIO_SWPORTA_DDR_OFFSET)))
#define GPIO_SWPORTA_CTL_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_GPIO_BASE) + GPIO_SWPORTA_CTL_OFFSET)))
@@ -56,5 +56,6 @@
extern void spc300_init_gpio(void);
extern int gpio_write(int no, int value);
+#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_IPS_GPIO_H */
diff --git a/common/include/asm/arch/ips/hardware/bus_sys.h b/common/include/asm/arch/ips/hardware/bus_sys.h
index 8484aa0b96..0e48aacb99 100644
--- a/common/include/asm/arch/ips/hardware/bus_sys.h
+++ b/common/include/asm/arch/ips/hardware/bus_sys.h
@@ -44,7 +44,16 @@
#include "sdram.h"
#endif
+#if defined (CONFIG_CHIP_FEATURE_MIU_CTRL)
+#define MIU_REG_BASE (0xC8050000)
+#define MIU_ATOP_REG_BASE (0xC8060000)
+#include "miu.h"
+#endif
+
#define ETHERNET_CTRL_BASE (0xD0000000)
#include "ethernet_ctrl.h"
+#define DSP_BASE (0xA0000000)
+#include "dsp.h"
+
#endif /* __ASM_ARCH_IPS_HW_BUS_SYS_H */
diff --git a/common/include/asm/arch/ips/hardware/dsp.h b/common/include/asm/arch/ips/hardware/dsp.h
new file mode 100644
index 0000000000..f8040fb85d
--- /dev/null
+++ b/common/include/asm/arch/ips/hardware/dsp.h
@@ -0,0 +1,31 @@
+/*
+ * include/asm/arch/ips/hardware/dsp.h
+ *
+ * (C) Copyright 2008 SPiDCOM Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_IPS_HW_DSP_H
+#define __ASM_ARCH_IPS_HW_DSP_H
+
+#ifndef DSP_BASE
+ #error "DSP_BASE macro needs to be defined before including file dsp.h"
+#endif
+
+#define DSP_PRATIC_OFFSET (0x1000)
+#define DSP_PRATIC_BASE (DSP_BASE+DSP_PRATIC_OFFSET)
+#define DSP_PRATIC_STA_LOCAL_TIMER (DSP_PRATIC_BASE+0x10)
+
+#endif /* __ASM_ARCH_IPS_HW_DSP_H */
diff --git a/common/include/asm/arch/ips/hardware/ethernet_ctrl.h b/common/include/asm/arch/ips/hardware/ethernet_ctrl.h
index 88389cd888..6104614b97 100644
--- a/common/include/asm/arch/ips/hardware/ethernet_ctrl.h
+++ b/common/include/asm/arch/ips/hardware/ethernet_ctrl.h
@@ -37,6 +37,18 @@
#define Register1_RegisterResetValue 0x0
#define Register1_RegisterResetMask 0x0
+/* Register Register2 */
+/* MAC hash table high Filter */
+#define Register2 (GMAC_BaseAddress + 0x8)
+#define Register2_RegisterSize 32
+#define Register2_RegisterResetValue 0x0
+#define Register2_RegisterResetMask 0x0
+/* Register Register3 */
+/* MAC hash table low Filter */
+#define Register3 (GMAC_BaseAddress + 0xC)
+#define Register3_RegisterSize 32
+#define Register3_RegisterResetValue 0x0
+#define Register3_RegisterResetMask 0x0
/* Register Register4 */
/* GMII Address Register */
@@ -617,7 +629,7 @@
#define Register119_RegisterResetMask 0x0
-#define DMA_BaseAddress (ETHERNET_CTRL_BASE + 0x1000)
+#define DMA_BaseAddress (ETHERNET_CTRL_BASE + 0x1000)
/* Register Register0 */
/* Bus Mode Register */
diff --git a/common/include/asm/arch/ips/hardware/gpdma.h b/common/include/asm/arch/ips/hardware/gpdma.h
index 7c5ab26a6e..91d25b1c00 100644
--- a/common/include/asm/arch/ips/hardware/gpdma.h
+++ b/common/include/asm/arch/ips/hardware/gpdma.h
@@ -118,6 +118,7 @@
#define GPDMA_CTL0 (GPDMA_BASE+0x018)
#define GPDMA_CTL0h (GPDMA_BASE+0x018+4)
#define GPDMA_CFG0 (GPDMA_BASE+0x040)
+#define GPDMA_RawTfr (GPDMA_BASE+0x2c0)
#define GPDMA_MaskTfr (GPDMA_BASE+0x310)
#define GPDMA_MaskBlock (GPDMA_BASE+0x318)
#define GPDMA_ClearTfr (GPDMA_BASE+0x338)
diff --git a/common/include/asm/arch/ips/hardware/miu.h b/common/include/asm/arch/ips/hardware/miu.h
new file mode 100644
index 0000000000..7f0f4ce3cb
--- /dev/null
+++ b/common/include/asm/arch/ips/hardware/miu.h
@@ -0,0 +1,27 @@
+/*
+ * include/asm/arch/ips/hardware/miu.h
+ *
+ * (C) Copyright 2008 SPiDCOM Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_IPS_HW_MIU_H
+#define __ASM_ARCH_IPS_HW_MIU_H
+
+
+#define MIU_INIT_DONE_REG 0
+#define MIU_INIT_DONE_BIT 15
+
+#endif /* __ASM_ARCH_IPS_HW_MIU_H */
diff --git a/common/include/asm/arch/ips/hardware/mpeg_ts.h b/common/include/asm/arch/ips/hardware/mpeg_ts.h
new file mode 100644
index 0000000000..0199439c75
--- /dev/null
+++ b/common/include/asm/arch/ips/hardware/mpeg_ts.h
@@ -0,0 +1,37 @@
+/*
+ * include/asm/arch/ips/hardware/mpeg_ts.h
+ *
+ * (C) Copyright 2008 SPiDCOM Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_IPS_HW_MPEG_TS_H
+#define __ASM_ARCH_IPS_HW_MPEG_TS_H
+#ifndef MPEG_TS_BASE
+ #error "MPEG_TS_BASE macro needs to be defined before including file mpeg_ts.h"
+#endif
+
+
+#define MPEG_TS_CONFIG (MPEG_TS_BASE + 0x00)
+#define MPEG_TS_INTERRUPT (MPEG_TS_BASE + 0x04)
+#define MPEG_TS_MASK_INT (MPEG_TS_BASE + 0x08)
+#define MPEG_TS_DESC_POINTER (MPEG_TS_BASE + 0x0C)
+#define MPEG_TS_BUFF_DATA (MPEG_TS_BASE + 0x10)
+#define MPEG_TS_TS_STATUS (MPEG_TS_BASE + 0x14)
+#define MPEG_TS_NTB_DATE (MPEG_TS_BASE + 0x18)
+#define MPEG_TS_LOCAL_TIMER (MPEG_TS_BASE + 0x1C)
+#define MPEG_TS_TX_POOL_TIMER (MPEG_TS_BASE + 0x20)
+
+#endif /* __ASM_ARCH_IPS_HW_MPEG_TS_H */
diff --git a/common/include/asm/arch/ips/hardware/pcm.h b/common/include/asm/arch/ips/hardware/pcm.h
index 3fd15b3642..1eb8bb25e6 100644
--- a/common/include/asm/arch/ips/hardware/pcm.h
+++ b/common/include/asm/arch/ips/hardware/pcm.h
@@ -21,7 +21,7 @@
#define __ASM_ARCH_IPS_HW_PCM_H
/*
- * Register address SPI_Controller
+ * Register address of PCM Controller
*
* 2007-12-10
*/
diff --git a/common/include/asm/arch/ips/hardware/pkg_maria_regbank.h b/common/include/asm/arch/ips/hardware/pkg_maria_regbank.h
index e9420764b1..839f433c86 100644
--- a/common/include/asm/arch/ips/hardware/pkg_maria_regbank.h
+++ b/common/include/asm/arch/ips/hardware/pkg_maria_regbank.h
@@ -37,6 +37,7 @@
#define RB_ICM_PRIORITY_OFFSET (0x11c)
#define RB_LEON_ADD_START_OFFSET (0x120)
#define RB_LEON_TICK_CNT_OFFSET (0x124)
+#define RB_DSP_HLOCK_OFFSET (0x128)
#define RB_PIO_CONFIG_OFFSET (0x200)
#define RB_PIO_ENABLE_OFFSET (0x204)
#define RB_GPIO_0_CONFIG_OFFSET (0x208)
@@ -94,6 +95,7 @@
#define RB_CLK_DIV_STAT_MPG_INT_OFFSET (0x4CC)
#define RB_CLK_SEL_MPG_OFFSET (0x4D0)
#define RB_CLK_SEL_STAT_MPG_OFFSET (0x4D4)
+#define RB_CLK_POL_MPG_OFFSET (0x4D8)
#define RB_CLK_CMD_SPI_OFFSET (0x4E0)
#define RB_CLK_STAT_SPI_OFFSET (0x4E4)
#define RB_CLK_CMD_I2S_OFFSET (0x4F0)
@@ -104,6 +106,7 @@
#define RB_CLK_STAT_PCM_OFFSET (0x504)
#define RB_CLK_DIV_PCM_OFFSET (0x508)
#define RB_CLK_DIV_STAT_PCM_OFFSET (0x50C)
+#define RB_CLK_POL_PCM_OFFSET (0x510)
#define RB_CLK_DIV_T1_OFFSET (0x518)
#define RB_CLK_DIV_STAT_T1_OFFSET (0x51C)
#define RB_CLK_DIV_T2_OFFSET (0x528)
@@ -153,6 +156,8 @@
#define RB_RST_GROUP_OFFSET (0x708)
#define RB_RST_MODULE_OFFSET (0x70C)
#define RB_RST_GMASK_OFFSET (0x710)
+#define RB_DINI_UART_SELECT_OFFSET (0x900)
+#define RB_DINI_SPARE_1_OFFSET (0x904)
#define SLAVE_MARIA_REGBANK (0x8030)
#define RB_PACKAGE (MARIA_REGBANK_BASE+0x000)
@@ -172,6 +177,7 @@
#define RB_ICM_PRIORITY (MARIA_REGBANK_BASE+0x11c)
#define RB_LEON_ADD_START (MARIA_REGBANK_BASE+0x120)
#define RB_LEON_TICK_CNT (MARIA_REGBANK_BASE+0x124)
+#define RB_DSP_HLOCK (MARIA_REGBANK_BASE+0x128)
#define LEON_ADD_START_RESET (0x00011000)
#define LEON_TICK_CNT_RESET (0x1d4c)
#define RB_PIO_CONFIG (MARIA_REGBANK_BASE+0x200)
@@ -274,6 +280,7 @@
#define RB_CLK_SEL_STAT_MPG (MARIA_REGBANK_BASE+0x4D4)
#define CLK_SEL_MPG_INT (0x0)
#define CLK_SEL_MPG_EXT (0x1)
+#define RB_CLK_POL_MPG (MARIA_REGBANK_BASE+0x4D8)
#define RB_CLK_CMD_SPI (MARIA_REGBANK_BASE+0x4E0)
#define RB_CLK_STAT_SPI (MARIA_REGBANK_BASE+0x4E4)
#define RB_CLK_CMD_I2S (MARIA_REGBANK_BASE+0x4F0)
@@ -284,6 +291,7 @@
#define RB_CLK_STAT_PCM (MARIA_REGBANK_BASE+0x504)
#define RB_CLK_DIV_PCM (MARIA_REGBANK_BASE+0x508)
#define RB_CLK_DIV_STAT_PCM (MARIA_REGBANK_BASE+0x50C)
+#define RB_CLK_POL_PCM (MARIA_REGBANK_BASE+0x510)
#define RB_CLK_DIV_T1 (MARIA_REGBANK_BASE+0x518)
#define RB_CLK_DIV_STAT_T1 (MARIA_REGBANK_BASE+0x51C)
#define RB_CLK_DIV_T2 (MARIA_REGBANK_BASE+0x528)
@@ -314,6 +322,14 @@
#define RB_SPLL_EN (MARIA_REGBANK_BASE+0x594)
#define RB_SPLL_DEBUG (MARIA_REGBANK_BASE+0x598)
#define RB_SPLL_SSCGNRST (MARIA_REGBANK_BASE+0x59C)
+#define PLL_CMD_ON (0x0)
+#define PLL_CMD_OFF (0x1)
+#define PLL_CMD_BYPASS (0x1)
+#define PLL_CMD_PLL (0x0)
+#define PLL_IS_BYPASS (0x1)
+#define PLL_IS_PLL (0x2)
+#define PLL_LBWS_OFF (0x0)
+#define PLL_LBWS_ON (0x1)
#define RB_CLK_CMD_SDR (MARIA_REGBANK_BASE+0x5A0)
#define RB_CLK_STAT_SDR (MARIA_REGBANK_BASE+0x5A4)
#define RB_CLK_CMD_OUT25 (MARIA_REGBANK_BASE+0x5B0)
@@ -362,5 +378,10 @@
#define RB_RST_GMASK (MARIA_REGBANK_BASE+0x710)
#define RB_FCM3_UART_SELECT (MARIA_REGBANK_BASE+0x800)
#define RB_FCM3_AD_SPIEN (MARIA_REGBANK_BASE+0x804)
+#define RB_DINI_UART_SELECT (MARIA_REGBANK_BASE+0x900)
+#define RB_DINI_UART_SELECT_LEON (0x0)
+#define RB_DINI_UART_SELECT_ARM (0x1)
+#define RB_DINI_SPARE_1 (MARIA_REGBANK_BASE+0x904)
+#define RB_DINI_SPARE_1_ETH_RX_CLOCK_INVERT (0x800)
#endif /* __ASM_ARCH_IPS_HW_PKG_MARIA_REGBANK_H */
diff --git a/common/include/asm/arch/ips/hardware/sdram.h b/common/include/asm/arch/ips/hardware/sdram.h
index ed25de04b4..8634b42b28 100644
--- a/common/include/asm/arch/ips/hardware/sdram.h
+++ b/common/include/asm/arch/ips/hardware/sdram.h
@@ -33,21 +33,25 @@
/* Number of bank address bits */
#define SCONR_s_bank_addr_width_BitAddressOffset 3
#define SCONR_s_bank_addr_width_RegisterSize 2
+#define SCONR_s_bank_addr_width_RegisterMask (3<<SCONR_s_bank_addr_width_BitAddressOffset)
/* Register SCONR field s_row_addr_width */
/* Number of address bits for row address */
#define SCONR_s_row_addr_width_BitAddressOffset 5
#define SCONR_s_row_addr_width_RegisterSize 4
+#define SCONR_s_row_addr_width_RegisterMask (0x0f<<SCONR_s_row_addr_width_BitAddressOffset)
/* Register SCONR field s_col_addr_width */
/* Number of address bits for column address */
#define SCONR_s_col_addr_width_BitAddressOffset 9
#define SCONR_s_col_addr_width_RegisterSize 4
+#define SCONR_s_col_addr_width_RegisterMask (0x0f<<SCONR_s_col_addr_width_BitAddressOffset)
/* Register SCONR field s_data_width */
/* SDRAM data width */
#define SCONR_s_data_width_BitAddressOffset 13
#define SCONR_s_data_width_RegisterSize 2
+#define SCONR_s_data_width_RegisterMask (3<<SCONR_s_data_width_BitAddressOffset)
/* Register SCONR field s_sa */
/* Serial presence detect address bits */
diff --git a/common/include/asm/arch/ips/hardware/sys_apb.h b/common/include/asm/arch/ips/hardware/sys_apb.h
index b463299df2..883015d313 100644
--- a/common/include/asm/arch/ips/hardware/sys_apb.h
+++ b/common/include/asm/arch/ips/hardware/sys_apb.h
@@ -29,6 +29,7 @@
#include "i2s.h"
#define MPEG_TS_BASE (SYS_APB_BASE+0x010000)
+#include "mpeg_ts.h"
#define MAILBOXES_BASE (SYS_APB_BASE+0x030000)
diff --git a/common/include/asm/arch/ips/ips_access.h b/common/include/asm/arch/ips/ips_access.h
index 93ca010b86..efd7d31c67 100644
--- a/common/include/asm/arch/ips/ips_access.h
+++ b/common/include/asm/arch/ips/ips_access.h
@@ -22,6 +22,8 @@
#include <asm/arch/ips/hardware/bus_sys.h>
+#ifdef CONFIG_MMU
+
/* Where are in virtual memory the IO devices (timers, system controllers and so on) */
#define IO_BASE 0xF0000000 // VA of IO
#define IO_SIZE 0x0B000000 // How much?
@@ -29,4 +31,11 @@
/* Macro to get at IO space when running virtually */
#define IO_ADDRESS(x) (((x) >> 4) + IO_BASE)
+#else
+
+/* When there is no MMU, IO space and physical space are the same. */
+#define IO_ADDRESS(x) (x)
+
+#endif /* CONFIG_MMU */
+
#endif /* __ASM_ARCH_IPS_IPS_ACCESS_H */
diff --git a/common/include/asm/arch/ips/regbank.h b/common/include/asm/arch/ips/regbank.h
index ac3f26361c..0a4288eae2 100644
--- a/common/include/asm/arch/ips/regbank.h
+++ b/common/include/asm/arch/ips/regbank.h
@@ -22,6 +22,7 @@
#include <asm/arch/ips/ips_access.h>
+#ifndef __ASSEMBLY__
/** Virtual Address for regbank */
#define RB_PACKAGE_VA (*((volatile uint32_t *)(IO_ADDRESS(MARIA_REGBANK_BASE) + RB_PACKAGE_OFFSET)))
#define RB_SDRAM_RETURN_LAT_VA (*((volatile uint32_t *)(IO_ADDRESS(MARIA_REGBANK_BASE) + RB_SDRAM_RETURN_LAT_OFFSET)))
@@ -152,5 +153,6 @@
#define RB_RST_GROUP_VA (*((volatile uint32_t *)(IO_ADDRESS(MARIA_REGBANK_BASE) + RB_RST_GROUP_OFFSET)))
#define RB_RST_MODULE_VA (*((volatile uint32_t *)(IO_ADDRESS(MARIA_REGBANK_BASE) + RB_RST_MODULE_OFFSET)))
#define RB_RST_GMASK_VA (*((volatile uint32_t *)(IO_ADDRESS(MARIA_REGBANK_BASE) + RB_RST_GMASK_OFFSET)))
+#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_IPS_REGBANK_H */
diff --git a/common/include/asm/arch/ips/spi.h b/common/include/asm/arch/ips/spi.h
index df03cac0f6..a6e660e2ca 100644
--- a/common/include/asm/arch/ips/spi.h
+++ b/common/include/asm/arch/ips/spi.h
@@ -35,6 +35,7 @@
#define SPI_REG_MASK_OFFSET (SPI_REG_Mask - SPI_BASE)
#define SPI_REG_STATUS_OFFSET (SPI_REG_STATUS - SPI_BASE)
+#ifndef __ASSEMBLY__
/** Virtual Address for spi registers */
#define SPI_MASTER_SLAVE_VA (*((volatile uint32_t *)(IO_ADDRESS(SPI_BASE) + SPI_MASTER_SLAVE_OFFSET)))
#define SPI_CTRL_CFG_VA (*((volatile uint32_t *)(IO_ADDRESS(SPI_BASE) + SPI_CTRL_CFG_OFFSET)))
@@ -48,6 +49,7 @@
#define SPI_REG_IRQ_VA (*((volatile uint32_t *)(IO_ADDRESS(SPI_BASE) + SPI_REG_IRQ_OFFSET)))
#define SPI_REG_MASK_VA (*((volatile uint32_t *)(IO_ADDRESS(SPI_BASE) + SPI_REG_MASK_OFFSET)))
#define SPI_REG_STATUS_VA (*((volatile uint32_t *)(IO_ADDRESS(SPI_BASE) + SPI_REG_STATUS_OFFSET)))
+#endif /* __ASSEMBLY__ */
// Bitfields in MASTER_SLAVE
#define SPI_MODE_SHIFT 0
diff --git a/common/include/asm/arch/ips/timer.h b/common/include/asm/arch/ips/timer.h
index 7dc49aa0ca..084a9b74cd 100644
--- a/common/include/asm/arch/ips/timer.h
+++ b/common/include/asm/arch/ips/timer.h
@@ -22,6 +22,7 @@
#include <asm/arch/ips/ips_access.h>
+#ifndef __ASSEMBLY__
/** Virtual Address for timer 1 */
#define TIMER1BASE_1_VA (IO_ADDRESS(ARM_TIMER1_BASE) + 0x00)
#define TIMER2BASE_1_VA (IO_ADDRESS(ARM_TIMER1_BASE) + 0x14)
@@ -89,6 +90,7 @@
#define TIMERSEOI_2_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_TIMER2_BASE) + TIMERSEOIOFF_2)))
#define TIMERSINTSTAT_2_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_TIMER2_BASE) + TIMERSINTSTATOFF_2)))
#define TIMERSRAWINTSTAT_2_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_TIMER2_BASE) + TIMERSRAWINTSTATOFF_2)))
+#endif /* __ASSEMBLY__ */
#define TIMER_ENABLE_MASK (1<<0)
#define TIMER_MODE_MASK (1<<1)
diff --git a/common/include/asm/arch/ips/wdt.h b/common/include/asm/arch/ips/wdt.h
index 6e4c1c1bfc..d3eb59bd57 100644
--- a/common/include/asm/arch/ips/wdt.h
+++ b/common/include/asm/arch/ips/wdt.h
@@ -22,8 +22,8 @@
#include <asm/arch/ips/ips_access.h>
+#ifndef __ASSEMBLY__
/** Virtual Address for watchdog timer */
-
#define WDT_CR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_WDT_BASE) + WDTControlReg_Offset)))
#define WDT_TORR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_WDT_BASE) + WDTTimeoutRangeReg_Offset)))
#define WDT_CCVR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_WDT_BASE) + WDTCurrentCounterValueReg_Offset)))
@@ -40,6 +40,7 @@
#define WDT_COMP_TYPE_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_WDT_BASE) + WDTCOMP_TYPE_Offset)))
#define WDT_CRR_PA (*((volatile uint32_t *)(ARM_WDT_BASE + WDTCounterResetReg_Offset)))
+#endif /* __ASSEMBLY__ */
// Bitfields in Control Register
#define WDT_EN_SHIFT 0
@@ -83,4 +84,7 @@
( ((old) & ~(((1 << WDT_##name##_SIZE) - 1) << WDT_##name##_SHIFT)) \
| WDT_BF(name,value))
+#define WDT_DEFAULT_TIME 5 //seconds
+#define WDT_MAX_TIME 21 //seconds
+
#endif /* __ASM_ARCH_IPS_WDT_H */