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-rw-r--r--2004/n/fpga/src/portserie/portserie/bch_txserie.vhd54
-rw-r--r--2004/n/fpga/src/portserie/portserie/txserie.vhd11
-rw-r--r--2004/n/fpga/src/portserie/rxserie/rxserie.vhd2
3 files changed, 37 insertions, 30 deletions
diff --git a/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd b/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd
index 25fadff..0014d05 100644
--- a/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd
+++ b/2004/n/fpga/src/portserie/portserie/bch_txserie.vhd
@@ -73,7 +73,7 @@ begin
combi:process(state)
begin
- clk <= '0';
+ clk <= '1';
rw <= '0';
bus_data <= (others => 'Z');
csData <= '0';
@@ -87,14 +87,14 @@ begin
when 2 => bus_data<="01110111";
csConfig<='1';
rw<='0';
- clk<='1';
+ clk<='0';
when 4 => bus_data<="00010110";
csData<='1';
rw<='0';
when 5 => bus_data<="00010110";
csData<='1';
rw<='0';
- clk<='1';
+ clk<='0';
when 70 => bus_data<="00010110";
csData<='1';
@@ -102,14 +102,14 @@ begin
when 71 => bus_data<="00010110";
csData<='1';
rw<='0';
- clk<='1';
+ clk<='0';
when 12 => csFlag<='1';
rw<='1';
when 13 =>
csFlag<='1';
rw<='1';
- clk<='1';
+ clk<='0';
when 20 => bus_data<="01010101";
@@ -118,7 +118,7 @@ begin
when 21 => bus_data<="01010101";
csData<='1';
rw<='0';
- clk<='1';
+ clk<='0';
when 1004 => bus_data<="00010110";
csData<='1';
@@ -126,7 +126,7 @@ begin
when 1005 => bus_data<="00010110";
csData<='1';
rw<='0';
- clk<='1';
+ clk<='0';
--
when 1007 => bus_data<="01010110";
csData<='1';
@@ -134,7 +134,7 @@ begin
when 1008 => bus_data<="01010110";
csData<='1';
rw<='0';
- clk<='1';
+ clk<='0';
--
when 1010 => bus_data<="01010110";
csData<='1';
@@ -142,7 +142,7 @@ begin
when 1011 => bus_data<="01010110";
csData<='1';
rw<='0';
- clk<='1';
+ clk<='0';
--
when 1013 => bus_data<="01010110";
csData<='1';
@@ -150,7 +150,7 @@ begin
when 1014 => bus_data<="01010110";
csData<='1';
rw<='0';
- clk<='1';
+ clk<='0';
--
when 1016 => bus_data<="01010110";
csData<='1';
@@ -158,7 +158,7 @@ begin
when 1017 => bus_data<="01010110";
csData<='1';
rw<='0';
- clk<='1';
+ clk<='0';
--
when 1019 => bus_data<="01010110";
csData<='1';
@@ -166,7 +166,7 @@ begin
when 1020 => bus_data<="01010110";
csData<='1';
rw<='0';
- clk<='1';
+ clk<='0';
--
when 1022 => bus_data<="01010110";
csData<='1';
@@ -174,7 +174,7 @@ begin
when 1023 => bus_data<="01010110";
csData<='1';
rw<='0';
- clk<='1';
+ clk<='0';
--
when 1025 => bus_data<="01010110";
csData<='1';
@@ -182,7 +182,7 @@ begin
when 1026 => bus_data<="01010110";
csData<='1';
rw<='0';
- clk<='1';
+ clk<='0';
--
when 1028 => bus_data<="01010110";
csData<='1';
@@ -190,7 +190,7 @@ begin
when 1029 => bus_data<="01010110";
csData<='1';
rw<='0';
- clk<='1';
+ clk<='0';
--
when 1031 => bus_data<="01010110";
csData<='1';
@@ -198,7 +198,7 @@ begin
when 1032 => bus_data<="01010110";
csData<='1';
rw<='0';
- clk<='1';
+ clk<='0';
--
when 1034 => bus_data<="01010110";
csData<='1';
@@ -206,7 +206,7 @@ begin
when 1035 => bus_data<="01010110";
csData<='1';
rw<='0';
- clk<='1';
+ clk<='0';
--
when 1037 => bus_data<="01010110";
csData<='1';
@@ -214,7 +214,7 @@ begin
when 1038 => bus_data<="01010110";
csData<='1';
rw<='0';
- clk<='1';
+ clk<='0';
--
when 1040 => bus_data<="01010110";
csData<='1';
@@ -222,7 +222,7 @@ begin
when 1041 => bus_data<="01010110";
csData<='1';
rw<='0';
- clk<='1';
+ clk<='0';
--
when 1043 => bus_data<="01010110";
csData<='1';
@@ -230,7 +230,7 @@ begin
when 1044 => bus_data<="01010110";
csData<='1';
rw<='0';
- clk<='1';
+ clk<='0';
--
when 1046 => bus_data<="01010110";
csData<='1';
@@ -238,7 +238,7 @@ begin
when 1047 => bus_data<="01010110";
csData<='1';
rw<='0';
- clk<='1';
+ clk<='0';
--
when 1049 => bus_data<="01010110";
csData<='1';
@@ -246,7 +246,7 @@ begin
when 1050 => bus_data<="01010110";
csData<='1';
rw<='0';
- clk<='1';
+ clk<='0';
--
when 1052 => bus_data<="01010110";
csData<='1';
@@ -254,7 +254,7 @@ begin
when 1053 => bus_data<="01010110";
csData<='1';
rw<='0';
- clk<='1';
+ clk<='0';
--
when 1055 => bus_data<="01010110";
csData<='1';
@@ -262,7 +262,7 @@ begin
when 1056 => bus_data<="01010110";
csData<='1';
rw<='0';
- clk<='1';
+ clk<='0';
--
when 1058 => bus_data<="01010110";
csData<='1';
@@ -270,7 +270,7 @@ begin
when 1059 => bus_data<="01010110";
csData<='1';
rw<='0';
- clk<='1';
+ clk<='0';
--
when 1061 => bus_data<="01010110";
csData<='1';
@@ -278,7 +278,7 @@ begin
when 1062 => bus_data<="01010110";
csData<='1';
rw<='0';
- clk<='1';
+ clk<='0';
--
when 1064 => bus_data<="01010110";
csData<='1';
@@ -286,7 +286,7 @@ begin
when 1065 => bus_data<="01010110";
csData<='1';
rw<='0';
- clk<='1';
+ clk<='0';
when others => null;
diff --git a/2004/n/fpga/src/portserie/portserie/txserie.vhd b/2004/n/fpga/src/portserie/portserie/txserie.vhd
index 2b94529..ece9754 100644
--- a/2004/n/fpga/src/portserie/portserie/txserie.vhd
+++ b/2004/n/fpga/src/portserie/portserie/txserie.vhd
@@ -169,6 +169,7 @@ RCONF : regIO port map(
load=>dummy(0),
ck=>bus_clk,
rst=>rst);
+-- Config : (x ! x ! x ! On/Off ! Purge ! IntEn ! BdR1 ! BdR0)
-- Flag : (x ! x ! x ! x ! Empty ! Full ! FLI1 ! FLI0 )
RFLAG : regIO port map(
@@ -196,12 +197,17 @@ flagreg(3)<=fifoEmpty;
-- irq
minirq<=fifoFull and confreg(2); --fifo full AND Int/En
+
-- controle des flux
-fifockin <= (csData and bus_clk and not rw and not rst);
+fifockin <= (csData and not bus_clk and not rw and not rst);
fifockout <= (txready and not fifoEmpty);
-process(fifodready,txready)
+
+process(fifodready,txready,rst)
begin
+if(rst='1') then
+ state_txload<= 0;
+else
txload <= '0';
case state_txload is
when 0 => if(txready='1') then
@@ -232,6 +238,7 @@ begin
end if;
when others => state_txload <= 0;
end case;
+end if;
end process;
diff --git a/2004/n/fpga/src/portserie/rxserie/rxserie.vhd b/2004/n/fpga/src/portserie/rxserie/rxserie.vhd
index e0ec325..46d2a31 100644
--- a/2004/n/fpga/src/portserie/rxserie/rxserie.vhd
+++ b/2004/n/fpga/src/portserie/rxserie/rxserie.vhd
@@ -169,7 +169,7 @@ RCONF : regIO port map(
load=>dummy(0),
ck=>bus_clk,
rst=>rst);
-
+-- Config : (x ! x ! EIEn ! On/Off ! DRIEn ! FFIEn ! BdR1 ! BdR0)
-- Flag : (x ! PErr ! FErr ! OErr ! Empty ! Full ! FLI1 ! FLI0 )
RFLAG : regIO port map(
cs=>csFlag,