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-- modele.vhd
-- Eurobot 2004 : APB Team
-- Auteur : Pierre-Andr� Galmes
-- Fichier mod�le pour la d�claration de module.

library ieee;
use	ieee.std_logic_1164.all;
use     ieee.std_logic_arith.all;
use     ieee.std_logic_unsigned.all;

use	work.nono_const.all;


entity bch_txserie is
end bch_txserie;

architecture sim1 of bch_txserie is
component txserie
   port (
	rst : in std_logic;
	bus_clk : in std_logic;
	rw  : in std_logic; -- read (0) / write (1)
	bus_data : inout T_DATA:=(others => 'Z');
	clk: in std_logic;
	clk_ref: in std_logic;
	txout:	out std_logic;
	minIRQ:	out std_logic;
	csData : in std_logic;
	csConfig : in std_logic;
	csFlag : in std_logic
    );
end component;


-- d�finiton des signaux
signal simclk:std_logic:='0';
signal	rst : std_logic;
signal	clk : std_logic;
signal	clk_ref : std_logic:='0';
signal	rw  : std_logic;
signal	bus_data : T_DATA:=(others => 'Z');
signal	masterck: std_logic:='0';
signal	txout:	std_logic;
signal	minIRQ:	std_logic;
signal	csData : std_logic;
signal	csConfig : std_logic;
signal	csFlag :  std_logic;

signal state:integer:=-30;



begin
    UUT : txserie
 port map(
	rst => rst,
	bus_clk => clk,
	rw  =>rw,
	bus_data => bus_data,
	clk => masterck,
	clk_ref => clk_ref,
	txout => txout,
	minIRQ => minirq,
	csData => csData,
	csConfig => csConfig,
	csFlag => csFlag );


	rst<='1','0' after 5 ns;
   simclk<= not simclk after 10 ns;
   masterck<= not masterck after 3 ns;
	clk_ref <= not clk_ref after 10 ns;

	combi:process(state)
	begin
	clk <= '0';
	rw  <= '0';
	bus_data <= (others => 'Z');
	csData <= '0';
	csConfig <= '0';
	csFlag <= '0';

		case state is
		when 1 =>  	bus_data<="01110111";
						csConfig<='1';
						rw<='0';
		when 2 =>   bus_data<="01110111";
						csConfig<='1';
						rw<='0';
						clk<='1';
		when 4 =>  	bus_data<="00010110";
						csData<='1';
						rw<='0';
		when 5 =>   bus_data<="00010110";
						csData<='1';
						rw<='0';
						clk<='1';

		when 70 =>  	bus_data<="00010110";
						csData<='1';
						rw<='0';
		when 71 =>   bus_data<="00010110";
						csData<='1';
						rw<='0';
						clk<='1';

		when 12 =>  				csFlag<='1';
						rw<='1';
		when 13 =>   
						csFlag<='1';
						rw<='1';
						clk<='1';
						

		when 20 =>  	bus_data<="01010101";
						csData<='1';
						rw<='0';
		when 21 =>   bus_data<="01010101";
						csData<='1';
						rw<='0';
						clk<='1';

		when 1004 =>  	bus_data<="00010110";
						csData<='1';
						rw<='0';
		when 1005 =>   bus_data<="00010110";
						csData<='1';
						rw<='0';
						clk<='1';
-- 
		when 1007 =>  	bus_data<="01010110";
						csData<='1';
						rw<='0';
		when 1008 =>   bus_data<="01010110";
						csData<='1';
						rw<='0';
						clk<='1';
-- 
		when 1010 =>  	bus_data<="01010110";
						csData<='1';
						rw<='0';
		when 1011 =>   bus_data<="01010110";
						csData<='1';
						rw<='0';
						clk<='1';
-- 
		when 1013 =>  	bus_data<="01010110";
						csData<='1';
						rw<='0';
		when 1014 =>   bus_data<="01010110";
						csData<='1';
						rw<='0';
						clk<='1';
-- 
		when 1016 =>  	bus_data<="01010110";
						csData<='1';
						rw<='0';
		when 1017 =>   bus_data<="01010110";
						csData<='1';
						rw<='0';
						clk<='1';
-- 
		when 1019 =>  	bus_data<="01010110";
						csData<='1';
						rw<='0';
		when 1020 =>   bus_data<="01010110";
						csData<='1';
						rw<='0';
						clk<='1';
-- 
		when 1022 =>  	bus_data<="01010110";
						csData<='1';
						rw<='0';
		when 1023 =>   bus_data<="01010110";
						csData<='1';
						rw<='0';
						clk<='1';
-- 
		when 1025 =>  	bus_data<="01010110";
						csData<='1';
						rw<='0';
		when 1026 =>   bus_data<="01010110";
						csData<='1';
						rw<='0';
						clk<='1';
-- 
		when 1028 =>  	bus_data<="01010110";
						csData<='1';
						rw<='0';
		when 1029 =>   bus_data<="01010110";
						csData<='1';
						rw<='0';
						clk<='1';
-- 
		when 1031 =>  	bus_data<="01010110";
						csData<='1';
						rw<='0';
		when 1032 =>   bus_data<="01010110";
						csData<='1';
						rw<='0';
						clk<='1';
-- 
		when 1034 =>  	bus_data<="01010110";
						csData<='1';
						rw<='0';
		when 1035 =>   bus_data<="01010110";
						csData<='1';
						rw<='0';
						clk<='1';
-- 
		when 1037 =>  	bus_data<="01010110";
						csData<='1';
						rw<='0';
		when 1038 =>   bus_data<="01010110";
						csData<='1';
						rw<='0';
						clk<='1';
-- 
		when 1040 =>  	bus_data<="01010110";
						csData<='1';
						rw<='0';
		when 1041 =>   bus_data<="01010110";
						csData<='1';
						rw<='0';
						clk<='1';
-- 
		when 1043 =>  	bus_data<="01010110";
						csData<='1';
						rw<='0';
		when 1044 =>   bus_data<="01010110";
						csData<='1';
						rw<='0';
						clk<='1';
-- 
		when 1046 =>  	bus_data<="01010110";
						csData<='1';
						rw<='0';
		when 1047 =>   bus_data<="01010110";
						csData<='1';
						rw<='0';
						clk<='1';
-- 
		when 1049 =>  	bus_data<="01010110";
						csData<='1';
						rw<='0';
		when 1050 =>   bus_data<="01010110";
						csData<='1';
						rw<='0';
						clk<='1';
-- 
		when 1052 =>  	bus_data<="01010110";
						csData<='1';
						rw<='0';
		when 1053 =>   bus_data<="01010110";
						csData<='1';
						rw<='0';
						clk<='1';
-- 
		when 1055 =>  	bus_data<="01010110";
						csData<='1';
						rw<='0';
		when 1056 =>   bus_data<="01010110";
						csData<='1';
						rw<='0';
						clk<='1';
-- 
		when 1058 =>  	bus_data<="01010110";
						csData<='1';
						rw<='0';
		when 1059 =>   bus_data<="01010110";
						csData<='1';
						rw<='0';
						clk<='1';
-- 
		when 1061 =>  	bus_data<="01010110";
						csData<='1';
						rw<='0';
		when 1062 =>   bus_data<="01010110";
						csData<='1';
						rw<='0';
						clk<='1';
-- 
		when 1064 =>  	bus_data<="01010110";
						csData<='1';
						rw<='0';
		when 1065 =>   bus_data<="01010110";
						csData<='1';
						rw<='0';
						clk<='1';
					

		when others => null;
		end case;
	end process;

	sequ:process(simclk)
	begin
		state<=state+1;
	end process;




end sim1;