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-- -------------------------------------------
-- Port s�rie RX pour le fpga robot
-- -------------------------------------------
-- 
-- * Prend 3 adresses m�moire :
--    0 - Rxdata 
--    1 - Flag :   (x ! x ! FNE ! FFull  !  FL3  ! FL2  ! FL1  ! FL0 )
--    2 - Config : (x ! x !  x  ! On/Off ! FNEIF ! FFIF ! BdR1 ! BdR0)
-- * Mettre le bit On/Off � 1 pour activer la reception
-- * Chaque lecture dans rxdata d�pile la donn�e de la fifo
-- * D�s que le registre � d�calage est plein, il empile la donn�e dans la
--   fifo.
-- * Deux bits de stop
-- * Quand la fifo est pleine, met le flag FifoFull (FF) � 1. Chaque front
--   montant du flag FF met � 1 le flag d'interruption FFIF et g�n�re une
--   interruption. Il faut alors mettre � 0 FFIF, qui sera remis � 1 au
--   prochain front montant de FF
-- * Quand il y a au moins une donn�e dans la pile, le bit FifiNonEmpty (FNE) 
--   est � 1. Quand FNE passe de 0 � 1, le flag FNEIF passe � 1 et g�n�re une
--   interruption. Il faut alors mettre � 0 FNEIF, qui repassera � 1 au 
--   prochain front montant de FNE
-- * On peut lire l'�tat de la pile dans le registre de flags (FifoLevel1/0)
-- * Baudrate disponible : 
--	BdR1/0 	! Baudrate
--	00	! 9600
--	01	! 19200
--	10	! 57600
--	11	! 115200


-- Config : (x ! x ! EIEn ! On/Off ! DRIEn ! FFIEn ! BdR1 ! BdR0)
-- Flag : (x ! PErr ! FErr ! OErr ! Empty ! Full ! FLI1 ! FLI0 )


library ieee;
use	ieee.std_logic_1164.all;
use     ieee.std_logic_arith.all;
use     ieee.std_logic_unsigned.all;

use	work.nono_const.all;

entity rxserie is
    port (
	rst : in std_logic;
	bus_clk : in std_logic;
	rw  : in std_logic; -- read (0) / write (1)
	bus_data : inout T_DATA;
	clk: in std_logic;
	clk_ref: in std_logic;
	rxin:	in std_logic;
	irqFIFO:	out std_logic;
	irqRX:	out std_logic;
	irqERR:	out std_logic;
	csData : in std_logic;
	csConfig : in std_logic;
	csFlag : in std_logic
    );
end rxserie;

architecture rtl of rxserie is
-- composants
component clockgene
   port(
   rst:	in std_logic;
	ckin:	in std_logic;
	ckout:	out std_logic;
	param:	in std_logic_vector(1 downto 0)
	);
end component;

component regIO
   port(
	cs: in std_logic;
	bus_data: inout T_DATA;
	input: 	in   T_DATA;
	output: out  T_DATA;
	rw:	in std_logic;
	load:	in std_logic;
	ck:	in std_logic;
	rst:	in std_logic);
end component;

component fifodriver
   port(
	clk: in std_logic;
	rst: in std_logic;
	readreq: in std_logic;
	writereq: in std_logic;
	din: IN std_logic_VECTOR(7 downto 0);
	dout: OUT std_logic_VECTOR(7 downto 0);
	dready: out std_logic;
	full: OUT std_logic;
	empty: OUT std_logic;
	data_count: OUT std_logic_VECTOR(1 downto 0));
END COMPONENT;

component RXCVER 
   port (
	MCLKX16     : in  std_logic; -- input clock, 16x baudrate clock used for synchronization
	READ        : in  std_logic; -- Read Strobe
	RX          : in  std_logic; -- Receive Input Line
	RESET       : in  std_logic; -- Global Reset
	RXRDY       : out std_logic; -- Receiver data ready to read
	PARITY_ERR  : out std_logic; -- Receiver parity error flag
	FRAMING_ERR : out std_logic; -- Receiver framing error flag
	OVERRUN     : out std_logic; -- Receiver overrun error flag
	DATA        : out std_logic_vector(7 downto 0) -- 8 bit output data bus
	);
end component;


-- signaux
signal rxready:std_logic; -- Receiver data ready to read
signal rxread:std_logic:='0'; 
signal rxparERR:std_logic:='0'; -- Receiver parity error flag
signal rxfrmERR:std_logic:='0'; -- Receiver framing error flag
signal rxovrrERR:std_logic:='0'; -- Receiver overrun error flag

signal rxck: std_logic;
signal geneck:std_logic;

signal fifoEmpty: std_logic;
signal fifoFull: std_logic;
signal fifoLevel: std_logic_vector(1 downto 0);
signal fifopurge: std_logic:='0';
signal fifockin: std_logic;
signal fifockout: std_logic;
signal fifodready: std_logic;

signal confreg: T_DATA:="00000000";
signal flagreg: T_DATA:="00000000";
signal inter_data: T_DATA;
signal inter_bus: T_DATA;
signal inter_fifo: T_DATA;

signal state_rx_read:integer:=0;

signal dummy : T_DATA :=(others =>'0');
signal un: std_logic :='1';


begin
CLOCK1 : clockgene
port map(
	  rst => rst,
	  ckin=>geneck,
	  ckout=>rxck,
	  param=>confreg(1 downto 0));

FIFO1: fifodriver port map(
		clk => clk,
		rst => fifopurge,
		readreq => fifockout,
		writereq => fifockin,
		din => inter_data,
		dout => inter_fifo,
		dready => fifodready,
		full => fifoFull,
		empty => fifoEmpty,
		data_count => fifoLevel(1 downto 0));

-- Config : (x ! x ! EIEn ! On/Off ! DRIEn ! FFIEn ! BdR1 ! BdR0)
RCONF : regIO port map(
 	cs=>csConfig,
	bus_data=>bus_data,
	input=>dummy,
	output=>confreg,
	rw=>rw,
	load=>dummy(0),
	ck=>bus_clk,
	rst=>rst);
-- Config : (x ! x ! EIEn ! On/Off ! DRIEn ! FFIEn ! BdR1 ! BdR0)
-- Flag : (x ! PErr ! FErr ! OErr ! Empty ! Full ! FLI1 ! FLI0 )
RFLAG : regIO port map(
   cs=>csFlag,
	bus_data=>bus_data,
	input=>flagreg,
	output=>open,
	rw=>rw,
	load=>un,
	ck=>bus_clk,
	rst=>rst);

RC1:RXCVER
port map(
	MCLKX16     =>rxck, -- input clock, 16x baudrate clock used for synchronization
	READ        =>rxread, --rxread, -- Read Strobe
	RX          =>rxin, -- Receive Input Line
	RESET       =>rst, -- Global Reset
	RXRDY       =>rxready, -- Receiver data ready to read
	PARITY_ERR  =>rxparERR, -- Receiver parity error flag
	FRAMING_ERR =>rxfrmERR, -- Receiver framing error flag
	OVERRUN     =>rxovrrERR, -- Receiver overrun error flag
	DATA        =>inter_data -- 8 bit output data bus
	);


-- config
geneck <= (confreg(4) and clk_ref); -- On/Off et clk_ref --confreg(4)
fifopurge<=rst;

-- flags
flagreg(1 downto 0) <= fifoLevel(1 downto 0);
flagreg(2) <= fifoFull;
flagreg(3) <= fifoEmpty;
flagreg(4) <= rxparERR; -- Receiver parity error flag
flagreg(5) <= rxfrmERR; -- Receiver framing error flag
flagreg(6) <= rxovrrERR; -- Receiver overrun error flag


-- controle des flux
fifockout <= '1' when (csData='1' and rw='1' and rst='0') else '0';
fifockin <= ((not rxread) and (not fifoFull));

inter_bus <= inter_fifo when (fifockout='1') else (others => 'Z');

bus_data <= inter_bus;

-- irq
irqFifo <= (fifoLevel(1) and fifoLevel(0));-- and confreg(2); --fifo almost full AND Int/En
irqRx <= (not fifoEmpty);-- and confreg(3);
irqErr <= (rxparERR or rxovrrERR or rxfrmERR or fifoFull);-- and confreg(5);

-- sortie de donn�e du r�cepteur
process(rxck)
begin
	if(rxck'event and rxck='1') then
		rxread<='1';
		case state_rx_read is
		when 0 =>	if(rxready='1') then
							state_rx_read<=1;
						end if;
		when 1 =>	state_rx_read<=2;
		when 2 =>	rxread<='0';
						state_rx_read<=3;
		when 3 =>	if(rxready='0') then
							state_rx_read<=0;
						end if;
		when others => null;
		end case;
	end if;
end process;

end rtl;