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authorgalmes2004-03-01 15:57:50 +0000
committergalmes2004-03-01 15:57:50 +0000
commit76098ead389c3803b9d5b47c8f6e915e1123b03a (patch)
treea91a0f7f25e26e768cb00c0d1dace776c473a4cd /2004/n/fpga/src
parentaa5af70bfadebbf3f4809d232f3cf692541cac36 (diff)
Suppression du decodeur dans le gpio.
Diffstat (limited to '2004/n/fpga/src')
-rw-r--r--2004/n/fpga/src/gpio/bch_gpio.vhd93
-rw-r--r--2004/n/fpga/src/gpio/gpio.vhd58
2 files changed, 57 insertions, 94 deletions
diff --git a/2004/n/fpga/src/gpio/bch_gpio.vhd b/2004/n/fpga/src/gpio/bch_gpio.vhd
index 9f0e47a..16e5ca3 100644
--- a/2004/n/fpga/src/gpio/bch_gpio.vhd
+++ b/2004/n/fpga/src/gpio/bch_gpio.vhd
@@ -20,22 +20,20 @@ end bch_gpio;
architecture sim1 of bch_gpio is
component gpio
- generic (
- A_REG_DATA_WRITE : T_ADDRESS;
- A_REG_DIRECTION : T_ADDRESS;
- A_REG_INTERRUPT_MASK : T_ADDRESS;
- A_DATA_READ_OUTPUT : T_ADDRESS
- );
- port(
- rst : in std_logic;
- clk_i : in std_logic; -- clock du bus isa
- clk_m : in std_logic; -- master clock
- rw : in std_logic; -- read (0) / write (1) TODO ??
- interrupt : out std_logic;
- bus_address : in T_ADDRESS;
- bus_data : inout T_DATA;
- io_output : inout T_DATA
- );
+ port(
+ rst : in std_logic;
+ clk_i : in std_logic; -- clock du bus isa
+ clk_m : in std_logic; -- master clock
+ rw : in std_logic; -- read (0) / write (1) TODO ??
+ interrupt : out std_logic;
+ bus_data : inout T_DATA;
+ io_output : inout T_DATA;
+ -- chip select
+ cs_reg_data_write : in std_logic;
+ cs_reg_direction : in std_logic;
+ cs_reg_it_mask : in std_logic;
+ cs_reg_read_output : in std_logic
+ );
end component;
-- définiton des signaux
@@ -44,31 +42,31 @@ architecture sim1 of bch_gpio is
signal clk_m : std_logic := '0';
signal rw : std_logic := '0';
signal interrupt : std_logic;
- signal bus_address : T_ADDRESS;
signal bus_data : T_DATA;
signal io_output : T_DATA;
+ -- chip select
+ signal cs_reg_data_write : std_logic := '0';
+ signal cs_reg_direction : std_logic := '0';
+ signal cs_reg_it_mask : std_logic := '0';
+ signal cs_reg_read_output : std_logic := '0';
begin
-- -----------------------------------------------------
-- mapping du gpio. A reprendre pour le mapping final !!
-- -----------------------------------------------------
U1 : gpio
- generic map (
- -- Définition des addresses.
- A_REG_DATA_WRITE => A_IO1_REG_DATA,
- A_REG_DIRECTION => A_IO1_REG_DIRECTION,
- A_REG_INTERRUPT_MASK => A_IO1_REG_INTERRUPT_MASK,
- A_DATA_READ_OUTPUT => A_IO1_READ_OUTPUT
- )
port map (
rst => rst,
clk_i => clk_i,
clk_m => clk_m,
rw => rw,
interrupt => interrupt,
- bus_address => bus_address,
bus_data => bus_data,
- io_output => io_output
+ io_output => io_output,
+ cs_reg_read_output => cs_reg_read_output,
+ cs_reg_it_mask => cs_reg_it_mask,
+ cs_reg_direction => cs_reg_direction,
+ cs_reg_data_write => cs_reg_data_write
);
-- ---------------------------------
@@ -80,18 +78,17 @@ begin
-- déclaration de procédures de test.
-- ----------------------------------
-- Lire dans un registre ou la sortie !
- procedure do_read (address : in T_ADDRESS) is
- begin
- rw <= ISA_READ;
- bus_address <= address;
- bus_data <= "ZZZZZZZZ"; --est en sortie.
- end do_read;
+ --procedure do_read (address : in T_ADDRESS) is
+ --begin
+-- rw <= ISA_READ;
+-- bus_address <= address;
+-- bus_data <= "ZZZZZZZZ"; --est en sortie.
+-- end do_read;
-- Ecrire dans un registre !
- procedure do_write (address : in T_ADDRESS; data : in T_DATA) is
+ procedure do_write (data : in T_DATA) is
begin
rw <= ISA_WRITE;
- bus_address <= address;
bus_data <= data;
end do_write;
@@ -107,24 +104,27 @@ begin
-- Ecriture dans les trois registres.
wait for (3*CK_PERIOD);
- do_write (A_IO1_REG_DIRECTION, "00000111"); -- 3 bits poid faible : in.
+ cs_reg_direction <= '1';
+ do_write ("00000111"); -- 3 bits poid faible : in.
wait for (3*CK_PERIOD);
- do_write (A_IO1_REG_DATA, x"01");
+ cs_reg_direction <= '0';
+ cs_reg_data_write <= '1';
+ do_write (x"01"); -- 3 bits poid faible : in.
-- interruption sur les 5 bits de poid faible.
- wait for (3*CK_PERIOD);
- do_write (A_IO1_REG_INTERRUPT_MASK, "11111000");
+-- wait for (3*CK_PERIOD);
+-- do_write (A_IO1_REG_INTERRUPT_MASK, "11111000");
-- Lecture dans les trois registres.
- wait for (3*CK_PERIOD);
- do_read (A_IO1_REG_INTERRUPT_MASK);
- wait for (3*CK_PERIOD);
- do_read (A_IO1_REG_DIRECTION);
- wait for (3*CK_PERIOD);
- do_read (A_IO1_REG_DATA);
+-- wait for (3*CK_PERIOD);
+-- do_read (A_IO1_REG_INTERRUPT_MASK);
+-- wait for (3*CK_PERIOD);
+-- do_read (A_IO1_REG_DIRECTION);
+-- wait for (3*CK_PERIOD);
+-- do_read (A_IO1_REG_DATA);
-- Lecture de la donnée sur io_output.
- wait for (3*CK_PERIOD);
- do_read (A_IO1_READ_OUTPUT);
+-- wait for (3*CK_PERIOD);
+-- do_read (A_IO1_READ_OUTPUT);
end process;
@@ -137,6 +137,7 @@ begin
"00001ZZZ" after 10*CK_PERIOD,
"00010ZZZ" after 15*CK_PERIOD;
+
end sim1;
-- Configuration
diff --git a/2004/n/fpga/src/gpio/gpio.vhd b/2004/n/fpga/src/gpio/gpio.vhd
index 3329997..e38f6bf 100644
--- a/2004/n/fpga/src/gpio/gpio.vhd
+++ b/2004/n/fpga/src/gpio/gpio.vhd
@@ -11,21 +11,19 @@ use ieee.std_logic_unsigned.all;
use work.nono_const.all;
entity gpio is
- generic (
- A_REG_DATA_WRITE : T_ADDRESS;
- A_REG_DIRECTION : T_ADDRESS;
- A_REG_INTERRUPT_MASK : T_ADDRESS;
- A_DATA_READ_OUTPUT : T_ADDRESS
- );
port(
rst : in std_logic;
clk_i : in std_logic; -- clock du bus isa
clk_m : in std_logic; -- master clock
rw : in std_logic; -- read (0) / write (1) TODO ??
interrupt : out std_logic;
- bus_address : in T_ADDRESS;
bus_data : inout T_DATA;
- io_output : inout T_DATA
+ io_output : inout T_DATA;
+ -- chip select
+ cs_reg_data_write : in std_logic;
+ cs_reg_direction : in std_logic;
+ cs_reg_it_mask : in std_logic;
+ cs_reg_read_output : in std_logic
);
end entity;
@@ -33,23 +31,6 @@ architecture RTL of gpio is
-- Définition des composants utilisés.
--- Décodeur d'addresses.
-component decodeur is
- generic (
- -- adresses des différents registres du module.
- A_REG0 : T_ADDRESS;
- A_REG1 : T_ADDRESS;
- A_REG2 : T_ADDRESS;
- A_REG3 : T_ADDRESS
- );
- port (
- bus_address : in T_ADDRESS;
- enable0 : out std_logic;
- enable1 : out std_logic;
- enable2 : out std_logic;
- enable3 : out std_logic
- );
-end component;
-- Registre.
component reg_rw is
@@ -95,11 +76,6 @@ end component;
-- définition des signaux.
-- clk, rst... sont définis dans l'entity du GPIO.
--
-signal en_reg_direction : std_logic;
-signal en_reg_it_mask : std_logic;
-signal en_reg_data : std_logic;
-signal en_read_output : std_logic;
---
signal bus_direction_mask : T_DATA;
signal bus_it_mask : T_DATA;
signal bus_reg_data : T_DATA;
@@ -107,20 +83,6 @@ signal bus_reg_data : T_DATA;
begin
-- Mapping des composants.
-decod : decodeur
-generic map (
- A_IO1_REG_DATA,
- A_IO1_REG_DIRECTION,
- A_IO1_REG_INTERRUPT_MASK,
- A_IO1_READ_OUTPUT
-)
-port map (
- bus_address,
- en_reg_data,
- en_reg_direction,
- en_reg_it_mask,
- en_read_output
-);
--
Reg_direction_mask : reg_rw
@@ -128,7 +90,7 @@ port map (
clk_m,
rst,
rw,
- en_reg_direction,
+ cs_reg_direction,
bus_data,
bus_direction_mask
);
@@ -139,7 +101,7 @@ port map (
clk_m,
rst,
rw,
- en_reg_data,
+ cs_reg_data_write,
bus_data,
bus_reg_data
);
@@ -150,7 +112,7 @@ port map (
clk_m,
rst,
rw,
- en_reg_it_mask,
+ cs_reg_it_mask,
bus_data,
bus_it_mask
);
@@ -158,7 +120,7 @@ port map (
--
read_output : tristate
port map (
- en_read_output,
+ cs_reg_read_output,
io_output,
bus_data
);