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Diffstat (limited to '2004/n/fpga/src/gpio/gpio.vhd')
-rw-r--r--2004/n/fpga/src/gpio/gpio.vhd58
1 files changed, 10 insertions, 48 deletions
diff --git a/2004/n/fpga/src/gpio/gpio.vhd b/2004/n/fpga/src/gpio/gpio.vhd
index 3329997..e38f6bf 100644
--- a/2004/n/fpga/src/gpio/gpio.vhd
+++ b/2004/n/fpga/src/gpio/gpio.vhd
@@ -11,21 +11,19 @@ use ieee.std_logic_unsigned.all;
use work.nono_const.all;
entity gpio is
- generic (
- A_REG_DATA_WRITE : T_ADDRESS;
- A_REG_DIRECTION : T_ADDRESS;
- A_REG_INTERRUPT_MASK : T_ADDRESS;
- A_DATA_READ_OUTPUT : T_ADDRESS
- );
port(
rst : in std_logic;
clk_i : in std_logic; -- clock du bus isa
clk_m : in std_logic; -- master clock
rw : in std_logic; -- read (0) / write (1) TODO ??
interrupt : out std_logic;
- bus_address : in T_ADDRESS;
bus_data : inout T_DATA;
- io_output : inout T_DATA
+ io_output : inout T_DATA;
+ -- chip select
+ cs_reg_data_write : in std_logic;
+ cs_reg_direction : in std_logic;
+ cs_reg_it_mask : in std_logic;
+ cs_reg_read_output : in std_logic
);
end entity;
@@ -33,23 +31,6 @@ architecture RTL of gpio is
-- Définition des composants utilisés.
--- Décodeur d'addresses.
-component decodeur is
- generic (
- -- adresses des différents registres du module.
- A_REG0 : T_ADDRESS;
- A_REG1 : T_ADDRESS;
- A_REG2 : T_ADDRESS;
- A_REG3 : T_ADDRESS
- );
- port (
- bus_address : in T_ADDRESS;
- enable0 : out std_logic;
- enable1 : out std_logic;
- enable2 : out std_logic;
- enable3 : out std_logic
- );
-end component;
-- Registre.
component reg_rw is
@@ -95,11 +76,6 @@ end component;
-- définition des signaux.
-- clk, rst... sont définis dans l'entity du GPIO.
--
-signal en_reg_direction : std_logic;
-signal en_reg_it_mask : std_logic;
-signal en_reg_data : std_logic;
-signal en_read_output : std_logic;
---
signal bus_direction_mask : T_DATA;
signal bus_it_mask : T_DATA;
signal bus_reg_data : T_DATA;
@@ -107,20 +83,6 @@ signal bus_reg_data : T_DATA;
begin
-- Mapping des composants.
-decod : decodeur
-generic map (
- A_IO1_REG_DATA,
- A_IO1_REG_DIRECTION,
- A_IO1_REG_INTERRUPT_MASK,
- A_IO1_READ_OUTPUT
-)
-port map (
- bus_address,
- en_reg_data,
- en_reg_direction,
- en_reg_it_mask,
- en_read_output
-);
--
Reg_direction_mask : reg_rw
@@ -128,7 +90,7 @@ port map (
clk_m,
rst,
rw,
- en_reg_direction,
+ cs_reg_direction,
bus_data,
bus_direction_mask
);
@@ -139,7 +101,7 @@ port map (
clk_m,
rst,
rw,
- en_reg_data,
+ cs_reg_data_write,
bus_data,
bus_reg_data
);
@@ -150,7 +112,7 @@ port map (
clk_m,
rst,
rw,
- en_reg_it_mask,
+ cs_reg_it_mask,
bus_data,
bus_it_mask
);
@@ -158,7 +120,7 @@ port map (
--
read_output : tristate
port map (
- en_read_output,
+ cs_reg_read_output,
io_output,
bus_data
);