summaryrefslogtreecommitdiff
path: root/2004/n/fpga/src/gpio/bch_gpio.vhd
blob: 16e5ca3e1cb081d59ca4137394f7e520d3bd0f7c (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
-- bch_gpio.vhd
-- Eurobot 2004 : APB Team
-- Auteur : Pierre-Andr� Galmes
-- Banc de test.

-- RQ : Observer 240ns

library ieee;
use	ieee.std_logic_1164.all;
use     ieee.std_logic_arith.all;
use     ieee.std_logic_unsigned.all;

use	work.isa_const.all;
use	work.nono_const.all;


entity bch_gpio is
end bch_gpio;

architecture sim1 of bch_gpio is
    
    component gpio
    port(
        rst : in std_logic;
        clk_i : in std_logic;   -- clock du bus isa
        clk_m : in std_logic;   -- master clock
        rw  : in std_logic; -- read (0) / write (1) TODO ??
        interrupt : out std_logic;
        bus_data : inout T_DATA;
        io_output : inout T_DATA;
        -- chip select
        cs_reg_data_write : in std_logic;
        cs_reg_direction : in std_logic;
        cs_reg_it_mask : in std_logic;
        cs_reg_read_output : in std_logic
    );    	
    end component;

    -- d�finiton des signaux
    signal rst : std_logic;
    signal clk_i : std_logic := '0';
    signal clk_m : std_logic := '0';
    signal rw : std_logic := '0';
    signal interrupt : std_logic;
    signal bus_data : T_DATA;
    signal io_output : T_DATA;
    -- chip select
    signal cs_reg_data_write : std_logic := '0';
    signal cs_reg_direction : std_logic := '0';
    signal cs_reg_it_mask : std_logic := '0';
    signal cs_reg_read_output : std_logic := '0';

begin
    -- -----------------------------------------------------
    -- mapping du gpio. A reprendre pour le mapping final !!
    -- -----------------------------------------------------
    U1 : gpio
	port map (		
	    rst => rst,
	    clk_i => clk_i,
	    clk_m => clk_m,
	    rw => rw,
	    interrupt => interrupt,
	    bus_data => bus_data,
	    io_output => io_output,
	    cs_reg_read_output => cs_reg_read_output,
	    cs_reg_it_mask => cs_reg_it_mask,
	    cs_reg_direction => cs_reg_direction,
	    cs_reg_data_write => cs_reg_data_write
	);
    
    -- ---------------------------------
    -- Process de test.
    -- ---------------------------------
    process
    
    -- ----------------------------------
    -- d�claration de proc�dures de test.
    -- ----------------------------------
    -- Lire dans un registre ou la sortie !
    --procedure do_read (address : in T_ADDRESS) is
    --begin
--	rw <= ISA_READ;
--	bus_address <= address;
--	bus_data <= "ZZZZZZZZ"; --est en sortie.
--    end do_read;
    
    -- Ecrire dans un registre !
    procedure do_write (data : in T_DATA) is
    begin
	rw <= ISA_WRITE;
	bus_data <= data;
    end do_write;

    -- Tester que le d�codeur fonctionne correctement.
    --procedure test_decod (bidon1 : in std_logic) is
    --begin
    --end test_decod;

    -- -------------------------
    -- D�but du process de test.
    -- -------------------------
    begin

	-- Ecriture dans les trois registres.
	wait for (3*CK_PERIOD);
	cs_reg_direction <= '1';
	do_write ("00000111"); -- 3 bits poid faible : in.
	wait for (3*CK_PERIOD);
	cs_reg_direction <= '0';
	cs_reg_data_write <= '1';
	do_write (x"01"); -- 3 bits poid faible : in.
	-- interruption sur les 5 bits de poid faible.
--	wait for (3*CK_PERIOD);
--	do_write (A_IO1_REG_INTERRUPT_MASK, "11111000"); 
	
	-- Lecture dans les trois registres.
--	wait for (3*CK_PERIOD);
--	do_read (A_IO1_REG_INTERRUPT_MASK);
--	wait for (3*CK_PERIOD);
--	do_read (A_IO1_REG_DIRECTION);
--	wait for (3*CK_PERIOD);
--	do_read (A_IO1_REG_DATA);
	
	-- Lecture de la donn�e sur io_output.
--	wait for (3*CK_PERIOD);
--	do_read (A_IO1_READ_OUTPUT);
    
    end process;

    rst <= '1','0' after (CK_PERIOD/5);
    clk_m <= not clk_m after (CK_PERIOD/2);

    -- Affecter des entr�es sur la sortie : test des interruptions
    io_output <= "00001ZZZ",
    		 "00010ZZZ" after 5*CK_PERIOD,
    		 "00001ZZZ" after 10*CK_PERIOD,
    		 "00010ZZZ" after 15*CK_PERIOD;


end sim1;

-- Configuration
configuration cf1_bch_gpio of bch_gpio is
    for sim1
        for all : gpio use entity work.gpio(RTL); end for;
    end for;
end cf1_bch_gpio;