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authorgalmes2004-03-30 10:57:06 +0000
committergalmes2004-03-30 10:57:06 +0000
commit0040e7dc7b9bddb7e6c8dce2347d0e198a198863 (patch)
tree56b80d8e274a6941e3ab42cfbe9d616719180c89 /2004/n/fpga/src/three-state/tristate.vhd
parentfb2d0d107767bf9d95f87542f9954f275e6f288a (diff)
Modifications du registre reg_rw et tristate pour synthétiser.
Diffstat (limited to '2004/n/fpga/src/three-state/tristate.vhd')
-rw-r--r--2004/n/fpga/src/three-state/tristate.vhd19
1 files changed, 2 insertions, 17 deletions
diff --git a/2004/n/fpga/src/three-state/tristate.vhd b/2004/n/fpga/src/three-state/tristate.vhd
index d3616f7..07e440e 100644
--- a/2004/n/fpga/src/three-state/tristate.vhd
+++ b/2004/n/fpga/src/three-state/tristate.vhd
@@ -18,8 +18,6 @@ use work.nono_const.all;
entity tristate is
port (
- rst : std_logic;
- clk : std_logic;
enable : in std_logic;
data_in : in T_DATA;
data_out : out T_DATA
@@ -28,19 +26,6 @@ end entity;
architecture RTL of tristate is
begin
- process (rst, clk)
- begin
- if (rst = '1') then
- data_out <= (others => 'Z');
- elsif (clk'event and clk = '1') then
- if (enable = '1') then
- data_out <= data_in;
- else
- data_out <= (others => 'Z');
- end if;
- end if;
- end process;
-
- -- partie combinatoire.
- --data_out <= data_in when (enable = '1') else (others => 'Z');
+ -- partie combinatoire.
+ data_out <= data_in when (enable = '1') else (others => 'Z');
end RTL;