From 0040e7dc7b9bddb7e6c8dce2347d0e198a198863 Mon Sep 17 00:00:00 2001 From: galmes Date: Tue, 30 Mar 2004 10:57:06 +0000 Subject: Modifications du registre reg_rw et tristate pour synthétiser. --- 2004/n/fpga/src/three-state/tristate.vhd | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) (limited to '2004/n/fpga/src/three-state/tristate.vhd') diff --git a/2004/n/fpga/src/three-state/tristate.vhd b/2004/n/fpga/src/three-state/tristate.vhd index d3616f7..07e440e 100644 --- a/2004/n/fpga/src/three-state/tristate.vhd +++ b/2004/n/fpga/src/three-state/tristate.vhd @@ -18,8 +18,6 @@ use work.nono_const.all; entity tristate is port ( - rst : std_logic; - clk : std_logic; enable : in std_logic; data_in : in T_DATA; data_out : out T_DATA @@ -28,19 +26,6 @@ end entity; architecture RTL of tristate is begin - process (rst, clk) - begin - if (rst = '1') then - data_out <= (others => 'Z'); - elsif (clk'event and clk = '1') then - if (enable = '1') then - data_out <= data_in; - else - data_out <= (others => 'Z'); - end if; - end if; - end process; - - -- partie combinatoire. - --data_out <= data_in when (enable = '1') else (others => 'Z'); + -- partie combinatoire. + data_out <= data_in when (enable = '1') else (others => 'Z'); end RTL; -- cgit v1.2.3