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-rw-r--r--common/include/asm/arch/hardware.h3
-rw-r--r--common/include/asm/arch/ips/wdt.h3
-rw-r--r--common/include/asm/arch/nvram.h171
-rw-r--r--common/include/asm/arch/spid_img_desc.h2
4 files changed, 175 insertions, 4 deletions
diff --git a/common/include/asm/arch/hardware.h b/common/include/asm/arch/hardware.h
index 44f58bedfa..03f9e4648d 100644
--- a/common/include/asm/arch/hardware.h
+++ b/common/include/asm/arch/hardware.h
@@ -21,6 +21,9 @@
#define __ASM_ARCH_HARDWARE_H
#include <asm/arch/ips/ips_access.h>
+
+#ifdef LINUX_COMPILE
#include <asm/arch/platform.h>
+#endif /* LINUX_COMPILE */
#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/common/include/asm/arch/ips/wdt.h b/common/include/asm/arch/ips/wdt.h
index d3eb59bd57..d4f574bfb0 100644
--- a/common/include/asm/arch/ips/wdt.h
+++ b/common/include/asm/arch/ips/wdt.h
@@ -84,7 +84,4 @@
( ((old) & ~(((1 << WDT_##name##_SIZE) - 1) << WDT_##name##_SHIFT)) \
| WDT_BF(name,value))
-#define WDT_DEFAULT_TIME 5 //seconds
-#define WDT_MAX_TIME 21 //seconds
-
#endif /* __ASM_ARCH_IPS_WDT_H */
diff --git a/common/include/asm/arch/nvram.h b/common/include/asm/arch/nvram.h
index 1b46f6e213..629aa5cc7f 100644
--- a/common/include/asm/arch/nvram.h
+++ b/common/include/asm/arch/nvram.h
@@ -31,6 +31,8 @@
MAX_INTERNAL_GPIOS : MIN_INTERNAL_GPIOS)
#define spc300_gpio_direction(gpio_allow_dir,num) ((gpio_allow_dir >> (num * 2)) & 0x3)
+#ifndef __ASSEMBLY__
+
enum spc300_gpio_direction_t
{
SPC300_GPIO_DIRECTION_NONE = 0,
@@ -131,6 +133,173 @@ static inline void spc300_nvram_copy(void* dst, void* src, unsigned int length)
}
}
}
-#endif
+#endif /* __KERNEL__ */
+
+#endif /* __ASSEMBLY__ */
+
+/* Offset fields. */
+#define NVRAM_MAGIC_OFFSET 0x0
+#define NVRAM_PKG_CFG_OFFSET 0x8
+#define NVRAM_GPIO_0_7_CFG_OFFSET 0xC
+#define NVRAM_GPIO_8_15_CFG_OFFSET 0x10
+#define NVRAM_GPIO_ALLOW_DIR_OFFSET 0x14
+#define NVRAM_SDRAM_CONFIG_OFFSET 0x18
+#define NVRAM_SDRAM_TIMING0_OFFSET 0x1C
+#define NVRAM_SDRAM_TIMING1_OFFSET 0x20
+#define NVRAM_SDRAM_REFRESH_OFFSET 0x24
+#define NVRAM_MIU_CONFIG_OFFSET 0x18
+#define NVRAM_MIU_RAM_SIZE_OFFSET 0x1C
+#define NVRAM_FLASH_ORG_OFFSET 0x28
+#define NVRAM_IMG_0_OFFSET_OFFSET 0x2C
+#define NVRAM_NB_IMAGES_OFFSET 0x30
+#define NVRAM_PRODUCT_NAME_OFFSET 0x34
+#define NVRAM_PRODUCT_PARTNB_OFFSET 0x74
+#define NVRAM_PRODUCT_DESC_OFFSET 0xB4
+#define NVRAM_SERIAL_NUMBER_OFFSET 0x134
+#define NVRAM_ETH_PHY_ADDR_OFFSET 0x174
+#define NVRAM_ETH_ADDRESS_OFFSET 0x178
+#define NVRAM_ETH_PORT_NB_OFFSET 0x17E
+#define NVRAM_RESERVED1_OFFSET 0x17F
+#define NVRAM_PLC_ADDRESS_OFFSET 0x180
+#define NVRAM_RESERVED2_OFFSET 0x186
+#define NVRAM_DEVICE_PASSWORD_OFFSET 0x188
+#define NVRAM_OEM_INFO_OFFSET 0x1A8
+#define NVRAM_TONEMASK_OFFSET 0x1E8
+#define NVRAM_MANUFACTORY_INFO_OFFSET 0x2A8
+#define NVRAM_IMG_MAX_SIZE_OFFSET 0x2E8
+#define NVRAM_CPU_PARTNB_OFFSET 0x2EC
+#define NVRAM_DYNAMIC_OFFSET 0x2F0
+
+/* Bitfields for pkg_cfg. */
+#define NVRAM_XCLK_SHIFT 0
+#define NVRAM_XCLK_MASK 0x3
+#define NVRAM_FREQ_SHIFT 2
+#define NVRAM_FREQ_MASK 0x3
+#define NVRAM_PIO_SHIFT 4
+#define NVRAM_PIO_MASK 0xF
+#define NVRAM_ETH_MODE_SHIFT 8
+#define NVRAM_ETH_MODE_MASK 0x3
+
+/* Values for pkg_cfg. */
+#define NVRAM_XCLK_1875 0
+#define NVRAM_XCLK_25 1
+#define NVRAM_XCLK_375 2
+#define NVRAM_FREQ_100 0
+#define NVRAM_FREQ_125 1
+#define NVRAM_FREQ_133 2
+#define NVRAM_FREQ_150 3
+#define NVRAM_ETH_MODE_MII 0
+#define NVRAM_ETH_MODE_RMII 1
+#define NVRAM_ETH_MODE_GMII 2
+
+#define NVRAM_GPIO_SHIFT 4
+#define NVRAM_GPIO_MASK 0xF
+/* Bitfields for gpio 0 to gpio 7. */
+#define NVRAM_GPIO_0_SHIFT 0
+#define NVRAM_GPIO_0_MASK 0xF
+#define NVRAM_GPIO_1_SHIFT 4
+#define NVRAM_GPIO_1_MASK 0xF
+#define NVRAM_GPIO_2_SHIFT 8
+#define NVRAM_GPIO_2_MASK 0xF
+#define NVRAM_GPIO_3_SHIFT 12
+#define NVRAM_GPIO_3_MASK 0xF
+#define NVRAM_GPIO_4_SHIFT 16
+#define NVRAM_GPIO_4_MASK 0xF
+#define NVRAM_GPIO_5_SHIFT 20
+#define NVRAM_GPIO_5_MASK 0xF
+#define NVRAM_GPIO_6_SHIFT 24
+#define NVRAM_GPIO_6_MASK 0xF
+#define NVRAM_GPIO_7_SHIFT 28
+#define NVRAM_GPIO_7_MASK 0xF
+
+/* Bitfields for gpio 8 to gpio 15. */
+#define NVRAM_GPIO_8_SHIFT 0
+#define NVRAM_GPIO_8_MASK 0xF
+#define NVRAM_GPIO_9_SHIFT 4
+#define NVRAM_GPIO_9_MASK 0xF
+#define NVRAM_GPIO_10_SHIFT 8
+#define NVRAM_GPIO_10_MASK 0xF
+#define NVRAM_GPIO_11_SHIFT 12
+#define NVRAM_GPIO_11_MASK 0xF
+#define NVRAM_GPIO_12_SHIFT 16
+#define NVRAM_GPIO_12_MASK 0xF
+#define NVRAM_GPIO_13_SHIFT 20
+#define NVRAM_GPIO_13_MASK 0xF
+#define NVRAM_GPIO_14_SHIFT 24
+#define NVRAM_GPIO_14_MASK 0xF
+#define NVRAM_GPIO_15_SHIFT 28
+#define NVRAM_GPIO_15_MASK 0xF
+
+/* Bitfields for gpio allowed direction. */
+#define NVRAM_GPIO_DIR_0_SHIFT 0
+#define NVRAM_GPIO_DIR_0_MASK 0x3
+#define NVRAM_GPIO_DIR_1_SHIFT 2
+#define NVRAM_GPIO_DIR_1_MASK 0x3
+#define NVRAM_GPIO_DIR_2_SHIFT 4
+#define NVRAM_GPIO_DIR_2_MASK 0x3
+#define NVRAM_GPIO_DIR_3_SHIFT 6
+#define NVRAM_GPIO_DIR_3_MASK 0x3
+#define NVRAM_GPIO_DIR_4_SHIFT 8
+#define NVRAM_GPIO_DIR_4_MASK 0x3
+#define NVRAM_GPIO_DIR_5_SHIFT 10
+#define NVRAM_GPIO_DIR_5_MASK 0x3
+#define NVRAM_GPIO_DIR_6_SHIFT 12
+#define NVRAM_GPIO_DIR_6_MASK 0x3
+#define NVRAM_GPIO_DIR_7_SHIFT 14
+#define NVRAM_GPIO_DIR_7_MASK 0x3
+#define NVRAM_GPIO_DIR_8_SHIFT 16
+#define NVRAM_GPIO_DIR_8_MASK 0x3
+#define NVRAM_GPIO_DIR_9_SHIFT 18
+#define NVRAM_GPIO_DIR_9_MASK 0x3
+#define NVRAM_GPIO_DIR_10_SHIFT 20
+#define NVRAM_GPIO_DIR_10_MASK 0x3
+#define NVRAM_GPIO_DIR_11_SHIFT 22
+#define NVRAM_GPIO_DIR_11_MASK 0x3
+#define NVRAM_GPIO_DIR_12_SHIFT 24
+#define NVRAM_GPIO_DIR_12_MASK 0x3
+#define NVRAM_GPIO_DIR_13_SHIFT 26
+#define NVRAM_GPIO_DIR_13_MASK 0x3
+#define NVRAM_GPIO_DIR_14_SHIFT 28
+#define NVRAM_GPIO_DIR_14_MASK 0x3
+#define NVRAM_GPIO_DIR_15_SHIFT 30
+#define NVRAM_GPIO_DIR_15_MASK 0x3
+
+/* Values for gpio allowed direction. */
+#define NVRAM_GPIO_DIR_NONE 0
+#define NVRAM_GPIO_DIR_IN 1
+#define NVRAM_GPIO_DIR_OUT 2
+#define NVRAM_GPIO_DIR_ALL 3
+
+/* Bitfields for flash organization. */
+#define NVRAM_FLASH_NB_SECT_SHIFT 0
+#define NVRAM_FLASH_NB_SECT_MASK 0xF
+#define NVRAM_FLASH_SECT_SZ_SHIFT 4
+#define NVRAM_FLASH_SECT_SZ_MASK 0xF
+
+/* Values for flash organization. */
+#define NVRAM_FLASH_1_SECT 0
+#define NVRAM_FLASH_2_SECT 1
+#define NVRAM_FLASH_4_SECT 2
+#define NVRAM_FLASH_8_SECT 3
+#define NVRAM_FLASH_16_SECT 4
+#define NVRAM_FLASH_32_SECT 5
+#define NVRAM_FLASH_64_SECT 6
+#define NVRAM_FLASH_128_SECT 7
+#define NVRAM_FLASH_256_SECT 8
+#define NVRAM_FLASH_512_SECT 9
+#define NVRAM_FLASH_SECT_64 0
+#define NVRAM_FLASH_SECT_128 1
+#define NVRAM_FLASH_SECT_256 2
+
+/* Bit manipulation macros. */
+#define NVRAM_BIT(name) \
+ (1 << NVRAM_##name##_SHIFT)
+#define NVRAM_BF(name,value) \
+ (((value) & (NVRAM_##name##_MASK)) << NVRAM_##name##_SHIFT)
+#define NVRAM_BFEXT(name,value) \
+ (((value) >> NVRAM_##name##_SHIFT) & (NVRAM_##name##_MASK))
+#define NVRAM_BFINS(name,value,old) \
+ ( ((old) & ~((NVRAM_##name##_MASK) << NVRAM_##name##_SHIFT)) \
+ | NVRAM_BF(name,value))
#endif /* __ASM_ARCH_NVRAM_H */
diff --git a/common/include/asm/arch/spid_img_desc.h b/common/include/asm/arch/spid_img_desc.h
index 91cec6d21c..2184fcc53b 100644
--- a/common/include/asm/arch/spid_img_desc.h
+++ b/common/include/asm/arch/spid_img_desc.h
@@ -20,7 +20,9 @@
#ifndef __ASM_ARCH_SPID_IMG_DESC_H
#define __ASM_ARCH_SPID_IMG_DESC_H
+#ifndef __KERNEL__
#include <stdint.h>
+#endif /* __KERNEL__ */
#define SPIDCOM_IMG_DESC_MTD_NAME_0 "image 0"
#define SPIDCOM_IMG_DESC_MTD_NAME_1 "image 1"