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-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S122
-rw-r--r--cleopatre/u-boot-1.1.6/include/configs/spc300_arch.h1
2 files changed, 62 insertions, 61 deletions
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S b/cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S
index 1b631c7216..7b1575d894 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S
@@ -86,9 +86,9 @@ pll_init:
/*
* Activate 3V3 in input clock buffer.
*/
- ldr r1, =MSEPLL_DPLL_BASE
- regbitclear r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_3V3_SHIFT, \
- MSEPLL_DPLL_CTRL_PD_3V3_MASK, r2, r3
+ ldr r1, =MSEAFE_BASE
+ regbitclear r1, MSEAFE_DPLL_CTRL_OFFSET, MSEAFE_DPLL_CTRL_PD_3V3_SHIFT, \
+ MSEAFE_DPLL_CTRL_PD_3V3_MASK, r2, r3
/*
* Bypass PLLs.
@@ -117,17 +117,17 @@ pll_init:
regbitset r1, MSEPLL_SPPLL_CTRL_OFFSET, MSEPLL_SPPLL_CTRL_PD_SHIFT, \
MSEPLL_SPPLL_CTRL_PD_MASK, r2, r3
/* DSP PLL */
- ldr r1, =MSEPLL_DPLL_BASE
- regbitset r1, MSEPLL_DPLL_CONF_OFFSET, MSEPLL_DPLL_CONF_PD_SHIFT, \
- MSEPLL_DPLL_CONF_PD_MASK, r2, r3
- regbitset r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_CLK_SHIFT, \
- MSEPLL_DPLL_CTRL_PD_CLK_MASK, r2, r3
- regbitset r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_DAC_CLK_OUT_SHIFT, \
- MSEPLL_DPLL_CTRL_PD_DAC_CLK_OUT_MASK, r2, r3
- regbitset r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_DAC_CLK_SHIFT, \
- MSEPLL_DPLL_CTRL_PD_DAC_CLK_MASK, r2, r3
- regbitset r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_ADC_CLK_SHIFT, \
- MSEPLL_DPLL_CTRL_PD_ADC_CLK_MASK, r2, r3
+ ldr r1, =MSEAFE_BASE
+ regbitset r1, MSEAFE_DPLL_CONF_OFFSET, MSEAFE_DPLL_CONF_PD_SHIFT, \
+ MSEAFE_DPLL_CONF_PD_MASK, r2, r3
+ regbitset r1, MSEAFE_DPLL_CTRL_OFFSET, MSEAFE_DPLL_CTRL_PD_CLK_SHIFT, \
+ MSEAFE_DPLL_CTRL_PD_CLK_MASK, r2, r3
+ regbitset r1, MSEAFE_DPLL_CTRL_OFFSET, MSEAFE_DPLL_CTRL_PD_DAC_CLK_OUT_SHIFT, \
+ MSEAFE_DPLL_CTRL_PD_DAC_CLK_OUT_MASK, r2, r3
+ regbitset r1, MSEAFE_DPLL_CTRL_OFFSET, MSEAFE_DPLL_CTRL_PD_DAC_CLK_SHIFT, \
+ MSEAFE_DPLL_CTRL_PD_DAC_CLK_MASK, r2, r3
+ regbitset r1, MSEAFE_DPLL_CTRL_OFFSET, MSEAFE_DPLL_CTRL_PD_ADC_CLK_SHIFT, \
+ MSEAFE_DPLL_CTRL_PD_ADC_CLK_MASK, r2, r3
/*
* Configure PLLs (while switched off).
@@ -170,27 +170,27 @@ pll_init:
str r2, [r1, #MSEPLL_SPPLL_CONF_OFFSET]
/* DSP PLL */
- ldr r1, =MSEPLL_DPLL_BASE
+ ldr r1, =MSEAFE_BASE
/* Config to have an ouptut clock at 300 MHz */
- ldr r2, [r1, #MSEPLL_DPLL_CTRL_OFFSET]
- bitinsert r2, MSEPLL_DPLL_CTRL_REF_DIV_MASK, MSEPLL_DPLL_CTRL_REF_DIV_SHIFT, \
- MSEPLL_DPLL_CTRL_REF_DIV_2, r3
- bitinsert r2, MSEPLL_DPLL_CTRL_ADC_DIV_MASK, MSEPLL_DPLL_CTRL_ADC_DIV_SHIFT, \
- MSEPLL_DPLL_CTRL_ADC_DIV_4, r3
- str r2, [r1, #MSEPLL_DPLL_CTRL_OFFSET]
+ ldr r2, [r1, #MSEAFE_DPLL_CTRL_OFFSET]
+ bitinsert r2, MSEAFE_DPLL_CTRL_REF_DIV_MASK, MSEAFE_DPLL_CTRL_REF_DIV_SHIFT, \
+ MSEAFE_DPLL_CTRL_REF_DIV_2, r3
+ bitinsert r2, MSEAFE_DPLL_CTRL_ADC_DIV_MASK, MSEAFE_DPLL_CTRL_ADC_DIV_SHIFT, \
+ MSEAFE_DPLL_CTRL_ADC_DIV_4, r3
+ str r2, [r1, #MSEAFE_DPLL_CTRL_OFFSET]
mov r2, #0
- mov r3, #MSEPLL_DPLL_LOOP_DIV_FIRST_2
- add r2, r2, r3, lsl #MSEPLL_DPLL_LOOP_DIV_FIRST_SHIFT
+ mov r3, #MSEAFE_DPLL_LOOP_DIV_FIRST_2
+ add r2, r2, r3, lsl #MSEAFE_DPLL_LOOP_DIV_FIRST_SHIFT
mov r3, #25
- add r2, r2, r3, lsl #MSEPLL_DPLL_LOOP_DIV_SECOND_SHIFT
- str r2, [r1, #MSEPLL_DPLL_LOOP_DIV_OFFSET]
- ldr r2, [r1, #MSEPLL_DPLL_CONF_OFFSET]
- bitinsert r2, MSEPLL_DPLL_CONF_DSP_DIV_MASK, MSEPLL_DPLL_CONF_DSP_DIV_SHIFT, \
- MSEPLL_DPLL_CONF_DSP_DIV_2, r3
- bitinsert r2, MSEPLL_DPLL_CONF_DAC_DIV_MASK, MSEPLL_DPLL_CONF_DAC_DIV_SHIFT, \
- MSEPLL_DPLL_CONF_DAC_DIV_2, r3
- bitinsert r2, MSEPLL_DPLL_CONF_ICP_MASK, MSEPLL_DPLL_CONF_ICP_SHIFT, 2, r3
- str r2, [r1, #MSEPLL_DPLL_CONF_OFFSET]
+ add r2, r2, r3, lsl #MSEAFE_DPLL_LOOP_DIV_SECOND_SHIFT
+ str r2, [r1, #MSEAFE_DPLL_LOOP_DIV_OFFSET]
+ ldr r2, [r1, #MSEAFE_DPLL_CONF_OFFSET]
+ bitinsert r2, MSEAFE_DPLL_CONF_DSP_DIV_MASK, MSEAFE_DPLL_CONF_DSP_DIV_SHIFT, \
+ MSEAFE_DPLL_CONF_DSP_DIV_2, r3
+ bitinsert r2, MSEAFE_DPLL_CONF_DAC_DIV_MASK, MSEAFE_DPLL_CONF_DAC_DIV_SHIFT, \
+ MSEAFE_DPLL_CONF_DAC_DIV_2, r3
+ bitinsert r2, MSEAFE_DPLL_CONF_ICP_MASK, MSEAFE_DPLL_CONF_ICP_SHIFT, 2, r3
+ str r2, [r1, #MSEAFE_DPLL_CONF_OFFSET]
b .Lendconf
200:
@@ -213,27 +213,27 @@ pll_init:
str r2, [r1, #MSEPLL_SPPLL_CONF_OFFSET]
/* DSP PLL */
- ldr r1, =MSEPLL_DPLL_BASE
+ ldr r1, =MSEAFE_BASE
/* Config to have an ouptut clock at 256 MHz */
- ldr r2, [r1, #MSEPLL_DPLL_CTRL_OFFSET]
- bitinsert r2, MSEPLL_DPLL_CTRL_REF_DIV_MASK, MSEPLL_DPLL_CTRL_REF_DIV_SHIFT, \
- MSEPLL_DPLL_CTRL_REF_DIV_2, r3
- bitinsert r2, MSEPLL_DPLL_CTRL_ADC_DIV_MASK, MSEPLL_DPLL_CTRL_ADC_DIV_SHIFT, \
- MSEPLL_DPLL_CTRL_ADC_DIV_6, r3
- str r2, [r1, #MSEPLL_DPLL_CTRL_OFFSET]
+ ldr r2, [r1, #MSEAFE_DPLL_CTRL_OFFSET]
+ bitinsert r2, MSEAFE_DPLL_CTRL_REF_DIV_MASK, MSEAFE_DPLL_CTRL_REF_DIV_SHIFT, \
+ MSEAFE_DPLL_CTRL_REF_DIV_2, r3
+ bitinsert r2, MSEAFE_DPLL_CTRL_ADC_DIV_MASK, MSEAFE_DPLL_CTRL_ADC_DIV_SHIFT, \
+ MSEAFE_DPLL_CTRL_ADC_DIV_6, r3
+ str r2, [r1, #MSEAFE_DPLL_CTRL_OFFSET]
mov r2, #0
- mov r3, #MSEPLL_DPLL_LOOP_DIV_FIRST_2
- add r2, r2, r3, lsl #MSEPLL_DPLL_LOOP_DIV_FIRST_SHIFT
+ mov r3, #MSEAFE_DPLL_LOOP_DIV_FIRST_2
+ add r2, r2, r3, lsl #MSEAFE_DPLL_LOOP_DIV_FIRST_SHIFT
mov r3, #32
- add r2, r2, r3, lsl #MSEPLL_DPLL_LOOP_DIV_SECOND_SHIFT
- str r2, [r1, #MSEPLL_DPLL_LOOP_DIV_OFFSET]
- ldr r2, [r1, #MSEPLL_DPLL_CONF_OFFSET]
- bitinsert r2, MSEPLL_DPLL_CONF_DSP_DIV_MASK, MSEPLL_DPLL_CONF_DSP_DIV_SHIFT, \
- MSEPLL_DPLL_CONF_DSP_DIV_3, r3
- bitinsert r2, MSEPLL_DPLL_CONF_DAC_DIV_MASK, MSEPLL_DPLL_CONF_DAC_DIV_SHIFT, \
- MSEPLL_DPLL_CONF_DAC_DIV_3, r3
- bitinsert r2, MSEPLL_DPLL_CONF_ICP_MASK, MSEPLL_DPLL_CONF_ICP_SHIFT, 3, r3
- str r2, [r1, #MSEPLL_DPLL_CONF_OFFSET]
+ add r2, r2, r3, lsl #MSEAFE_DPLL_LOOP_DIV_SECOND_SHIFT
+ str r2, [r1, #MSEAFE_DPLL_LOOP_DIV_OFFSET]
+ ldr r2, [r1, #MSEAFE_DPLL_CONF_OFFSET]
+ bitinsert r2, MSEAFE_DPLL_CONF_DSP_DIV_MASK, MSEAFE_DPLL_CONF_DSP_DIV_SHIFT, \
+ MSEAFE_DPLL_CONF_DSP_DIV_3, r3
+ bitinsert r2, MSEAFE_DPLL_CONF_DAC_DIV_MASK, MSEAFE_DPLL_CONF_DAC_DIV_SHIFT, \
+ MSEAFE_DPLL_CONF_DAC_DIV_3, r3
+ bitinsert r2, MSEAFE_DPLL_CONF_ICP_MASK, MSEAFE_DPLL_CONF_ICP_SHIFT, 3, r3
+ str r2, [r1, #MSEAFE_DPLL_CONF_OFFSET]
.Lendconf:
/*
@@ -249,17 +249,17 @@ pll_init:
regbitclear r1, MSEPLL_SPPLL_CTRL_OFFSET, MSEPLL_SPPLL_CTRL_PD_SHIFT, \
MSEPLL_SPPLL_CTRL_PD_MASK, r2, r3
/* DSP PLL */
- ldr r1, =MSEPLL_DPLL_BASE
- regbitclear r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_ADC_CLK_SHIFT, \
- MSEPLL_DPLL_CTRL_PD_ADC_CLK_MASK, r2, r3
- regbitclear r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_DAC_CLK_SHIFT, \
- MSEPLL_DPLL_CTRL_PD_DAC_CLK_MASK, r2, r3
- regbitclear r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_DAC_CLK_OUT_SHIFT, \
- MSEPLL_DPLL_CTRL_PD_DAC_CLK_OUT_MASK, r2, r3
- regbitclear r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_CLK_SHIFT, \
- MSEPLL_DPLL_CTRL_PD_CLK_MASK, r2, r3
- regbitclear r1, MSEPLL_DPLL_CONF_OFFSET, MSEPLL_DPLL_CONF_PD_SHIFT, \
- MSEPLL_DPLL_CONF_PD_MASK, r2, r3
+ ldr r1, =MSEAFE_BASE
+ regbitclear r1, MSEAFE_DPLL_CTRL_OFFSET, MSEAFE_DPLL_CTRL_PD_ADC_CLK_SHIFT, \
+ MSEAFE_DPLL_CTRL_PD_ADC_CLK_MASK, r2, r3
+ regbitclear r1, MSEAFE_DPLL_CTRL_OFFSET, MSEAFE_DPLL_CTRL_PD_DAC_CLK_SHIFT, \
+ MSEAFE_DPLL_CTRL_PD_DAC_CLK_MASK, r2, r3
+ regbitclear r1, MSEAFE_DPLL_CTRL_OFFSET, MSEAFE_DPLL_CTRL_PD_DAC_CLK_OUT_SHIFT, \
+ MSEAFE_DPLL_CTRL_PD_DAC_CLK_OUT_MASK, r2, r3
+ regbitclear r1, MSEAFE_DPLL_CTRL_OFFSET, MSEAFE_DPLL_CTRL_PD_CLK_SHIFT, \
+ MSEAFE_DPLL_CTRL_PD_CLK_MASK, r2, r3
+ regbitclear r1, MSEAFE_DPLL_CONF_OFFSET, MSEAFE_DPLL_CONF_PD_SHIFT, \
+ MSEAFE_DPLL_CONF_PD_MASK, r2, r3
/* active wait */
ldr r2, =PLL_WAIT_TIME
diff --git a/cleopatre/u-boot-1.1.6/include/configs/spc300_arch.h b/cleopatre/u-boot-1.1.6/include/configs/spc300_arch.h
index 4e88e8e6b8..9ef4b9368f 100644
--- a/cleopatre/u-boot-1.1.6/include/configs/spc300_arch.h
+++ b/cleopatre/u-boot-1.1.6/include/configs/spc300_arch.h
@@ -55,6 +55,7 @@
# define CONFIG_CHIP_FEATURE_MSEPLL 1
# define CONFIG_CHIP_FEATURE_IOMUX 1
# define CONFIG_CHIP_FEATURE_MSEETH 1
+# define CONFIG_AFE_MSEAFE 1
#else
# error "undefined chip"
#endif