summaryrefslogtreecommitdiff
path: root/cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S
blob: 1b631c72167dfc3108c58527007728e37a699d17 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
/*
 * cpu/spc300/msepll.S
 *
 * Copyright (C) 2012 SPiDCOM Technologies
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <config.h>

#if defined (CONFIG_CHIP_FEATURE_MSEPLL)

#include <asm/hardware.h>
#include <asm/arch/nvram.h>

/* Counter to repeat group of NB_INSTR instructions to reach 600uS time. */
/* (((time_to_wait * Xclk) / 1000000) / cpu_cycles_nb) */
#define PLL_WAIT_TIME   2880    /* (((600 * 24000000) / 1000000) / 5) */

    .file	"msepll.S"

    .text
    .arm                    @ This is ARM code; performs the same action as .code 32
    .align  2               @ Align to word boundary; "2" means the number of bits that must be zero
    .globl  pll_init
    .type   pll_init, %function

    /* This macro is used to clear bits in an IP register. */
    .macro regbitclear, base, offset, shift, mask, tmp1, tmp2
        ldr \tmp2, [\base, #\offset]
        mov \tmp1, #\mask
        mov \tmp1, \tmp1, lsl #\shift
        bic \tmp1, \tmp2, \tmp1
        str \tmp1, [\base, #\offset]
    .endm

    /* This macro is used to set bits in an IP register. */
    .macro regbitset, base, offset, shift, mask, tmp1, tmp2
        ldr \tmp2, [\base, #\offset]
        mov \tmp1, #\mask
        mov \tmp1, \tmp1, lsl #\shift
        orr \tmp1, \tmp2, \tmp1
        str \tmp1, [\base, #\offset]
    .endm

    /* This macro is used to insert bits in an ARM register. */
    .macro bitinsert baseval, mask, shift, value, tmp
        mov \tmp, #\mask
        mov \tmp, \tmp, lsl #\shift
        bic \baseval, \baseval, \tmp
        mov \tmp, #\value
        add \baseval, \baseval, \tmp, lsl #\shift
    .endm

    .macro waitstatus, base, offset, statval, tmp
1:
        ldr     \tmp, [\base, #\offset]
        cmp     \tmp, #\statval
        bne     1b
    .endm

    /*
     * PLL system set-up
     */
pll_init:
    /*
     * Find MSE500 mode from NVRAM.
     * NVRAM struct adress was passed to this function in r10.
     */
    ldr r0, [r10, #NVRAM_PKG_CFG_OFFSET]
    lsr r0, r0, #NVRAM_MSE500_MODE_SHIFT
    and r0, r0, #NVRAM_MSE500_MODE_MASK

    /*
     * Activate 3V3 in input clock buffer.
     */
    ldr r1, =MSEPLL_DPLL_BASE
    regbitclear r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_3V3_SHIFT, \
                MSEPLL_DPLL_CTRL_PD_3V3_MASK, r2, r3

    /*
     * Bypass PLLs.
     */
    ldr r1, =MARIA_REGBANK_BASE
    ldr r2, =PLL_CMD_BYPASS
    /* System PLL */
    str r2, [r1, #RB_SPLL_BYPASS_OFFSET]
    waitstatus r1, RB_SPLL_BYPASS_STAT_OFFSET, PLL_IS_BYPASS, r2
    /* Peripheral PLL */
    str r2, [r1, #RB_PPLL_BYPASS_OFFSET]
    waitstatus r1, RB_PPLL_BYPASS_STAT_OFFSET, PLL_IS_BYPASS, r2
    /* DSP PLL */
    str r2, [r1, #RB_DPLL_BYPASS_OFFSET]
    waitstatus r1, RB_DPLL_BYPASS_STAT_OFFSET, PLL_IS_BYPASS, r2

    /*
     * Switch OFF PLLs (before doing configuration).
     */
    /* System PLL */
    ldr r1, =MSEPLL_SPLL_BASE
    regbitset r1, MSEPLL_SPPLL_CTRL_OFFSET, MSEPLL_SPPLL_CTRL_PD_SHIFT, \
              MSEPLL_SPPLL_CTRL_PD_MASK, r2, r3
    /* Peripheral PLL */
    ldr r1, =MSEPLL_PPLL_BASE
    regbitset r1, MSEPLL_SPPLL_CTRL_OFFSET, MSEPLL_SPPLL_CTRL_PD_SHIFT, \
              MSEPLL_SPPLL_CTRL_PD_MASK, r2, r3
    /* DSP PLL */
    ldr r1, =MSEPLL_DPLL_BASE
    regbitset r1, MSEPLL_DPLL_CONF_OFFSET, MSEPLL_DPLL_CONF_PD_SHIFT, \
              MSEPLL_DPLL_CONF_PD_MASK, r2, r3
    regbitset r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_CLK_SHIFT, \
              MSEPLL_DPLL_CTRL_PD_CLK_MASK, r2, r3
    regbitset r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_DAC_CLK_OUT_SHIFT, \
              MSEPLL_DPLL_CTRL_PD_DAC_CLK_OUT_MASK, r2, r3
    regbitset r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_DAC_CLK_SHIFT, \
              MSEPLL_DPLL_CTRL_PD_DAC_CLK_MASK, r2, r3
    regbitset r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_ADC_CLK_SHIFT, \
              MSEPLL_DPLL_CTRL_PD_ADC_CLK_MASK, r2, r3

    /*
     * Configure PLLs (while switched off).
     */
    /* Peripheral PLL */
    ldr r1, =MSEPLL_PPLL_BASE
    regbitclear r1, MSEPLL_SPPLL_CTRL_OFFSET, MSEPLL_SPPLL_CTRL_VCO_DIV2_DIS_SHIFT, \
                MSEPLL_SPPLL_CTRL_VCO_DIV2_DIS_MASK, r2, r3
    /* Config to have an ouptut clock at 250 MHz */
    mov r2, #0
    mov r3, #MSEPLL_PPLL_CONF_INPUT_DIV_FIRST_3
    add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_INPUT_DIV_FIRST_SHIFT
    mov r3, #MSEPLL_PPLL_CONF_OUTPUT_DIV_FIRST_4
    add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_OUTPUT_DIV_FIRST_SHIFT
    mov r3, #MSEPLL_PPLL_CONF_LOOP_DIV_FIRST_5
    add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_LOOP_DIV_FIRST_SHIFT
    mov r3, #25
    add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_LOOP_DIV_SECOND_SHIFT
    str r2, [r1, #MSEPLL_SPPLL_CONF_OFFSET]

    /* Other PLL config depends on MSE500 mode (200 or else) */
    cmp r0, #NVRAM_MSE500_MODE_200
    beq 200f

    /* System PLL */
    ldr r1, =MSEPLL_SPLL_BASE
    regbitset r1, MSEPLL_SPPLL_CTRL_OFFSET, MSEPLL_SPPLL_CTRL_VCO_DIV2_DIS_SHIFT, \
              MSEPLL_SPPLL_CTRL_VCO_DIV2_DIS_MASK, r2, r3
    /* Config to have an ouptut clock at 492 MHz */
    mov r2, #0
    mov r3, #MSEPLL_SPLL_CONF_INPUT_DIV_FIRST_4
    add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_INPUT_DIV_FIRST_SHIFT
    str r2, [r1, #MSEPLL_SPPLL_CONF_OFFSET]
    mov r3, #MSEPLL_SPLL_CONF_OUTPUT_DIV_FIRST_2
    add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_OUTPUT_DIV_FIRST_SHIFT
    mov r3, #MSEPLL_SPLL_CONF_LOOP_DIV_FIRST_2
    add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_LOOP_DIV_FIRST_SHIFT
    mov r3, #41
    add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_LOOP_DIV_SECOND_SHIFT
    str r2, [r1, #MSEPLL_SPPLL_CONF_OFFSET]

    /* DSP PLL */
    ldr r1, =MSEPLL_DPLL_BASE
    /* Config to have an ouptut clock at 300 MHz */
    ldr r2, [r1, #MSEPLL_DPLL_CTRL_OFFSET]
    bitinsert r2, MSEPLL_DPLL_CTRL_REF_DIV_MASK, MSEPLL_DPLL_CTRL_REF_DIV_SHIFT, \
              MSEPLL_DPLL_CTRL_REF_DIV_2, r3
    bitinsert r2, MSEPLL_DPLL_CTRL_ADC_DIV_MASK, MSEPLL_DPLL_CTRL_ADC_DIV_SHIFT, \
              MSEPLL_DPLL_CTRL_ADC_DIV_4, r3
    str r2, [r1, #MSEPLL_DPLL_CTRL_OFFSET]
    mov r2, #0
    mov r3, #MSEPLL_DPLL_LOOP_DIV_FIRST_2
    add r2, r2, r3, lsl #MSEPLL_DPLL_LOOP_DIV_FIRST_SHIFT
    mov r3, #25
    add r2, r2, r3, lsl #MSEPLL_DPLL_LOOP_DIV_SECOND_SHIFT
    str r2, [r1, #MSEPLL_DPLL_LOOP_DIV_OFFSET]
    ldr r2, [r1, #MSEPLL_DPLL_CONF_OFFSET]
    bitinsert r2, MSEPLL_DPLL_CONF_DSP_DIV_MASK, MSEPLL_DPLL_CONF_DSP_DIV_SHIFT, \
              MSEPLL_DPLL_CONF_DSP_DIV_2, r3
    bitinsert r2, MSEPLL_DPLL_CONF_DAC_DIV_MASK, MSEPLL_DPLL_CONF_DAC_DIV_SHIFT, \
              MSEPLL_DPLL_CONF_DAC_DIV_2, r3
    bitinsert r2, MSEPLL_DPLL_CONF_ICP_MASK, MSEPLL_DPLL_CONF_ICP_SHIFT, 2, r3
    str r2, [r1, #MSEPLL_DPLL_CONF_OFFSET]
    b .Lendconf

200:
    /* For MSE500-200 mode */
    /* System PLL */
    ldr r1, =MSEPLL_SPLL_BASE
    regbitclear r1, MSEPLL_SPPLL_CTRL_OFFSET, MSEPLL_SPPLL_CTRL_VCO_DIV2_DIS_SHIFT, \
                MSEPLL_SPPLL_CTRL_VCO_DIV2_DIS_MASK, r2, r3
    /* Config to have an ouptut clock at 192 MHz */
    mov r2, #0
    mov r3, #MSEPLL_SPLL_CONF_INPUT_DIV_FIRST_4
    add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_INPUT_DIV_FIRST_SHIFT
    str r2, [r1, #MSEPLL_SPPLL_CONF_OFFSET]
    mov r3, #MSEPLL_SPLL_CONF_OUTPUT_DIV_FIRST_2
    add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_OUTPUT_DIV_FIRST_SHIFT
    mov r3, #MSEPLL_SPLL_CONF_LOOP_DIV_FIRST_2
    add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_LOOP_DIV_FIRST_SHIFT
    mov r3, #32
    add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_LOOP_DIV_SECOND_SHIFT
    str r2, [r1, #MSEPLL_SPPLL_CONF_OFFSET]

    /* DSP PLL */
    ldr r1, =MSEPLL_DPLL_BASE
    /* Config to have an ouptut clock at 256 MHz */
    ldr r2, [r1, #MSEPLL_DPLL_CTRL_OFFSET]
    bitinsert r2, MSEPLL_DPLL_CTRL_REF_DIV_MASK, MSEPLL_DPLL_CTRL_REF_DIV_SHIFT, \
              MSEPLL_DPLL_CTRL_REF_DIV_2, r3
    bitinsert r2, MSEPLL_DPLL_CTRL_ADC_DIV_MASK, MSEPLL_DPLL_CTRL_ADC_DIV_SHIFT, \
              MSEPLL_DPLL_CTRL_ADC_DIV_6, r3
    str r2, [r1, #MSEPLL_DPLL_CTRL_OFFSET]
    mov r2, #0
    mov r3, #MSEPLL_DPLL_LOOP_DIV_FIRST_2
    add r2, r2, r3, lsl #MSEPLL_DPLL_LOOP_DIV_FIRST_SHIFT
    mov r3, #32
    add r2, r2, r3, lsl #MSEPLL_DPLL_LOOP_DIV_SECOND_SHIFT
    str r2, [r1, #MSEPLL_DPLL_LOOP_DIV_OFFSET]
    ldr r2, [r1, #MSEPLL_DPLL_CONF_OFFSET]
    bitinsert r2, MSEPLL_DPLL_CONF_DSP_DIV_MASK, MSEPLL_DPLL_CONF_DSP_DIV_SHIFT, \
              MSEPLL_DPLL_CONF_DSP_DIV_3, r3
    bitinsert r2, MSEPLL_DPLL_CONF_DAC_DIV_MASK, MSEPLL_DPLL_CONF_DAC_DIV_SHIFT, \
              MSEPLL_DPLL_CONF_DAC_DIV_3, r3
    bitinsert r2, MSEPLL_DPLL_CONF_ICP_MASK, MSEPLL_DPLL_CONF_ICP_SHIFT, 3, r3
    str r2, [r1, #MSEPLL_DPLL_CONF_OFFSET]

.Lendconf:
    /*
     * Switch ON PLLs and wait 200uS (or more)
     * until they stabilize
     */
    /* System PLL */
    ldr r1, =MSEPLL_SPLL_BASE
    regbitclear r1, MSEPLL_SPPLL_CTRL_OFFSET, MSEPLL_SPPLL_CTRL_PD_SHIFT, \
                MSEPLL_SPPLL_CTRL_PD_MASK, r2, r3
    /* Peripheral PLL */
    ldr r1, =MSEPLL_PPLL_BASE
    regbitclear r1, MSEPLL_SPPLL_CTRL_OFFSET, MSEPLL_SPPLL_CTRL_PD_SHIFT, \
                MSEPLL_SPPLL_CTRL_PD_MASK, r2, r3
    /* DSP PLL */
    ldr r1, =MSEPLL_DPLL_BASE
    regbitclear r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_ADC_CLK_SHIFT, \
                MSEPLL_DPLL_CTRL_PD_ADC_CLK_MASK, r2, r3
    regbitclear r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_DAC_CLK_SHIFT, \
                MSEPLL_DPLL_CTRL_PD_DAC_CLK_MASK, r2, r3
    regbitclear r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_DAC_CLK_OUT_SHIFT, \
                MSEPLL_DPLL_CTRL_PD_DAC_CLK_OUT_MASK, r2, r3
    regbitclear r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_CLK_SHIFT, \
                MSEPLL_DPLL_CTRL_PD_CLK_MASK, r2, r3
    regbitclear r1, MSEPLL_DPLL_CONF_OFFSET, MSEPLL_DPLL_CONF_PD_SHIFT, \
                MSEPLL_DPLL_CONF_PD_MASK, r2, r3

    /* active wait */
    ldr r2, =PLL_WAIT_TIME
1:
    sub r2, r2, #1
    cmp r2, #0
    bne 1b

    /*
     * Switch to PLL clock
     */
    ldr r1, =MARIA_REGBANK_BASE
    ldr r2, =PLL_CMD_PLL

    /* System PLL */
    str r2, [r1, #RB_SPLL_BYPASS_OFFSET]
    waitstatus r1, RB_SPLL_BYPASS_STAT_OFFSET, PLL_IS_PLL, r2

    /* Peripheral PLL */
    str r2, [r1, #RB_PPLL_BYPASS_OFFSET]
    waitstatus r1, RB_PPLL_BYPASS_STAT_OFFSET, PLL_IS_PLL, r2

    /* DSP PLL */
    str r2, [r1, #RB_DPLL_BYPASS_OFFSET]
    waitstatus r1, RB_DPLL_BYPASS_STAT_OFFSET, PLL_IS_PLL, r2

    /* back to my caller */
    mov	pc, lr

#endif /* CONFIG_CHIP_FEATURE_MSEPLL */