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Diffstat (limited to 'cleopatre/u-boot-1.1.6/cpu/spc300')
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/masterclk.c14
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S34
2 files changed, 0 insertions, 48 deletions
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/masterclk.c b/cleopatre/u-boot-1.1.6/cpu/spc300/masterclk.c
index 1e843acc7e..c86e2c8a69 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/masterclk.c
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/masterclk.c
@@ -42,19 +42,6 @@ ulong get_master_clock(void)
bd_t *bd = gd->bd;
spidcom_nvram_t *nvram = (spidcom_nvram_t*)bd->bi_nvram_addr;
-#ifdef CONFIG_CHIP_MSE500
- switch(NVRAM_BFEXT(MSE500_MODE, nvram->pkg_cfg))
- {
- case NVRAM_MSE500_MODE_200:
- masterclk = 96000000;
- break;
- case NVRAM_MSE500_MODE_300:
- case NVRAM_MSE500_MODE_500:
- default:
- masterclk = 246000000;
- break;
- }
-#else
switch(NVRAM_BFEXT(FREQ, nvram->pkg_cfg))
{
case NVRAM_FREQ_100:
@@ -71,7 +58,6 @@ ulong get_master_clock(void)
masterclk = 147000000;
break;
}
-#endif /* CONFIG_CHIP_MSE500 */
#endif /* CONFIG_CHIP_FEATURE_FIXED_MASTER_CLOCK */
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S b/cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S
index 7e0e79ab67..703d4752b4 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S
@@ -67,14 +67,6 @@
*/
pll_init:
/*
- * Find MSE500 mode from NVRAM.
- * NVRAM struct adress was passed to this function in r10.
- */
- ldr r0, [r10, #NVRAM_PKG_CFG_OFFSET]
- lsr r0, r0, #NVRAM_MSE500_MODE_SHIFT
- and r0, r0, #NVRAM_MSE500_MODE_MASK
-
- /*
* Activate 3V3 in input clock buffer.
*/
ldr r1, =MSEAFE_BASE
@@ -128,10 +120,6 @@ pll_init:
add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_LOOP_DIV_SECOND_SHIFT
str r2, [r1, #MSEPLL_SPPLL_CONF_OFFSET]
- /* Other PLL config depends on MSE500 mode (200 or else) */
- cmp r0, #NVRAM_MSE500_MODE_200
- beq 200f
-
/* System PLL */
ldr r1, =MSEPLL_SPLL_BASE
regbitset r1, MSEPLL_SPPLL_CTRL_OFFSET, MSEPLL_SPPLL_CTRL_VCO_DIV2_DIS_SHIFT, \
@@ -149,28 +137,6 @@ pll_init:
add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_LOOP_DIV_SECOND_SHIFT
str r2, [r1, #MSEPLL_SPPLL_CONF_OFFSET]
- b .Lendconf
-
-200:
- /* For MSE500-200 mode */
- /* System PLL */
- ldr r1, =MSEPLL_SPLL_BASE
- regbitclear r1, MSEPLL_SPPLL_CTRL_OFFSET, MSEPLL_SPPLL_CTRL_VCO_DIV2_DIS_SHIFT, \
- MSEPLL_SPPLL_CTRL_VCO_DIV2_DIS_MASK, r2, r3
- /* Config to have an ouptut clock at 192 MHz */
- mov r2, #0
- mov r3, #MSEPLL_SPLL_CONF_INPUT_DIV_FIRST_4
- add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_INPUT_DIV_FIRST_SHIFT
- str r2, [r1, #MSEPLL_SPPLL_CONF_OFFSET]
- mov r3, #MSEPLL_SPLL_CONF_OUTPUT_DIV_FIRST_2
- add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_OUTPUT_DIV_FIRST_SHIFT
- mov r3, #MSEPLL_SPLL_CONF_LOOP_DIV_FIRST_2
- add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_LOOP_DIV_FIRST_SHIFT
- mov r3, #32
- add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_LOOP_DIV_SECOND_SHIFT
- str r2, [r1, #MSEPLL_SPPLL_CONF_OFFSET]
-
-.Lendconf:
/*
* Switch ON PLLs and wait 200uS (or more)
* until they stabilize