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-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/Makefile2
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/iomux.S49
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/miu.S74
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/nvram_dyn_cfg.S107
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/start.S2
-rw-r--r--cleopatre/u-boot-1.1.6/include/configs/spc300_arch.h1
-rw-r--r--common/include/asm/arch/nvram.h34
-rw-r--r--common/tools/genNVRAM/genNVRAM.c328
-rw-r--r--common/tools/genNVRAM/nvram_mse500_simu.conf3
9 files changed, 400 insertions, 200 deletions
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile b/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile
index 34c636c1c2..c0210ae44c 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile
@@ -24,7 +24,7 @@ LIB = lib$(CPU).a
START = start.o
OBJS = interrupts.o cpu.o timer.o serial.o wdt.o
SOBJS = reset.o spcpll.o msepll.o eth_init.o nvram.o dsp.o sdram.o miu.o \
- spcpio.o
+ spcpio.o iomux.o
all: .depend $(START) $(LIB)
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/iomux.S b/cleopatre/u-boot-1.1.6/cpu/spc300/iomux.S
new file mode 100644
index 0000000000..80dcad9ae4
--- /dev/null
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/iomux.S
@@ -0,0 +1,49 @@
+/*
+ * cpu/spc300/iomux.S
+ *
+ * Copyright (C) 2012 SPiDCOM Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+/* Skip file if not using IOMUX IP. */
+#ifdef CONFIG_CHIP_FEATURE_IOMUX
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/nvram.h>
+
+#include "nvram_dyn_cfg.S"
+
+ .file "iomux.S"
+
+ .text
+ .arm @ This is ARM code; performs the same action as .code 32
+ .align 2 @ Align to word boundary; "2" means the number of bits that must be zero
+ .globl gpio_pio_init
+ .type gpio_pio_init, %function
+
+
+gpio_pio_init:
+ /* Load IOMUX config from NVRAM. */
+ read_dyn_cfg r10, IOMUX_BASE, NVRAM_IOMUX_CONFIG_OFFSET, \
+ r0, r1, r2, r3, r4, r5, r6
+
+ /* back to my caller */
+ mov pc, lr
+
+#endif /* CONFIG_CHIP_FEATURE_IOMUX */
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/miu.S b/cleopatre/u-boot-1.1.6/cpu/spc300/miu.S
index 3db3da95bc..e25f4ded65 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/miu.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/miu.S
@@ -26,6 +26,8 @@
/* Skip file if not using MIU controller. */
#ifdef CONFIG_CHIP_FEATURE_MIU_CTRL
+#include "nvram_dyn_cfg.S"
+
.file "miu.S"
.text
@@ -36,77 +38,11 @@
sdram_init:
- ldr r0, =MIU_BASE
- ldr r1, [r10, #NVRAM_MIU_CONFIG_OFFSET]
- lsr r2, r1, #16 /* r2: config size. */
- lsl r1, r1, #16
- lsrs r1, r1, #16 /* r1: offset in nvram. */
-1: beq 1b /* Infinite loop of death if no MIU config. */
-
-.Lwriteloop:
- /* Write registers according to config words.
- * Each config word is composed of:
- * - bit 31 to 16: an offset in word to add to MIU_BASE,
- * - bit 15 to 0: the value to write at this address. */
- ldr r3, [r10, r1, lsl #2]
- lsr r4, r3, #16
- lsl r4, r4, #2 /* r4: offset in byte. */
- lsl r3, r3, #16
- lsr r3, r3, #16 /* r3: value to write. */
-
- /* Check if r4 is a code op instead of an offset. */
- mov r5, #1
- lsl r5, #17
- tst r4, r5
- bne .Lcodeop
-
- /* Store value at offset. */
- str r3, [r0, r4]
-
-.Lloopnext:
- /* Go to the next offset/value pair in NVRAM. */
- add r1, r1, #1
- subs r2, r2, #1
- bne .Lwriteloop
- b .Lreturn
+ /* Load MIU config from NVRAM. */
+ read_dyn_cfg r10, MIU_BASE, NVRAM_MIU_CONFIG_OFFSET, \
+ r0, r1, r2, r3, r4, r5, r6
-.Lcodeop:
- /* Transform the code op into an offset in the code op table. */
- sub r4, r4, #NVRAM_MIU_WAIT_CODE_OP
- adr r5, .Lcodeoptable
- add pc, r5, r4
-
-.Lwait:
- /* Wait for a certain amount of time.
- * We have to convert value in us to clock cycles with the following
- * formula: (((time_to_wait * cpu_clk) / 1000000) / cpu_cycles_nb).
- * We make the calculus using a cpuclk of 492 MHz (max speed used). If
- * the actual speed is lower, wait will be longer but we consider that it
- * is not a problem.
- * The 3 instructions take 5 CPU cycles.
- * With cpu_clk = 492 MHz and cpu_cycles_nb = 5, we have to multiply the
- * initial value by (492000000 / 1000000) / 5 = 98.4, rounded to 99 */
- mov r4, #99
- mul r5, r3, r4
-1:
- sub r5, r5, #1
- cmp r5, #0
- bne 1b
- b .Lloopnext
-
-.Lwaitinitdone:
- /* Wait until init done. */
- ldr r3, [r0, #MIU_INIT_DONE_REG]
- tst r3, #(1 << MIU_INIT_DONE_BIT)
- beq .Lwaitinitdone
- b .Lloopnext
-
-.Lreturn:
/* Back to my caller. */
mov pc, lr
-.Lcodeoptable:
- b .Lwait
- b .Lwaitinitdone
-
#endif /* CONFIG_CHIP_FEATURE_MIU_CTRL */
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/nvram_dyn_cfg.S b/cleopatre/u-boot-1.1.6/cpu/spc300/nvram_dyn_cfg.S
new file mode 100644
index 0000000000..334505387c
--- /dev/null
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/nvram_dyn_cfg.S
@@ -0,0 +1,107 @@
+/*
+ * cpu/spc300/nvram_dyn_cfg.S
+ *
+ * Copyright (C) 2012 SPiDCOM Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/nvram.h>
+
+.Lcodeoptable:
+ b .Lwait
+ b .Lmiuwaitinitdone
+
+.macro read_dyn_cfg, nvram, ip, cfg_offset, tmp0, tmp1, tmp2, tmp3, tmp4, \
+ tmp5, tmp6
+ ldr \tmp0, =\ip
+ ldr \tmp1, [\nvram, #\cfg_offset]
+ lsrs \tmp2, \tmp1, #16 /* \tmp2: config size. */
+ beq .Lreturn /* config size = 0, nothing to do. */
+ lsl \tmp1, \tmp1, #16
+ lsrs \tmp1, \tmp1, #16 /* \tmp1: offset in nvram. */
+ beq .Lreturn /* config offset = 0, nothing to do. */
+
+.Lwriteloop:
+ /* Write registers according to config words.
+ * Each pair of config words is composed of:
+ * - word 0: offset in byte to add to \ip,
+ * - word 1:
+ * - bit 31 to 16: the mask of bits to write at this address,
+ * - bit 15 to 0: the value to write at this address. */
+ ldr \tmp3, [\nvram, \tmp1] /* \tmp3: offset. */
+ add \tmp1, \tmp1, #4
+ ldr \tmp4, [\nvram, \tmp1]
+ lsr \tmp5, \tmp4, #16 /* \tmp5: mask. */
+ lsl \tmp4, \tmp4, #16
+ lsr \tmp4, \tmp4, #16 /* \tmp4: value. */
+
+ /* Check if \tmp3 is a code op instead of an offset. */
+ lsrs \tmp6, \tmp3, #17
+ bne .Lcodeop
+
+ /* Mask value. */
+ and \tmp4, \tmp4, \tmp5
+ /* Load register at offset \tmp3. */
+ ldr \tmp6, [\tmp0, \tmp3]
+ /* Apply masked value. */
+ bic \tmp6, \tmp6, \tmp5
+ orr \tmp6, \tmp6, \tmp4
+ /* Store value at offset. */
+ str \tmp6, [\tmp0, \tmp3]
+
+.Lloopnext:
+ /* Go to the next triplet in NVRAM. */
+ add \tmp1, \tmp1, #4
+ subs \tmp2, \tmp2, #(2*4)
+ bne .Lwriteloop
+ b .Lreturn
+
+.Lcodeop:
+ /* Transform the code op into an offset in the code op table. */
+ sub \tmp3, \tmp3, #NVRAM_WAIT_CODE_OP
+ lsl \tmp3, \tmp3, #2
+ adr \tmp6, .Lcodeoptable
+ add pc, \tmp6, \tmp3
+
+.Lwait:
+ /* Wait for a certain amount of time.
+ * We have to convert value in us to clock cycles with the following
+ * formula: (((time_to_wait * cpu_clk) / 1000000) / cpu_cycles_nb).
+ * We make the calculus using a cpuclk of 492 MHz (max speed used). If
+ * the actual speed is lower, wait will be longer but we consider that it
+ * is not a problem.
+ * The 3 instructions take 5 CPU cycles.
+ * With cpu_clk = 492 MHz and cpu_cycles_nb = 5, we have to multiply the
+ * initial value by (492000000 / 1000000) / 5 = 98.4, rounded to 99 */
+ mov \tmp3, #99
+ mul \tmp3, \tmp4, \tmp3
+1:
+ sub \tmp3, \tmp3, #1
+ cmp \tmp3, #0
+ bne 1b
+ b .Lloopnext
+
+.Lmiuwaitinitdone:
+ /* Wait until init done. */
+ ldr \tmp3, [\tmp0, #MIU_INIT_DONE_REG]
+ tst \tmp3, #(1 << MIU_INIT_DONE_BIT)
+ beq .Lmiuwaitinitdone
+ b .Lloopnext
+
+.Lreturn:
+.endm
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
index 859d34a42c..ebb9330019 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
@@ -272,7 +272,7 @@ in_sdram:
*/
bl timer_clock_config /* we pass NVRAM addr in r10; do not corrupt r10 in this function */
-#if defined(CONFIG_CHIP_FEATURE_SPCPIO)
+#if defined(CONFIG_CHIP_FEATURE_SPCPIO) || defined(CONFIG_CHIP_FEATURE_IOMUX)
/*
* Configure GPIOs and PIO
* WARNING: NVRAM need to be found and put to r10
diff --git a/cleopatre/u-boot-1.1.6/include/configs/spc300_arch.h b/cleopatre/u-boot-1.1.6/include/configs/spc300_arch.h
index 64b3f8e17b..08c7366812 100644
--- a/cleopatre/u-boot-1.1.6/include/configs/spc300_arch.h
+++ b/cleopatre/u-boot-1.1.6/include/configs/spc300_arch.h
@@ -54,6 +54,7 @@
# define CONFIG_CHIP_FEATURE_FIXED_ARM_CLOCK 1
# define CONFIG_CHIP_MAX_MASTER_CLOCK 246000000
# define CONFIG_CHIP_FEATURE_MSEPLL 1
+# define CONFIG_CHIP_FEATURE_IOMUX 1
#else
# error "undefined chip"
#endif
diff --git a/common/include/asm/arch/nvram.h b/common/include/asm/arch/nvram.h
index 26726515b7..01f9a54dbe 100644
--- a/common/include/asm/arch/nvram.h
+++ b/common/include/asm/arch/nvram.h
@@ -68,8 +68,8 @@ typedef struct
uint32_t gpio_8_15_cfg; /* GPIO 8 to 15 configuration register */
} spcpio;
struct {
- uint16_t config_offset; /* Offset of IOMUX config in nvram */
- uint16_t config_size; /* Size of IOMUX config in words */
+ uint16_t config_offset; /* Offset of IOMUX config in nvram in bytes */
+ uint16_t config_size; /* Size of IOMUX config in bytes */
uint32_t reserved;
} iomux;
} io;
@@ -82,8 +82,8 @@ typedef struct
uint32_t refresh; /* SDRAM refresh register */
} sdram;
struct {
- uint16_t config_offset; /* Offset of MIU config in nvram */
- uint16_t config_size; /* Size of MIU config in words */
+ uint16_t config_offset; /* Offset of MIU config in nvram in bytes */
+ uint16_t config_size; /* Size of MIU config in bytes */
uint32_t ram_size; /* Size of MIU connected RAM in bytes */
uint32_t reserved[2];
} miu;
@@ -349,24 +349,26 @@ static inline void spidcom_nvram_copy(void* dst, void* src, unsigned int length)
| NVRAM_BF(name,value))
/*
- * MIU registers are loaded by uboot, using the informations in NVRAM.
- * NVRAM stores a 32 bits word for each pair offset/value used to configure MIU.
+ * MIU and IOMUX registers are loaded by uboot, using the informations in NVRAM.
+ * NVRAM stores two 32 bits words for each triplet offset/value/mask used to
+ * configure MIU and IOMUX (one 32 bits word for offset and two 16 bits words
+ * for value/mask).
* There are special offsets that are interpreted by uboot as commands,
- * see the defines below. In this case, value is interpreted as the code op
- * operand.
- * If someone wants to create new code op, be aware that they must be between
- * 0x20000 and 0x3fffc and 4 bytes aligned. Operands must be 16 bits max.
+ * see the defines below. In this case, value and mask are interpreted as
+ * code op operands.
+ * If someone wants to create new code op, be aware that they must be superior
+ * to 0x20000.
*/
/* Timed wait command.
- * Operand is the time to wait in us (max 65535 us) for a CPU running
+ * Operand1 is the time to wait in us (max 65535 us) for a CPU running
* at 492 MHz (max speed used). If CPU speed is lower, actual wait will be
- * longer. */
-#define NVRAM_MIU_WAIT_CODE_OP 0x20000
+ * longer.
+ * Operand2 is not used. */
+#define NVRAM_WAIT_CODE_OP 0x00020000
-/* Wait init done command.
+/* MIU wait init done command.
* No operand. */
-#define NVRAM_MIU_WAIT_INIT_DONE_CODE_OP 0x20004
-
+#define NVRAM_MIU_WAIT_INIT_DONE_CODE_OP 0x00020001
#endif /* __ASM_ARCH_NVRAM_H */
diff --git a/common/tools/genNVRAM/genNVRAM.c b/common/tools/genNVRAM/genNVRAM.c
index ae9ca6cf31..0cf83ea806 100644
--- a/common/tools/genNVRAM/genNVRAM.c
+++ b/common/tools/genNVRAM/genNVRAM.c
@@ -214,89 +214,148 @@ static uint32_t *nvram_dynamic = nvram.dynamic;
static enum
{
+ IO_NOINIT,
+ IO_GPIO,
+ IO_IOMUX,
+} io = IO_NOINIT;
+
+/*
+ * IOMUX configurations: triplet of offset, value, mask, where offset is
+ * relative to IOMUX_BASE.
+ */
+
+uint32_t iomux_config_bringup[] =
+{
+ 0x00000000, 0x0000, 0xFFFF,
+ 0x00000050, 0x1025, 0x1477,
+ 0x00000080, 0x0500, 0x0F00,
+ 0x00000084, 0x0002, 0x0002,
+ 0x0000003C, 0x0004, 0x0004,
+ 0x00000048, 0x000F, 0x000F,
+ (uint32_t)-1
+};
+
+uint32_t iomux_config_bringup_uart_leon[] =
+{
+ 0x00000000, 0x0000, 0xFFFF,
+ 0x00000050, 0x1025, 0x1477,
+ 0x00000080, 0x0500, 0x0F00,
+ 0x00000084, 0x0002, 0x0002,
+ 0x0000003C, 0x0004, 0x0004,
+ 0x00000048, 0x0010, 0x0010,
+ (uint32_t)-1
+};
+
+uint32_t iomux_config_bringup_dsu_uart_leon[] =
+{
+ 0x00000000, 0x0000, 0xFFFF,
+ 0x00000050, 0x1025, 0x1477,
+ 0x00000080, 0x0500, 0x0F00,
+ 0x00000084, 0x0002, 0x0002,
+ 0x0000003C, 0x0004, 0x0004,
+ 0x00000048, 0x0090, 0x0090,
+ (uint32_t)-1
+};
+
+struct iomux_config_table_t
+{
+ char *name;
+ uint32_t *config;
+};
+
+static const struct iomux_config_table_t iomux_config_table[] =
+{
+ { "bringup", iomux_config_bringup },
+ { "bringup_uart_leon", iomux_config_bringup_uart_leon },
+ { "bringup_dsu_uart_leon", iomux_config_bringup_dsu_uart_leon },
+ NULL
+};
+
+static enum
+{
DRAM_NOINIT,
DRAM_SDRAM,
DRAM_MIU,
} dram = DRAM_NOINIT;
/*
- * MIU configurations: pair of offset, value, where offset is relative to
- * MIU_BASE.
+ * MIU configurations: triplet of offset, value, mask, where offset is
+ * relative to MIU_BASE.
* There are special offsets that are interpreted by uboot as commands,
* see nvram.h.
*/
uint32_t miu_config_sdram_dini_64m[] =
{
- 0x0004, 0x00000894,
- 0x0008, 0x00000185,
- 0x000c, 0x00000120,
- 0x0020, 0x00000031,
- 0x00b4, 0x00002000,
- 0x003c, 0x00000c01,
- 0x003c, 0x00000c08,
- 0x0000, 0x00000008,
- 0x0000, 0x0000000c,
- 0x0000, 0x0000000e,
- 0x0000, 0x0000000f,
- NVRAM_MIU_WAIT_INIT_DONE_CODE_OP, 0,
+ 0x00000004, 0x0894, 0xFFFF,
+ 0x00000008, 0x0185, 0xFFFF,
+ 0x0000000c, 0x0120, 0xFFFF,
+ 0x00000020, 0x0031, 0xFFFF,
+ 0x000000b4, 0x2000, 0xFFFF,
+ 0x0000003c, 0x0c01, 0xFFFF,
+ 0x0000003c, 0x0c08, 0xFFFF,
+ 0x00000000, 0x0008, 0xFFFF,
+ 0x00000000, 0x000c, 0xFFFF,
+ 0x00000000, 0x000e, 0xFFFF,
+ 0x00000000, 0x000f, 0xFFFF,
+ NVRAM_MIU_WAIT_INIT_DONE_CODE_OP, 0, 0,
(uint32_t)-1
};
uint32_t miu_config_mt47h32m16[] =
{
- 0x003c, 0x0c01,
- 0x003c, 0x0c00,
- 0x008c, 0xFFFE,
- 0x0090, 0xFFFF,
- 0x0094, 0xFFFF,
- 0x0098, 0xFFFF,
- 0x008c, 0xFFFE,
- 0x10060, 0x8348,
- 0x10064, 0x0014,
- 0x10068, 0x0000,
- 0x1006c, 0x0000,
- 0x10040, 0x0000,
- 0x10010, 0x70ff,
- 0x100fc, 0x0000,
- NVRAM_MIU_WAIT_CODE_OP, 500,
- 0x0004, 0x0292,
- 0x0008, 0x008b,
- 0x000c, 0x1420,
- 0x0010, 0x1066,
- 0x0014, 0x1644,
- 0x0018, 0x7465,
- 0x001c, 0x204f,
- 0x0020, 0x0a62,
- 0x0024, 0x4004,
- 0x0028, 0x8000,
- 0x002c, 0xc000,
- 0x10000, 0x0010,
- 0x10070, 0x0033,
- 0x10074, 0x0000,
- 0x10004, 0x0000,
- 0x10008, 0x0000,
- 0x10078, 0x0200,
- 0x1007c, 0x0022,
- 0x1001c, 0x00a7,
- 0x100dc, 0x0055,
- 0x100d0, 0x004f,
- 0x100d4, 0x004f,
- 0x100a8, 0x0000,
- 0x003c, 0x0c01,
- 0x003c, 0x0c00,
- 0x10000, 0x0000,
- 0x10004, 0xaaaa,
- NVRAM_MIU_WAIT_CODE_OP, 1,
- 0x0000, 0x0000,
- 0x0000, 0x0008,
- 0x0000, 0x000c,
- NVRAM_MIU_WAIT_CODE_OP, 200,
- 0x0000, 0x000e,
- NVRAM_MIU_WAIT_CODE_OP, 500,
- 0x0000, 0x001f,
- NVRAM_MIU_WAIT_INIT_DONE_CODE_OP, 0,
- 0x008c, 0x0000,
+ 0x0000003c, 0x0c01, 0xFFFF,
+ 0x0000003c, 0x0c00, 0xFFFF,
+ 0x0000008c, 0xFFFE, 0xFFFF,
+ 0x00000090, 0xFFFF, 0xFFFF,
+ 0x00000094, 0xFFFF, 0xFFFF,
+ 0x00000098, 0xFFFF, 0xFFFF,
+ 0x0000008c, 0xFFFE, 0xFFFF,
+ 0x00010060, 0x8348, 0xFFFF,
+ 0x00010064, 0x0014, 0xFFFF,
+ 0x00010068, 0x0000, 0xFFFF,
+ 0x0001006c, 0x0000, 0xFFFF,
+ 0x00010040, 0x0000, 0xFFFF,
+ 0x00010010, 0x70ff, 0xFFFF,
+ 0x000100fc, 0x0000, 0xFFFF,
+ NVRAM_WAIT_CODE_OP, 500, 0,
+ 0x00000004, 0x0292, 0xFFFF,
+ 0x00000008, 0x008b, 0xFFFF,
+ 0x0000000c, 0x1420, 0xFFFF,
+ 0x00000010, 0x1066, 0xFFFF,
+ 0x00000014, 0x1644, 0xFFFF,
+ 0x00000018, 0x7465, 0xFFFF,
+ 0x0000001c, 0x204f, 0xFFFF,
+ 0x00000020, 0x0a62, 0xFFFF,
+ 0x00000024, 0x4004, 0xFFFF,
+ 0x00000028, 0x8000, 0xFFFF,
+ 0x0000002c, 0xc000, 0xFFFF,
+ 0x00010000, 0x0010, 0xFFFF,
+ 0x00010070, 0x0033, 0xFFFF,
+ 0x00010074, 0x0000, 0xFFFF,
+ 0x00010004, 0x0000, 0xFFFF,
+ 0x00010008, 0x0000, 0xFFFF,
+ 0x00010078, 0x0200, 0xFFFF,
+ 0x0001007c, 0x0022, 0xFFFF,
+ 0x0001001c, 0x00a7, 0xFFFF,
+ 0x000100dc, 0x0055, 0xFFFF,
+ 0x000100d0, 0x004f, 0xFFFF,
+ 0x000100d4, 0x004f, 0xFFFF,
+ 0x000100a8, 0x0000, 0xFFFF,
+ 0x0000003c, 0x0c01, 0xFFFF,
+ 0x0000003c, 0x0c00, 0xFFFF,
+ 0x00010000, 0x0000, 0xFFFF,
+ 0x00010004, 0xaaaa, 0xFFFF,
+ NVRAM_WAIT_CODE_OP, 1, 0,
+ 0x00000000, 0x0000, 0xFFFF,
+ 0x00000000, 0x0008, 0xFFFF,
+ 0x00000000, 0x000c, 0xFFFF,
+ NVRAM_WAIT_CODE_OP, 200, 0,
+ 0x00000000, 0x000e, 0xFFFF,
+ NVRAM_WAIT_CODE_OP, 500, 0,
+ 0x00000000, 0x001f, 0xFFFF,
+ NVRAM_MIU_WAIT_INIT_DONE_CODE_OP, 0, 0,
+ 0x0000008c, 0x0000, 0xFFFF,
(uint32_t)-1
};
@@ -344,6 +403,7 @@ static void print_usage(const char *cmd)
" [ --pkgcfg package number ] (300/500)\n"
" [ --gpio07 GPIO 0 to 7 config ] (300/500)\n"
" [ --gpio815 GPIO 8 to 15 config ] (300/500)\n"
+ " [ --iomux-config IOMUX config ] (500)\n"
" [ --gpiodir GPIO allowed directions ] (300/500)\n"
" [ --sconr SDRAM config register ] (300/500)\n"
" [ --stmg0r SDRAM timing0 register ] (300/500)\n"
@@ -495,16 +555,71 @@ static int parse_pkgcfg(char *arg)
return 0;
}
+static int parse_gpio_check(void)
+{
+ if (io != IO_NOINIT && io != IO_GPIO)
+ {
+ fprintf (stderr, "Several IO muxing configuration detected\n");
+ return -1;
+ }
+ else
+ {
+ io = IO_GPIO;
+ return 0;
+ }
+}
+
static int parse_gpio07(char *arg)
{
nvram.io.spcpio.gpio_0_7_cfg = (uint32_t)strtoul(arg, NULL, 0);
- return 0;
+ return parse_gpio_check();
}
static int parse_gpio815(char *arg)
{
nvram.io.spcpio.gpio_8_15_cfg = (uint32_t)strtoul(arg, NULL, 0);
- return 0;
+ return parse_gpio_check();
+}
+
+static void write_dynamic_config (uint16_t *config_offset, uint16_t *config_size,
+ uint32_t *config)
+{
+ *config_size = 0;
+ *config_offset = (uint32_t) ((uint8_t *) nvram_dynamic - (uint8_t *) &nvram);
+ /* Translate the configuration into NVRAM format, see nvram_dyn_cfg.S in
+ * u-boot. */
+ for ( ; *config != (uint32_t) -1; config += 3)
+ {
+ assert (!(config[1] & ~0xffff));
+ assert (!(config[2] & ~0xffff));
+ *nvram_dynamic++ = config[0];
+ *nvram_dynamic++ = (config[2] << 16) | config[1];
+ *config_size += 2 * sizeof (uint32_t);
+ }
+}
+
+static int parse_iomux_config(char *arg)
+{
+ if (io != IO_NOINIT)
+ {
+ fprintf (stderr, "Several IO muxing configuration detected\n");
+ return -1;
+ }
+ io = IO_IOMUX;
+ /* Lookup the requested config. */
+ const struct iomux_config_table_t *p;
+ for (p = iomux_config_table; p->name; p++)
+ {
+ if (strcmp(p->name, arg) == 0)
+ {
+ nvram.io.iomux.reserved = 0;
+ write_dynamic_config (&nvram.io.iomux.config_offset,
+ &nvram.io.iomux.config_size,
+ p->config);
+ return 0;
+ }
+ }
+ return -1;
}
static int parse_gpiodir(char *arg)
@@ -571,23 +686,12 @@ static int parse_miu_config(char *arg)
{
if (strcmp(p->name, arg) == 0)
{
- int size = 0;
- nvram.dram.miu.config_offset =
- (uint32_t) (nvram_dynamic - (uint32_t *) &nvram);
nvram.dram.miu.ram_size = p->ram_size;
nvram.dram.miu.reserved[0] = 0;
nvram.dram.miu.reserved[1] = 0;
- uint32_t *config;
- /* Translate the configuration into NVRAM format, see miu.S in
- * u-boot. */
- for (config = p->config; *config != (uint32_t) -1; config += 2)
- {
- assert (!(config[0] & ~0x3fffc));
- assert (!(config[1] & ~0xffff));
- *nvram_dynamic++ = (config[0] >> 2 << 16) | config[1];
- size++;
- }
- nvram.dram.miu.config_size = size;
+ write_dynamic_config (&nvram.dram.miu.config_offset,
+ &nvram.dram.miu.config_size,
+ p->config);
return 0;
}
}
@@ -798,6 +902,7 @@ struct parser parse_table[] =
{ "pkgcfg", parse_pkgcfg, NVRAM_TYPE_SPC300 | NVRAM_TYPE_MSE500 },
{ "gpio07", parse_gpio07, NVRAM_TYPE_SPC300 | NVRAM_TYPE_MSE500 },
{ "gpio815", parse_gpio815, NVRAM_TYPE_SPC300 | NVRAM_TYPE_MSE500 },
+ { "iomux_config", parse_iomux_config, NVRAM_TYPE_MSE500 },
{ "gpiodir", parse_gpiodir, NVRAM_TYPE_SPC300 | NVRAM_TYPE_MSE500 },
{ "sconr", parse_sdramcfg, NVRAM_TYPE_SPC300 | NVRAM_TYPE_MSE500 },
{ "stmg0r", parse_sdramtmg0, NVRAM_TYPE_SPC300 | NVRAM_TYPE_MSE500 },
@@ -887,35 +992,36 @@ int main(int argc, char **argv)
{ "pkgcfg", required_argument, NULL, 3 },
{ "gpio07", required_argument, NULL, 4 },
{ "gpio815", required_argument, NULL, 5 },
- { "gpiodir", required_argument, NULL, 6 },
- { "sconr", required_argument, NULL, 7 },
- { "stmg0r", required_argument, NULL, 8 },
- { "stmg1r", required_argument, NULL, 9 },
- { "srefr", required_argument, NULL, 10 },
- { "ssize", required_argument, NULL, 11 },
- { "miu-config", required_argument, NULL, 12 },
- { "forg", required_argument, NULL, 13 },
- { "img0off", required_argument, NULL, 14 },
- { "img1off", required_argument, NULL, 15 },
- { "nbimg", required_argument, NULL, 16 },
- { "name", required_argument, NULL, 17 },
- { "partnb", required_argument, NULL, 18 },
- { "desc", required_argument, NULL, 19 },
- { "serial", required_argument, NULL, 20 },
- { "phy", required_argument, NULL, 21 },
- { "ethernet", required_argument, NULL, 22 },
- { "plc", required_argument, NULL, 23 },
- { "dpw", required_argument, NULL, 24 },
- { "oem", required_argument, NULL, 25 },
- { "tonemask", required_argument, NULL, 26 },
- { "factory", required_argument, NULL, 27 },
- { "portnb", required_argument, NULL, 28 },
- { "imgmaxsize", required_argument, NULL, 29 },
- { "cpupartnb", required_argument, NULL, 30 },
- { "brdnb", required_argument, NULL, 31 },
- { "brddesc", required_argument, NULL, 32 },
- { "brdid", required_argument, NULL, 33 },
- { "afetype", required_argument, NULL, 34 },
+ { "iomux-config", required_argument, NULL, 6 },
+ { "gpiodir", required_argument, NULL, 7 },
+ { "sconr", required_argument, NULL, 8 },
+ { "stmg0r", required_argument, NULL, 9 },
+ { "stmg1r", required_argument, NULL, 10 },
+ { "srefr", required_argument, NULL, 11 },
+ { "ssize", required_argument, NULL, 12 },
+ { "miu-config", required_argument, NULL, 13 },
+ { "forg", required_argument, NULL, 14 },
+ { "img0off", required_argument, NULL, 15 },
+ { "img1off", required_argument, NULL, 16 },
+ { "nbimg", required_argument, NULL, 17 },
+ { "name", required_argument, NULL, 18 },
+ { "partnb", required_argument, NULL, 19 },
+ { "desc", required_argument, NULL, 20 },
+ { "serial", required_argument, NULL, 21 },
+ { "phy", required_argument, NULL, 22 },
+ { "ethernet", required_argument, NULL, 23 },
+ { "plc", required_argument, NULL, 24 },
+ { "dpw", required_argument, NULL, 25 },
+ { "oem", required_argument, NULL, 26 },
+ { "tonemask", required_argument, NULL, 27 },
+ { "factory", required_argument, NULL, 28 },
+ { "portnb", required_argument, NULL, 29 },
+ { "imgmaxsize", required_argument, NULL, 30 },
+ { "cpupartnb", required_argument, NULL, 31 },
+ { "brdnb", required_argument, NULL, 32 },
+ { "brddesc", required_argument, NULL, 33 },
+ { "brdid", required_argument, NULL, 34 },
+ { "afetype", required_argument, NULL, 35 },
{ 0, 0, 0, 0 }
};
diff --git a/common/tools/genNVRAM/nvram_mse500_simu.conf b/common/tools/genNVRAM/nvram_mse500_simu.conf
index f726e70088..3f03e42943 100644
--- a/common/tools/genNVRAM/nvram_mse500_simu.conf
+++ b/common/tools/genNVRAM/nvram_mse500_simu.conf
@@ -1,6 +1,5 @@
pkgcfg=0x0000300f
-gpio07=0x00000000
-gpio815=0x00000000
+iomux_config = bringup
gpiodir=0xffffffff
miu_config = mt47h32m16
forg=0x00000006