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/*
 *  include/asm/arch/nvram.h
 *
 *  Copyright (C) 2012 MStar Semiconductor.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
 */
#ifndef __ASM_ARCH_NVRAM_H
#define __ASM_ARCH_NVRAM_H

/* NVRAM integrity word */
#define SPC300_NVRAM_MAGIC      "NVRAM\0\0\0"
#define SPC200_NVRAM_MAGIC1     0x0000FEED
#define SPC200_NVRAM_MAGIC2     0xDEADBEEF
#define SPC200_NVRAM2_MAGIC     "NVRAM2\0\0"

#define NVRAM_IS_VALID(nvram)   (!memcmp((nvram)->magic, SPC300_NVRAM_MAGIC, 8))

#define NVRAM_MTD_NAME          "nvram"

/* GPIO common definitions */
#define MAX_INTERNAL_GPIOS 16
#define MIN_INTERNAL_GPIOS 8
#define spc300_gpio_max_nb(pkg_cfg) ((((pkg_cfg & 0x000000F0) >> 4) < 5) ? \
                                    MAX_INTERNAL_GPIOS : MIN_INTERNAL_GPIOS)
#define spc300_gpio_direction(gpio_allow_dir,num) ((gpio_allow_dir >> (num * 2)) & 0x3)

#ifndef __ASSEMBLY__

enum spc300_gpio_direction_t
{
    SPC300_GPIO_DIRECTION_NONE   = 0,
    SPC300_GPIO_DIRECTION_INPUT  = 1,
    SPC300_GPIO_DIRECTION_OUTPUT = 2,
    SPC300_GPIO_DIRECTION_BIDIR  = 3,
};

/*
 * MSE500 NVRAM is the concatenation of SPC300 and SPC200C NVRAMs.  We chose
 * this solution to avoid any modification in polux or cleopatre software and
 * limit them to genNVRAM.  As a consequence some informations are
 * duplicated, but, as we have way more flash memory dedicated to NVRAM than
 * needed, it is acceptable.
 */

/* /!\ All values are LITTLE-ENDIAN */
typedef struct
{
    /* SPC300 fields. */
#define SPC300_NVRAM_FIRST_FIELD_OFFSET ((uint32_t)(((spidcom_nvram_t *)(0))->magic))
    char            magic[8];              /* Magic number "NVRAM\0\0\0" */
    uint32_t        pkg_cfg;               /* Package configuration register */
    union {
        struct {
            uint32_t gpio_0_7_cfg;          /* GPIO 0 to 7 configuration register */
            uint32_t gpio_8_15_cfg;         /* GPIO 8 to 15 configuration register */
        } spcpio;
        struct {
            uint16_t config_offset;         /* Offset of IOMUX config in nvram */
            uint16_t config_size;           /* Size of IOMUX config in words */
            uint32_t reserved;
        } iomux;
    } io;
    uint32_t        gpio_allow_dir;        /* GPIO allowed directions 0:none 1:in 2:out 3:bi */
    union {
        struct {
            uint32_t config;                /* SDRAM configuration register */
            uint32_t timing0;               /* SDRAM timing register 0 */
            uint32_t timing1;               /* SDRAM timing register 1 */
            uint32_t refresh;               /* SDRAM refresh register */
        } sdram;
        struct {
            uint16_t config_offset;         /* Offset of MIU config in nvram */
            uint16_t config_size;           /* Size of MIU config in words */
            uint32_t ram_size;              /* Size of MIU connected RAM in bytes */
            uint32_t reserved[2];
        } miu;
    } dram;
    uint32_t        flash_org;             /* Flash organization */
    uint32_t        img_0_offset;          /* Offset of first image address */
    uint32_t        nb_images;             /* Max Number of Images present in flash */
    char            product_name[64];      /* Product short name in string format */
    char            product_partnb[64];    /* Product part number in string format */
    char            product_desc[128];     /* Product long description in string format */
    char            serial_number[64];     /* Product serial number in string format */
    uint32_t        eth_phy_addr;          /* Address of Ethernet PHY */
    unsigned char   eth_address[6];        /* Ethernet MAC address */
    unsigned char   eth_port_nb;           /* Ethernet port number */
    unsigned char   reserved1;
    unsigned char   plc_address[6];        /* PowerLine MAC address */
    unsigned char   reserved2[2];
    char            device_password[32];   /* HomePlugAV device unique password (DPW) */
    char            oem_info[64];          /* Additional information for OEM */
    unsigned char   tonemask[192];         /* HomePlugAV tonemask */
    char            manufactory_info[64];  /* Name of the product manufacturer */
    uint32_t        img_max_size;          /* Max size of an image in flash */
    uint32_t        cpu_partnb;            /* SPC3x0 partnb */
    uint32_t        dynamic[256];          /* Dynamic data (see miu_config) */
#define SPC300_NVRAM_LAST_FIELD_OFFSET ((uint32_t)(((spidcom_nvram_t *)(0))->dynamic) + 256 * sizeof (uint32_t))

#ifdef CONFIG_CHIP_FEATURE_EXTRA_NVRAM_FIELDS
    /* SPC200 fields. */
#define SPC200_NVRAM_FIRST_FIELD_OFFSET ((uint32_t)&(((spidcom_nvram_t *)(0))->magicWord1))
    uint32_t        magicWord1;
    uint32_t        magicWord2;
    uint32_t        boardNumber;           /* board Number */
    char            serialNumber[64];      /* serial number as tagged on the board */
    char            sysDescr[256];         /* system description */
    char            ethPhysAddress[6];     /* MAC Address */
    char            plcPhysAddress[6];     /* MAC Address */
    char            reserved[8];
    char            magicNvram2[8];        /* 0x4e565241 0x4d320000  "NVRAM2" */
    char            boardDesc[16];         /* board description string */
    uint32_t        boardId;               /* board identification number */
    char            vendorInfo[64];        /* vendor additional info (OEM) */
    uint32_t        sdramSize;             /* size of SDRAM in MBytes */
    unsigned char   *imageOffset0;         /* address of image #0 in flash */
    unsigned char   *imageOffset1;         /* address of image #1 in flash */
    uint32_t        afeType;               /* Type of AFE design */
    uint32_t        ethPortNum;            /* Number of the eth port */
    char            manufactoryInfo[64];   /* manufactory info string */
#define SPC200_NVRAM_LAST_FIELD_OFFSET ((uint32_t)(((spidcom_nvram_t *)(0))->manufactoryInfo) + 64 * sizeof (char))
#endif /* CONFIG_CHIP_FEATURE_EXTRA_NVRAM_FIELDS */
} spidcom_nvram_t; //Currently __attribute__((packed)) not needed

/* genNVRAM needs to know the sizes of the "sub-NVRAMs".  But, as we only have
 * one structure now, we can not use a sizeof anymore. */
#define SPC300_NVRAM_SIZE (SPC300_NVRAM_LAST_FIELD_OFFSET - SPC300_NVRAM_FIRST_FIELD_OFFSET)
#define SPC200_NVRAM_SIZE (SPC200_NVRAM_LAST_FIELD_OFFSET - SPC200_NVRAM_FIRST_FIELD_OFFSET)

#ifdef __KERNEL__
extern spidcom_nvram_t spidcom_nvram;

static inline void spidcom_nvram_copy(void* dst, void* src, unsigned int length)
{
    unsigned int burst, rest, i;
    unsigned long *src32, *dst32;
    unsigned char *src8, *dst8;

    src32 = (unsigned long*)src;
    dst32 = (unsigned long*)dst;
    burst = length / 4;
    rest = length % 4;

    for(i=0 ; i<burst ; i++)
    {
        *dst32 = *src32;
        dst32++;
        src32++;
    }
    if(rest)
    {
        src8 = (unsigned char*)src32;
        dst8 = (unsigned char*)dst32;
        for(i=0 ; i<rest ; i++)
        {
            *dst8 = *src8;
            dst8++;
            src8++;
        }
    }
}
#endif /* __KERNEL__ */

#endif /* __ASSEMBLY__ */

/* Offset fields. */
#define NVRAM_MAGIC_OFFSET              0x0
#define NVRAM_PKG_CFG_OFFSET            0x8
#define NVRAM_GPIO_0_7_CFG_OFFSET       0xC
#define NVRAM_GPIO_8_15_CFG_OFFSET      0x10
#define NVRAM_IOMUX_CONFIG_OFFSET       0xC
#define NVRAM_GPIO_ALLOW_DIR_OFFSET     0x14
#define NVRAM_SDRAM_CONFIG_OFFSET       0x18
#define NVRAM_SDRAM_TIMING0_OFFSET      0x1C
#define NVRAM_SDRAM_TIMING1_OFFSET      0x20
#define NVRAM_SDRAM_REFRESH_OFFSET      0x24
#define NVRAM_MIU_CONFIG_OFFSET         0x18
#define NVRAM_MIU_RAM_SIZE_OFFSET       0x1C
#define NVRAM_FLASH_ORG_OFFSET          0x28
#define NVRAM_IMG_0_OFFSET_OFFSET       0x2C
#define NVRAM_NB_IMAGES_OFFSET          0x30
#define NVRAM_PRODUCT_NAME_OFFSET       0x34
#define NVRAM_PRODUCT_PARTNB_OFFSET     0x74
#define NVRAM_PRODUCT_DESC_OFFSET       0xB4
#define NVRAM_SERIAL_NUMBER_OFFSET      0x134
#define NVRAM_ETH_PHY_ADDR_OFFSET       0x174
#define NVRAM_ETH_ADDRESS_OFFSET        0x178
#define NVRAM_ETH_PORT_NB_OFFSET        0x17E
#define NVRAM_RESERVED1_OFFSET          0x17F
#define NVRAM_PLC_ADDRESS_OFFSET        0x180
#define NVRAM_RESERVED2_OFFSET          0x186
#define NVRAM_DEVICE_PASSWORD_OFFSET    0x188
#define NVRAM_OEM_INFO_OFFSET           0x1A8
#define NVRAM_TONEMASK_OFFSET           0x1E8
#define NVRAM_MANUFACTORY_INFO_OFFSET   0x2A8
#define NVRAM_IMG_MAX_SIZE_OFFSET       0x2E8
#define NVRAM_CPU_PARTNB_OFFSET         0x2EC
#define NVRAM_DYNAMIC_OFFSET            0x2F0

/* Bitfields for pkg_cfg. */
#define NVRAM_XCLK_SHIFT                0
#define NVRAM_XCLK_MASK                 0x3
#define NVRAM_FREQ_SHIFT                2
#define NVRAM_FREQ_MASK                 0x3
#define NVRAM_PIO_SHIFT                 4
#define NVRAM_PIO_MASK                  0xF
#define NVRAM_ETH_MODE_SHIFT            8
#define NVRAM_ETH_MODE_MASK             0x3
#define NVRAM_MSE500_MODE_SHIFT         12
#define NVRAM_MSE500_MODE_MASK          0x3

/* Values for pkg_cfg. */
#define NVRAM_XCLK_1875                 0
#define NVRAM_XCLK_25                   1
#define NVRAM_XCLK_375                  2
#define NVRAM_XCLK_MSE500               3
#define NVRAM_FREQ_100                  0
#define NVRAM_FREQ_125                  1
#define NVRAM_FREQ_133                  2
#define NVRAM_FREQ_150                  3
#define NVRAM_ETH_MODE_MII              0
#define NVRAM_ETH_MODE_RMII             1
#define NVRAM_ETH_MODE_GMII             2
#define NVRAM_MSE500_MODE_200           1
#define NVRAM_MSE500_MODE_300           2
#define NVRAM_MSE500_MODE_500           3

#define NVRAM_GPIO_SHIFT                4
#define NVRAM_GPIO_MASK                 0xF
/* Bitfields for gpio 0 to gpio 7. */
#define NVRAM_GPIO_0_SHIFT              0
#define NVRAM_GPIO_0_MASK               0xF
#define NVRAM_GPIO_1_SHIFT              4
#define NVRAM_GPIO_1_MASK               0xF
#define NVRAM_GPIO_2_SHIFT              8
#define NVRAM_GPIO_2_MASK               0xF
#define NVRAM_GPIO_3_SHIFT              12
#define NVRAM_GPIO_3_MASK               0xF
#define NVRAM_GPIO_4_SHIFT              16
#define NVRAM_GPIO_4_MASK               0xF
#define NVRAM_GPIO_5_SHIFT              20
#define NVRAM_GPIO_5_MASK               0xF
#define NVRAM_GPIO_6_SHIFT              24
#define NVRAM_GPIO_6_MASK               0xF
#define NVRAM_GPIO_7_SHIFT              28
#define NVRAM_GPIO_7_MASK               0xF

/* Bitfields for gpio 8 to gpio 15. */
#define NVRAM_GPIO_8_SHIFT              0
#define NVRAM_GPIO_8_MASK               0xF
#define NVRAM_GPIO_9_SHIFT              4
#define NVRAM_GPIO_9_MASK               0xF
#define NVRAM_GPIO_10_SHIFT             8
#define NVRAM_GPIO_10_MASK              0xF
#define NVRAM_GPIO_11_SHIFT             12
#define NVRAM_GPIO_11_MASK              0xF
#define NVRAM_GPIO_12_SHIFT             16
#define NVRAM_GPIO_12_MASK              0xF
#define NVRAM_GPIO_13_SHIFT             20
#define NVRAM_GPIO_13_MASK              0xF
#define NVRAM_GPIO_14_SHIFT             24
#define NVRAM_GPIO_14_MASK              0xF
#define NVRAM_GPIO_15_SHIFT             28
#define NVRAM_GPIO_15_MASK              0xF

/* Bitfields for gpio allowed direction. */
#define NVRAM_GPIO_DIR_0_SHIFT          0
#define NVRAM_GPIO_DIR_0_MASK           0x3
#define NVRAM_GPIO_DIR_1_SHIFT          2
#define NVRAM_GPIO_DIR_1_MASK           0x3
#define NVRAM_GPIO_DIR_2_SHIFT          4
#define NVRAM_GPIO_DIR_2_MASK           0x3
#define NVRAM_GPIO_DIR_3_SHIFT          6
#define NVRAM_GPIO_DIR_3_MASK           0x3
#define NVRAM_GPIO_DIR_4_SHIFT          8
#define NVRAM_GPIO_DIR_4_MASK           0x3
#define NVRAM_GPIO_DIR_5_SHIFT          10
#define NVRAM_GPIO_DIR_5_MASK           0x3
#define NVRAM_GPIO_DIR_6_SHIFT          12
#define NVRAM_GPIO_DIR_6_MASK           0x3
#define NVRAM_GPIO_DIR_7_SHIFT          14
#define NVRAM_GPIO_DIR_7_MASK           0x3
#define NVRAM_GPIO_DIR_8_SHIFT          16
#define NVRAM_GPIO_DIR_8_MASK           0x3
#define NVRAM_GPIO_DIR_9_SHIFT          18
#define NVRAM_GPIO_DIR_9_MASK           0x3
#define NVRAM_GPIO_DIR_10_SHIFT         20
#define NVRAM_GPIO_DIR_10_MASK          0x3
#define NVRAM_GPIO_DIR_11_SHIFT         22
#define NVRAM_GPIO_DIR_11_MASK          0x3
#define NVRAM_GPIO_DIR_12_SHIFT         24
#define NVRAM_GPIO_DIR_12_MASK          0x3
#define NVRAM_GPIO_DIR_13_SHIFT         26
#define NVRAM_GPIO_DIR_13_MASK          0x3
#define NVRAM_GPIO_DIR_14_SHIFT         28
#define NVRAM_GPIO_DIR_14_MASK          0x3
#define NVRAM_GPIO_DIR_15_SHIFT         30
#define NVRAM_GPIO_DIR_15_MASK          0x3

/* Values for gpio allowed direction. */
#define NVRAM_GPIO_DIR_NONE             0
#define NVRAM_GPIO_DIR_IN               1
#define NVRAM_GPIO_DIR_OUT              2
#define NVRAM_GPIO_DIR_ALL              3

/* Bitfields for flash organization. */
#define NVRAM_FLASH_NB_SECT_SHIFT       0
#define NVRAM_FLASH_NB_SECT_MASK        0xF
#define NVRAM_FLASH_SECT_SZ_SHIFT       4
#define NVRAM_FLASH_SECT_SZ_MASK        0xF

/* Values for flash organization. */
#define NVRAM_FLASH_1_SECT              0
#define NVRAM_FLASH_2_SECT              1
#define NVRAM_FLASH_4_SECT              2
#define NVRAM_FLASH_8_SECT              3
#define NVRAM_FLASH_16_SECT             4
#define NVRAM_FLASH_32_SECT             5
#define NVRAM_FLASH_64_SECT             6
#define NVRAM_FLASH_128_SECT            7
#define NVRAM_FLASH_256_SECT            8
#define NVRAM_FLASH_512_SECT            9
#define NVRAM_FLASH_SECT_64             0
#define NVRAM_FLASH_SECT_128            1
#define NVRAM_FLASH_SECT_256            2

/* Bit manipulation macros. */
#define NVRAM_BIT(name) \
    (1 << NVRAM_##name##_SHIFT)
#define NVRAM_BF(name,value) \
    (((value) & (NVRAM_##name##_MASK)) << NVRAM_##name##_SHIFT)
#define NVRAM_BFEXT(name,value) \
    (((value) >> NVRAM_##name##_SHIFT) & (NVRAM_##name##_MASK))
#define NVRAM_BFINS(name,value,old) \
    ( ((old) & ~((NVRAM_##name##_MASK) << NVRAM_##name##_SHIFT)) \
      | NVRAM_BF(name,value))

/*
 * MIU registers are loaded by uboot, using the informations in NVRAM.
 * NVRAM stores a 32 bits word for each pair offset/value used to configure MIU.
 * There are special offsets that are interpreted by uboot as commands,
 * see the defines below. In this case, value is interpreted as the code op
 * operand.
 * If someone wants to create new code op, be aware that they must be between
 * 0x20000 and 0x3fffc and 4 bytes aligned. Operands must be 16 bits max.
 */

/* Timed wait command.
 * Operand is the time to wait in us (max 65535 us) for a CPU running
 * at 492 MHz (max speed used). If CPU speed is lower, actual wait will be
 * longer. */
#define NVRAM_MIU_WAIT_CODE_OP 0x20000

/* Wait init done command.
 * No operand. */
#define NVRAM_MIU_WAIT_INIT_DONE_CODE_OP 0x20004


#endif  /* __ASM_ARCH_NVRAM_H */