summaryrefslogtreecommitdiff
path: root/common
diff options
context:
space:
mode:
authorCyril Jourdan2012-09-20 09:18:49 +0200
committerCyril Jourdan2012-09-20 09:43:00 +0200
commit196b6d9d440236f2b1372dad4744f1e82bcffbb6 (patch)
tree9936b62875a086cb6d96a219ba1f853686231813 /common
parenta576516df91a2f56f1f8ab838385e65ed0956b9c (diff)
common/inc/asm/arch: handle a 64 lines version of the GIC, refs #3119
Diffstat (limited to 'common')
-rw-r--r--common/include/asm/arch/ips/gic.h81
-rw-r--r--common/include/asm/arch/irqs.h4
2 files changed, 77 insertions, 8 deletions
diff --git a/common/include/asm/arch/ips/gic.h b/common/include/asm/arch/ips/gic.h
index 5b2448b31a..ba76e904a5 100644
--- a/common/include/asm/arch/ips/gic.h
+++ b/common/include/asm/arch/ips/gic.h
@@ -22,15 +22,30 @@
#include <asm/arch/ips/ips_access.h>
+#ifdef CONFIG_CHIP_FEATURE_GIC_64_LINES
+# define GIC_LINES_NB 64
+#else
+# define GIC_LINES_NB 32
+#endif
+
#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+#ifdef CONFIG_CHIP_FEATURE_GIC_64_LINES
+typedef uint64_t lines_reg_t;
+#else
+typedef uint32_t lines_reg_t;
+#endif
+
/** Virtual Address for gic */
-#define IRQ_INTEN_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_INTEN_OFFSET)))
-#define IRQ_INTMASK_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_INTMASK_OFFSET)))
-#define IRQ_INTFORCE_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_INTFORCE_OFFSET)))
-#define IRQ_RAWSTATUS_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_RAWSTATUS_OFFSET)))
-#define IRQ_STATUS_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_STATUS_OFFSET)))
-#define IRQ_MASKSTATUS_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_MASKSTATUS_OFFSET)))
-#define IRQ_FINALSTATUS_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_FINALSTATUS_OFFSET)))
+#define IRQ_INTEN_VA (*((volatile lines_reg_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_INTEN_OFFSET)))
+#define IRQ_INTMASK_VA (*((volatile lines_reg_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_INTMASK_OFFSET)))
+#define IRQ_INTFORCE_VA (*((volatile lines_reg_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_INTFORCE_OFFSET)))
+#define IRQ_RAWSTATUS_VA (*((volatile lines_reg_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_RAWSTATUS_OFFSET)))
+#define IRQ_STATUS_VA (*((volatile lines_reg_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_STATUS_OFFSET)))
+#define IRQ_MASKSTATUS_VA (*((volatile lines_reg_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_MASKSTATUS_OFFSET)))
+#define IRQ_FINALSTATUS_VA (*((volatile lines_reg_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_FINALSTATUS_OFFSET)))
#define FIQ_INTEN_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + FIQ_INTEN_OFFSET)))
#define FIQ_INTMASK_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + FIQ_INTMASK_OFFSET)))
#define FIQ_INTFORCE_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + FIQ_INTFORCE_OFFSET)))
@@ -71,7 +86,59 @@
#define IRQ_P29_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P29_OFFSET)))
#define IRQ_P30_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P30_OFFSET)))
#define IRQ_P31_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P31_OFFSET)))
+
+#ifdef CONFIG_CHIP_FEATURE_GIC_64_LINES
+#define IRQ_P32_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P32_OFFSET)))
+#define IRQ_P33_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P33_OFFSET)))
+#define IRQ_P34_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P34_OFFSET)))
+#define IRQ_P35_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P35_OFFSET)))
+#define IRQ_P36_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P36_OFFSET)))
+#define IRQ_P37_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P37_OFFSET)))
+#define IRQ_P38_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P38_OFFSET)))
+#define IRQ_P39_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P39_OFFSET)))
+#define IRQ_P40_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P40_OFFSET)))
+#define IRQ_P41_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P41_OFFSET)))
+#define IRQ_P42_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P42_OFFSET)))
+#define IRQ_P43_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P43_OFFSET)))
+#define IRQ_P44_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P44_OFFSET)))
+#define IRQ_P45_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P45_OFFSET)))
+#define IRQ_P46_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P46_OFFSET)))
+#define IRQ_P47_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P47_OFFSET)))
+#define IRQ_P48_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P48_OFFSET)))
+#define IRQ_P49_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P49_OFFSET)))
+#define IRQ_P50_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P50_OFFSET)))
+#define IRQ_P51_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P51_OFFSET)))
+#define IRQ_P52_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P52_OFFSET)))
+#define IRQ_P53_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P53_OFFSET)))
+#define IRQ_P54_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P54_OFFSET)))
+#define IRQ_P55_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P55_OFFSET)))
+#define IRQ_P56_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P56_OFFSET)))
+#define IRQ_P57_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P57_OFFSET)))
+#define IRQ_P58_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P58_OFFSET)))
+#define IRQ_P59_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P59_OFFSET)))
+#define IRQ_P60_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P60_OFFSET)))
+#define IRQ_P61_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P61_OFFSET)))
+#define IRQ_P62_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P62_OFFSET)))
+#define IRQ_P63_ADDR_VA (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P63_OFFSET)))
+#endif /* CONFIG_CHIP_FEATURE_GIC_64_LINES */
+
#define IRQ_PRIO_ADDR_VA ((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P0_OFFSET))
+
#endif /* __ASSEMBLY__ */
+/** Enable an IRQ. */
+#define IRQ_ENABLE(num) (IRQ_INTEN_VA |= (((lines_reg_t) 1) << (num)))
+/** Disable an IRQ. */
+#define IRQ_DISABLE(num) (IRQ_INTEN_VA &= ~(((lines_reg_t) 1) << (num)))
+
+/** Force an IRQ. */
+#define IRQ_FORCE(num) (IRQ_INTFORCE_VA |= (((lines_reg_t) 1) << (num)))
+/** Clear an IRQ that has been forced. */
+#define IRQ_FORCE_CLEAR(num) (IRQ_INTFORCE_VA &= ~(((lines_reg_t) 1) << (num)))
+
+/** Get Raw Status for a defined IRQ. */
+#define IRQ_GET_RAWSTATUS(num) (IRQ_RAWSTATUS_VA & (((lines_reg_t) 1) << (num)) ? 1 : 0)
+/** Get Status for a defined IRQ. */
+#define IRQ_GET_STATUS(num) (IRQ_STATUS_VA & (((lines_reg_t) 1) << (num)) ? 1 : 0)
+
#endif /* __ASM_ARCH_IPS_GIC_H */
diff --git a/common/include/asm/arch/irqs.h b/common/include/asm/arch/irqs.h
index a915359465..b86301240d 100644
--- a/common/include/asm/arch/irqs.h
+++ b/common/include/asm/arch/irqs.h
@@ -20,6 +20,8 @@
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
+#include <asm/arch/ips/gic.h>
+
#if defined (CONFIG_CHIP_FEATURE_INT_MAP_V1)
#define INT_TIMER_1 0
@@ -138,7 +140,7 @@
# error "no irqs definition"
#endif
-#define NR_IRQS 32
+#define NR_IRQS GIC_LINES_NB
#ifndef NO_IRQ
#define NO_IRQ ((unsigned int)(-1))