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/*
 *  include/asm/arch/ips/gic.h
 *
 *  Copyright (C) 2012 MStar Semiconductor.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
 */
#ifndef __ASM_ARCH_IPS_GIC_H
#define __ASM_ARCH_IPS_GIC_H

#include <asm/arch/ips/ips_access.h>

#ifdef CONFIG_CHIP_FEATURE_GIC_64_LINES
#   define GIC_LINES_NB 64
#else
#   define GIC_LINES_NB 32
#endif

#ifndef __ASSEMBLY__

#include <linux/types.h>

#ifdef CONFIG_CHIP_FEATURE_GIC_64_LINES
typedef uint64_t lines_reg_t;
#else
typedef uint32_t lines_reg_t;
#endif

/** Virtual Address for gic */
#define IRQ_INTEN_VA         (*((volatile lines_reg_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_INTEN_OFFSET)))
#define IRQ_INTMASK_VA       (*((volatile lines_reg_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_INTMASK_OFFSET)))
#define IRQ_INTFORCE_VA      (*((volatile lines_reg_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_INTFORCE_OFFSET)))
#define IRQ_RAWSTATUS_VA     (*((volatile lines_reg_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_RAWSTATUS_OFFSET)))
#define IRQ_STATUS_VA        (*((volatile lines_reg_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_STATUS_OFFSET)))
#define IRQ_MASKSTATUS_VA    (*((volatile lines_reg_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_MASKSTATUS_OFFSET)))
#define IRQ_FINALSTATUS_VA   (*((volatile lines_reg_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_FINALSTATUS_OFFSET)))
#define FIQ_INTEN_VA         (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + FIQ_INTEN_OFFSET)))
#define FIQ_INTMASK_VA       (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + FIQ_INTMASK_OFFSET)))
#define FIQ_INTFORCE_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + FIQ_INTFORCE_OFFSET)))
#define FIQ_RAWSTATUS_VA     (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + FIQ_RAWSTATUS_OFFSET)))
#define FIQ_STATUS_VA        (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + FIQ_STATUS_OFFSET)))
#define FIQ_FINALSTATUS_VA   (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + FIQ_FINALSTATUS_OFFSET)))
#define IRQ_PLEVEL_VA        (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_PLEVEL_OFFSET)))
#define ICTL_VERSION_ID_VA   (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + ICTL_VERSION_ID_OFFSET)))
#define IRQ_P0_ADDR_VA       (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P0_OFFSET)))
#define IRQ_P1_ADDR_VA       (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P1_OFFSET)))
#define IRQ_P2_ADDR_VA       (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P2_OFFSET)))
#define IRQ_P3_ADDR_VA       (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P3_OFFSET)))
#define IRQ_P4_ADDR_VA       (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P4_OFFSET)))
#define IRQ_P5_ADDR_VA       (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P5_OFFSET)))
#define IRQ_P6_ADDR_VA       (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P6_OFFSET)))
#define IRQ_P7_ADDR_VA       (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P7_OFFSET)))
#define IRQ_P8_ADDR_VA       (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P8_OFFSET)))
#define IRQ_P9_ADDR_VA       (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P9_OFFSET)))
#define IRQ_P10_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P10_OFFSET)))
#define IRQ_P11_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P11_OFFSET)))
#define IRQ_P12_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P12_OFFSET)))
#define IRQ_P13_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P13_OFFSET)))
#define IRQ_P14_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P14_OFFSET)))
#define IRQ_P15_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P15_OFFSET)))
#define IRQ_P16_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P16_OFFSET)))
#define IRQ_P17_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P17_OFFSET)))
#define IRQ_P18_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P18_OFFSET)))
#define IRQ_P19_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P19_OFFSET)))
#define IRQ_P20_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P20_OFFSET)))
#define IRQ_P21_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P21_OFFSET)))
#define IRQ_P22_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P22_OFFSET)))
#define IRQ_P23_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P23_OFFSET)))
#define IRQ_P24_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P24_OFFSET)))
#define IRQ_P25_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P25_OFFSET)))
#define IRQ_P26_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P26_OFFSET)))
#define IRQ_P27_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P27_OFFSET)))
#define IRQ_P28_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P28_OFFSET)))
#define IRQ_P29_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P29_OFFSET)))
#define IRQ_P30_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P30_OFFSET)))
#define IRQ_P31_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P31_OFFSET)))

#ifdef CONFIG_CHIP_FEATURE_GIC_64_LINES
#define IRQ_P32_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P32_OFFSET)))
#define IRQ_P33_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P33_OFFSET)))
#define IRQ_P34_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P34_OFFSET)))
#define IRQ_P35_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P35_OFFSET)))
#define IRQ_P36_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P36_OFFSET)))
#define IRQ_P37_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P37_OFFSET)))
#define IRQ_P38_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P38_OFFSET)))
#define IRQ_P39_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P39_OFFSET)))
#define IRQ_P40_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P40_OFFSET)))
#define IRQ_P41_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P41_OFFSET)))
#define IRQ_P42_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P42_OFFSET)))
#define IRQ_P43_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P43_OFFSET)))
#define IRQ_P44_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P44_OFFSET)))
#define IRQ_P45_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P45_OFFSET)))
#define IRQ_P46_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P46_OFFSET)))
#define IRQ_P47_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P47_OFFSET)))
#define IRQ_P48_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P48_OFFSET)))
#define IRQ_P49_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P49_OFFSET)))
#define IRQ_P50_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P50_OFFSET)))
#define IRQ_P51_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P51_OFFSET)))
#define IRQ_P52_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P52_OFFSET)))
#define IRQ_P53_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P53_OFFSET)))
#define IRQ_P54_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P54_OFFSET)))
#define IRQ_P55_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P55_OFFSET)))
#define IRQ_P56_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P56_OFFSET)))
#define IRQ_P57_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P57_OFFSET)))
#define IRQ_P58_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P58_OFFSET)))
#define IRQ_P59_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P59_OFFSET)))
#define IRQ_P60_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P60_OFFSET)))
#define IRQ_P61_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P61_OFFSET)))
#define IRQ_P62_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P62_OFFSET)))
#define IRQ_P63_ADDR_VA      (*((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P63_OFFSET)))
#endif /* CONFIG_CHIP_FEATURE_GIC_64_LINES */

#define IRQ_PRIO_ADDR_VA     ((volatile uint32_t *)(IO_ADDRESS(ARM_ICTL_BASE) + IRQ_P0_OFFSET))

#endif /* __ASSEMBLY__ */

/** Enable an IRQ. */
#define IRQ_ENABLE(num) (IRQ_INTEN_VA |= (((lines_reg_t) 1) << (num)))
/** Disable an IRQ. */
#define IRQ_DISABLE(num) (IRQ_INTEN_VA &= ~(((lines_reg_t) 1) << (num)))

/** Force an IRQ. */
#define IRQ_FORCE(num) (IRQ_INTFORCE_VA |= (((lines_reg_t) 1) << (num)))
/** Clear an IRQ that has been forced. */
#define IRQ_FORCE_CLEAR(num) (IRQ_INTFORCE_VA &= ~(((lines_reg_t) 1) << (num)))

/** Get Raw Status for a defined IRQ. */
#define IRQ_GET_RAWSTATUS(num) (IRQ_RAWSTATUS_VA & (((lines_reg_t) 1) << (num)) ? 1 : 0)
/** Get Status for a defined IRQ. */
#define IRQ_GET_STATUS(num) (IRQ_STATUS_VA & (((lines_reg_t) 1) << (num)) ? 1 : 0)

#endif /* __ASM_ARCH_IPS_GIC_H */