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authorCyril Jourdan2012-07-27 11:27:48 +0200
committerCyril Jourdan2012-09-20 11:21:04 +0200
commitebb68ff48dcd331fcb2031feb8d0ffe23352cd6d (patch)
tree7bc97c49efb4e8b7a40c2a2f2198b623fc868812 /cleopatre
parentaa818ab29b78d8d0e40ef0e7cf7f4a00e54f073b (diff)
{common,cleo}: remove MIU_ATOP_REG_BASE, refs #2961
As a consequence, MIU_REG_BASE is renamed into MIU_BASE.
Diffstat (limited to 'cleopatre')
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/miu.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/miu.S b/cleopatre/u-boot-1.1.6/cpu/spc300/miu.S
index ce69ae6892..29230778ee 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/miu.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/miu.S
@@ -35,7 +35,7 @@
sdram_init:
- ldr r0, =MIU_REG_BASE
+ ldr r0, =MIU_BASE
ldr r1, [r10, #NVRAM_MIU_CONFIG_OFFSET]
lsr r2, r1, #16 /* r2: config size. */
lsl r1, r1, #16
@@ -44,7 +44,7 @@ sdram_init:
1: /* Write registers according to config words.
* Each config word is composed of:
- * - bit 31 to 16: an offset in word to add to MIU_REG_BASE,
+ * - bit 31 to 16: an offset in word to add to MIU_BASE,
* - bit 15 to 0: the value to write at this address. */
ldr r3, [r10, r1, lsl #2]
lsr r4, r3, #16 /* r4: offset. */