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authorCyril Jourdan2012-07-27 10:19:19 +0200
committerCyril Jourdan2012-09-20 11:21:03 +0200
commitaa818ab29b78d8d0e40ef0e7cf7f4a00e54f073b (patch)
tree6726011bd50d0c28948bddd1764addc6f50abd2a /cleopatre
parent498daaa6874e18e45a29d8c83a13fefda46e3eae (diff)
cleo/uboot/cpu/spc300: add msepll.S, refs #2961
Diffstat (limited to 'cleopatre')
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/Makefile2
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S292
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/start.S2
-rw-r--r--cleopatre/u-boot-1.1.6/include/configs/spc300_arch.h1
4 files changed, 295 insertions, 2 deletions
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile b/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile
index 9708ed8daa..9ec087b628 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/Makefile
@@ -23,7 +23,7 @@ LIB = lib$(CPU).a
START = start.o
OBJS = interrupts.o cpu.o timer.o serial.o wdt.o
-SOBJS = reset.o spcpll.o eth_init.o nvram.o dsp.o sdram.o miu.o
+SOBJS = reset.o spcpll.o msepll.o eth_init.o nvram.o dsp.o sdram.o miu.o
all: .depend $(START) $(LIB)
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S b/cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S
new file mode 100644
index 0000000000..1b631c7216
--- /dev/null
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/msepll.S
@@ -0,0 +1,292 @@
+/*
+ * cpu/spc300/msepll.S
+ *
+ * Copyright (C) 2012 SPiDCOM Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+
+#if defined (CONFIG_CHIP_FEATURE_MSEPLL)
+
+#include <asm/hardware.h>
+#include <asm/arch/nvram.h>
+
+/* Counter to repeat group of NB_INSTR instructions to reach 600uS time. */
+/* (((time_to_wait * Xclk) / 1000000) / cpu_cycles_nb) */
+#define PLL_WAIT_TIME 2880 /* (((600 * 24000000) / 1000000) / 5) */
+
+ .file "msepll.S"
+
+ .text
+ .arm @ This is ARM code; performs the same action as .code 32
+ .align 2 @ Align to word boundary; "2" means the number of bits that must be zero
+ .globl pll_init
+ .type pll_init, %function
+
+ /* This macro is used to clear bits in an IP register. */
+ .macro regbitclear, base, offset, shift, mask, tmp1, tmp2
+ ldr \tmp2, [\base, #\offset]
+ mov \tmp1, #\mask
+ mov \tmp1, \tmp1, lsl #\shift
+ bic \tmp1, \tmp2, \tmp1
+ str \tmp1, [\base, #\offset]
+ .endm
+
+ /* This macro is used to set bits in an IP register. */
+ .macro regbitset, base, offset, shift, mask, tmp1, tmp2
+ ldr \tmp2, [\base, #\offset]
+ mov \tmp1, #\mask
+ mov \tmp1, \tmp1, lsl #\shift
+ orr \tmp1, \tmp2, \tmp1
+ str \tmp1, [\base, #\offset]
+ .endm
+
+ /* This macro is used to insert bits in an ARM register. */
+ .macro bitinsert baseval, mask, shift, value, tmp
+ mov \tmp, #\mask
+ mov \tmp, \tmp, lsl #\shift
+ bic \baseval, \baseval, \tmp
+ mov \tmp, #\value
+ add \baseval, \baseval, \tmp, lsl #\shift
+ .endm
+
+ .macro waitstatus, base, offset, statval, tmp
+1:
+ ldr \tmp, [\base, #\offset]
+ cmp \tmp, #\statval
+ bne 1b
+ .endm
+
+ /*
+ * PLL system set-up
+ */
+pll_init:
+ /*
+ * Find MSE500 mode from NVRAM.
+ * NVRAM struct adress was passed to this function in r10.
+ */
+ ldr r0, [r10, #NVRAM_PKG_CFG_OFFSET]
+ lsr r0, r0, #NVRAM_MSE500_MODE_SHIFT
+ and r0, r0, #NVRAM_MSE500_MODE_MASK
+
+ /*
+ * Activate 3V3 in input clock buffer.
+ */
+ ldr r1, =MSEPLL_DPLL_BASE
+ regbitclear r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_3V3_SHIFT, \
+ MSEPLL_DPLL_CTRL_PD_3V3_MASK, r2, r3
+
+ /*
+ * Bypass PLLs.
+ */
+ ldr r1, =MARIA_REGBANK_BASE
+ ldr r2, =PLL_CMD_BYPASS
+ /* System PLL */
+ str r2, [r1, #RB_SPLL_BYPASS_OFFSET]
+ waitstatus r1, RB_SPLL_BYPASS_STAT_OFFSET, PLL_IS_BYPASS, r2
+ /* Peripheral PLL */
+ str r2, [r1, #RB_PPLL_BYPASS_OFFSET]
+ waitstatus r1, RB_PPLL_BYPASS_STAT_OFFSET, PLL_IS_BYPASS, r2
+ /* DSP PLL */
+ str r2, [r1, #RB_DPLL_BYPASS_OFFSET]
+ waitstatus r1, RB_DPLL_BYPASS_STAT_OFFSET, PLL_IS_BYPASS, r2
+
+ /*
+ * Switch OFF PLLs (before doing configuration).
+ */
+ /* System PLL */
+ ldr r1, =MSEPLL_SPLL_BASE
+ regbitset r1, MSEPLL_SPPLL_CTRL_OFFSET, MSEPLL_SPPLL_CTRL_PD_SHIFT, \
+ MSEPLL_SPPLL_CTRL_PD_MASK, r2, r3
+ /* Peripheral PLL */
+ ldr r1, =MSEPLL_PPLL_BASE
+ regbitset r1, MSEPLL_SPPLL_CTRL_OFFSET, MSEPLL_SPPLL_CTRL_PD_SHIFT, \
+ MSEPLL_SPPLL_CTRL_PD_MASK, r2, r3
+ /* DSP PLL */
+ ldr r1, =MSEPLL_DPLL_BASE
+ regbitset r1, MSEPLL_DPLL_CONF_OFFSET, MSEPLL_DPLL_CONF_PD_SHIFT, \
+ MSEPLL_DPLL_CONF_PD_MASK, r2, r3
+ regbitset r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_CLK_SHIFT, \
+ MSEPLL_DPLL_CTRL_PD_CLK_MASK, r2, r3
+ regbitset r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_DAC_CLK_OUT_SHIFT, \
+ MSEPLL_DPLL_CTRL_PD_DAC_CLK_OUT_MASK, r2, r3
+ regbitset r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_DAC_CLK_SHIFT, \
+ MSEPLL_DPLL_CTRL_PD_DAC_CLK_MASK, r2, r3
+ regbitset r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_ADC_CLK_SHIFT, \
+ MSEPLL_DPLL_CTRL_PD_ADC_CLK_MASK, r2, r3
+
+ /*
+ * Configure PLLs (while switched off).
+ */
+ /* Peripheral PLL */
+ ldr r1, =MSEPLL_PPLL_BASE
+ regbitclear r1, MSEPLL_SPPLL_CTRL_OFFSET, MSEPLL_SPPLL_CTRL_VCO_DIV2_DIS_SHIFT, \
+ MSEPLL_SPPLL_CTRL_VCO_DIV2_DIS_MASK, r2, r3
+ /* Config to have an ouptut clock at 250 MHz */
+ mov r2, #0
+ mov r3, #MSEPLL_PPLL_CONF_INPUT_DIV_FIRST_3
+ add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_INPUT_DIV_FIRST_SHIFT
+ mov r3, #MSEPLL_PPLL_CONF_OUTPUT_DIV_FIRST_4
+ add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_OUTPUT_DIV_FIRST_SHIFT
+ mov r3, #MSEPLL_PPLL_CONF_LOOP_DIV_FIRST_5
+ add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_LOOP_DIV_FIRST_SHIFT
+ mov r3, #25
+ add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_LOOP_DIV_SECOND_SHIFT
+ str r2, [r1, #MSEPLL_SPPLL_CONF_OFFSET]
+
+ /* Other PLL config depends on MSE500 mode (200 or else) */
+ cmp r0, #NVRAM_MSE500_MODE_200
+ beq 200f
+
+ /* System PLL */
+ ldr r1, =MSEPLL_SPLL_BASE
+ regbitset r1, MSEPLL_SPPLL_CTRL_OFFSET, MSEPLL_SPPLL_CTRL_VCO_DIV2_DIS_SHIFT, \
+ MSEPLL_SPPLL_CTRL_VCO_DIV2_DIS_MASK, r2, r3
+ /* Config to have an ouptut clock at 492 MHz */
+ mov r2, #0
+ mov r3, #MSEPLL_SPLL_CONF_INPUT_DIV_FIRST_4
+ add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_INPUT_DIV_FIRST_SHIFT
+ str r2, [r1, #MSEPLL_SPPLL_CONF_OFFSET]
+ mov r3, #MSEPLL_SPLL_CONF_OUTPUT_DIV_FIRST_2
+ add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_OUTPUT_DIV_FIRST_SHIFT
+ mov r3, #MSEPLL_SPLL_CONF_LOOP_DIV_FIRST_2
+ add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_LOOP_DIV_FIRST_SHIFT
+ mov r3, #41
+ add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_LOOP_DIV_SECOND_SHIFT
+ str r2, [r1, #MSEPLL_SPPLL_CONF_OFFSET]
+
+ /* DSP PLL */
+ ldr r1, =MSEPLL_DPLL_BASE
+ /* Config to have an ouptut clock at 300 MHz */
+ ldr r2, [r1, #MSEPLL_DPLL_CTRL_OFFSET]
+ bitinsert r2, MSEPLL_DPLL_CTRL_REF_DIV_MASK, MSEPLL_DPLL_CTRL_REF_DIV_SHIFT, \
+ MSEPLL_DPLL_CTRL_REF_DIV_2, r3
+ bitinsert r2, MSEPLL_DPLL_CTRL_ADC_DIV_MASK, MSEPLL_DPLL_CTRL_ADC_DIV_SHIFT, \
+ MSEPLL_DPLL_CTRL_ADC_DIV_4, r3
+ str r2, [r1, #MSEPLL_DPLL_CTRL_OFFSET]
+ mov r2, #0
+ mov r3, #MSEPLL_DPLL_LOOP_DIV_FIRST_2
+ add r2, r2, r3, lsl #MSEPLL_DPLL_LOOP_DIV_FIRST_SHIFT
+ mov r3, #25
+ add r2, r2, r3, lsl #MSEPLL_DPLL_LOOP_DIV_SECOND_SHIFT
+ str r2, [r1, #MSEPLL_DPLL_LOOP_DIV_OFFSET]
+ ldr r2, [r1, #MSEPLL_DPLL_CONF_OFFSET]
+ bitinsert r2, MSEPLL_DPLL_CONF_DSP_DIV_MASK, MSEPLL_DPLL_CONF_DSP_DIV_SHIFT, \
+ MSEPLL_DPLL_CONF_DSP_DIV_2, r3
+ bitinsert r2, MSEPLL_DPLL_CONF_DAC_DIV_MASK, MSEPLL_DPLL_CONF_DAC_DIV_SHIFT, \
+ MSEPLL_DPLL_CONF_DAC_DIV_2, r3
+ bitinsert r2, MSEPLL_DPLL_CONF_ICP_MASK, MSEPLL_DPLL_CONF_ICP_SHIFT, 2, r3
+ str r2, [r1, #MSEPLL_DPLL_CONF_OFFSET]
+ b .Lendconf
+
+200:
+ /* For MSE500-200 mode */
+ /* System PLL */
+ ldr r1, =MSEPLL_SPLL_BASE
+ regbitclear r1, MSEPLL_SPPLL_CTRL_OFFSET, MSEPLL_SPPLL_CTRL_VCO_DIV2_DIS_SHIFT, \
+ MSEPLL_SPPLL_CTRL_VCO_DIV2_DIS_MASK, r2, r3
+ /* Config to have an ouptut clock at 192 MHz */
+ mov r2, #0
+ mov r3, #MSEPLL_SPLL_CONF_INPUT_DIV_FIRST_4
+ add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_INPUT_DIV_FIRST_SHIFT
+ str r2, [r1, #MSEPLL_SPPLL_CONF_OFFSET]
+ mov r3, #MSEPLL_SPLL_CONF_OUTPUT_DIV_FIRST_2
+ add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_OUTPUT_DIV_FIRST_SHIFT
+ mov r3, #MSEPLL_SPLL_CONF_LOOP_DIV_FIRST_2
+ add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_LOOP_DIV_FIRST_SHIFT
+ mov r3, #32
+ add r2, r2, r3, lsl #MSEPLL_SPPLL_CONF_LOOP_DIV_SECOND_SHIFT
+ str r2, [r1, #MSEPLL_SPPLL_CONF_OFFSET]
+
+ /* DSP PLL */
+ ldr r1, =MSEPLL_DPLL_BASE
+ /* Config to have an ouptut clock at 256 MHz */
+ ldr r2, [r1, #MSEPLL_DPLL_CTRL_OFFSET]
+ bitinsert r2, MSEPLL_DPLL_CTRL_REF_DIV_MASK, MSEPLL_DPLL_CTRL_REF_DIV_SHIFT, \
+ MSEPLL_DPLL_CTRL_REF_DIV_2, r3
+ bitinsert r2, MSEPLL_DPLL_CTRL_ADC_DIV_MASK, MSEPLL_DPLL_CTRL_ADC_DIV_SHIFT, \
+ MSEPLL_DPLL_CTRL_ADC_DIV_6, r3
+ str r2, [r1, #MSEPLL_DPLL_CTRL_OFFSET]
+ mov r2, #0
+ mov r3, #MSEPLL_DPLL_LOOP_DIV_FIRST_2
+ add r2, r2, r3, lsl #MSEPLL_DPLL_LOOP_DIV_FIRST_SHIFT
+ mov r3, #32
+ add r2, r2, r3, lsl #MSEPLL_DPLL_LOOP_DIV_SECOND_SHIFT
+ str r2, [r1, #MSEPLL_DPLL_LOOP_DIV_OFFSET]
+ ldr r2, [r1, #MSEPLL_DPLL_CONF_OFFSET]
+ bitinsert r2, MSEPLL_DPLL_CONF_DSP_DIV_MASK, MSEPLL_DPLL_CONF_DSP_DIV_SHIFT, \
+ MSEPLL_DPLL_CONF_DSP_DIV_3, r3
+ bitinsert r2, MSEPLL_DPLL_CONF_DAC_DIV_MASK, MSEPLL_DPLL_CONF_DAC_DIV_SHIFT, \
+ MSEPLL_DPLL_CONF_DAC_DIV_3, r3
+ bitinsert r2, MSEPLL_DPLL_CONF_ICP_MASK, MSEPLL_DPLL_CONF_ICP_SHIFT, 3, r3
+ str r2, [r1, #MSEPLL_DPLL_CONF_OFFSET]
+
+.Lendconf:
+ /*
+ * Switch ON PLLs and wait 200uS (or more)
+ * until they stabilize
+ */
+ /* System PLL */
+ ldr r1, =MSEPLL_SPLL_BASE
+ regbitclear r1, MSEPLL_SPPLL_CTRL_OFFSET, MSEPLL_SPPLL_CTRL_PD_SHIFT, \
+ MSEPLL_SPPLL_CTRL_PD_MASK, r2, r3
+ /* Peripheral PLL */
+ ldr r1, =MSEPLL_PPLL_BASE
+ regbitclear r1, MSEPLL_SPPLL_CTRL_OFFSET, MSEPLL_SPPLL_CTRL_PD_SHIFT, \
+ MSEPLL_SPPLL_CTRL_PD_MASK, r2, r3
+ /* DSP PLL */
+ ldr r1, =MSEPLL_DPLL_BASE
+ regbitclear r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_ADC_CLK_SHIFT, \
+ MSEPLL_DPLL_CTRL_PD_ADC_CLK_MASK, r2, r3
+ regbitclear r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_DAC_CLK_SHIFT, \
+ MSEPLL_DPLL_CTRL_PD_DAC_CLK_MASK, r2, r3
+ regbitclear r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_DAC_CLK_OUT_SHIFT, \
+ MSEPLL_DPLL_CTRL_PD_DAC_CLK_OUT_MASK, r2, r3
+ regbitclear r1, MSEPLL_DPLL_CTRL_OFFSET, MSEPLL_DPLL_CTRL_PD_CLK_SHIFT, \
+ MSEPLL_DPLL_CTRL_PD_CLK_MASK, r2, r3
+ regbitclear r1, MSEPLL_DPLL_CONF_OFFSET, MSEPLL_DPLL_CONF_PD_SHIFT, \
+ MSEPLL_DPLL_CONF_PD_MASK, r2, r3
+
+ /* active wait */
+ ldr r2, =PLL_WAIT_TIME
+1:
+ sub r2, r2, #1
+ cmp r2, #0
+ bne 1b
+
+ /*
+ * Switch to PLL clock
+ */
+ ldr r1, =MARIA_REGBANK_BASE
+ ldr r2, =PLL_CMD_PLL
+
+ /* System PLL */
+ str r2, [r1, #RB_SPLL_BYPASS_OFFSET]
+ waitstatus r1, RB_SPLL_BYPASS_STAT_OFFSET, PLL_IS_PLL, r2
+
+ /* Peripheral PLL */
+ str r2, [r1, #RB_PPLL_BYPASS_OFFSET]
+ waitstatus r1, RB_PPLL_BYPASS_STAT_OFFSET, PLL_IS_PLL, r2
+
+ /* DSP PLL */
+ str r2, [r1, #RB_DPLL_BYPASS_OFFSET]
+ waitstatus r1, RB_DPLL_BYPASS_STAT_OFFSET, PLL_IS_PLL, r2
+
+ /* back to my caller */
+ mov pc, lr
+
+#endif /* CONFIG_CHIP_FEATURE_MSEPLL */
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
index 904798e285..a925671a9f 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
@@ -401,7 +401,7 @@ poll_RB_CLK_DIV_STAT_ARM:
#endif
-#if defined(CONFIG_CHIP_FEATURE_SPCPLL)
+#if defined(CONFIG_CHIP_FEATURE_SPCPLL) || defined(CONFIG_CHIP_FEATURE_MSEPLL)
/*
* Do PLL initialization (depending on nvram parameters Xclk and Freq)
diff --git a/cleopatre/u-boot-1.1.6/include/configs/spc300_arch.h b/cleopatre/u-boot-1.1.6/include/configs/spc300_arch.h
index 9585cdd501..9099e22b16 100644
--- a/cleopatre/u-boot-1.1.6/include/configs/spc300_arch.h
+++ b/cleopatre/u-boot-1.1.6/include/configs/spc300_arch.h
@@ -51,6 +51,7 @@
# define CONFIG_CHIP_FEATURE_LINUX_MEM_WORKAROUND 1
# define CONFIG_CHIP_FEATURE_FIXED_ARM_CLOCK 1
# define CONFIG_CHIP_MAX_MASTER_CLOCK 246000000
+# define CONFIG_CHIP_FEATURE_MSEPLL 1
#else
# error "undefined chip"
#endif