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authorCyril Jourdan2012-07-25 12:00:17 +0200
committerCyril Jourdan2012-09-20 11:13:24 +0200
commit9b404eab41254bf0c2eb30f3ba73bbefdb25cf4c (patch)
tree5c680f7259b59251cf3775bf6acd07b2023b9082 /cleopatre/u-boot-1.1.6
parentf1dcfc4eed20b3f720a77947c10702cb2a6f20ee (diff)
cleo/uboot/cpu/spc300: move sdram init after PLL init, refs #2961
In the case where you do not need to resync DSP and AFE clocks.
Diffstat (limited to 'cleopatre/u-boot-1.1.6')
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/start.S15
1 files changed, 13 insertions, 2 deletions
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
index 9fc0e52926..55127f6343 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
@@ -383,6 +383,8 @@ poll_RB_CLK_DIV_STAT_ARM:
bl detect_nvram /* r10 will hold the NVRAM address */
mov lr, ip /* restore link */
+#ifdef CONFIG_CHIP_FEATURE_SYNC_DSP_CLOCK
+
/*
* SDRAM and board specific bits setup prior to relocation.
*/
@@ -390,8 +392,6 @@ poll_RB_CLK_DIV_STAT_ARM:
bl sdram_init /* we pass NVRAM addr in r10; do not corrupt r10 in this function */
mov lr, ip /* restore link */
-#ifdef CONFIG_CHIP_FEATURE_SYNC_DSP_CLOCK
-
/*
* Synchronise DSP
*/
@@ -412,6 +412,17 @@ poll_RB_CLK_DIV_STAT_ARM:
#endif
+#ifndef CONFIG_CHIP_FEATURE_SYNC_DSP_CLOCK
+
+ /*
+ * SDRAM and board specific bits setup prior to relocation.
+ */
+ mov ip, lr /* perserve link reg across call */
+ bl sdram_init /* we pass NVRAM addr in r10; do not corrupt r10 in this function */
+ mov lr, ip /* restore link */
+
+#endif
+
/*
* All vital periphs configured, exit cpu_init_crit
*/