From 9b404eab41254bf0c2eb30f3ba73bbefdb25cf4c Mon Sep 17 00:00:00 2001 From: Cyril Jourdan Date: Wed, 25 Jul 2012 12:00:17 +0200 Subject: cleo/uboot/cpu/spc300: move sdram init after PLL init, refs #2961 In the case where you do not need to resync DSP and AFE clocks. --- cleopatre/u-boot-1.1.6/cpu/spc300/start.S | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) (limited to 'cleopatre/u-boot-1.1.6') diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S index 9fc0e52926..55127f6343 100644 --- a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S +++ b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S @@ -383,6 +383,8 @@ poll_RB_CLK_DIV_STAT_ARM: bl detect_nvram /* r10 will hold the NVRAM address */ mov lr, ip /* restore link */ +#ifdef CONFIG_CHIP_FEATURE_SYNC_DSP_CLOCK + /* * SDRAM and board specific bits setup prior to relocation. */ @@ -390,8 +392,6 @@ poll_RB_CLK_DIV_STAT_ARM: bl sdram_init /* we pass NVRAM addr in r10; do not corrupt r10 in this function */ mov lr, ip /* restore link */ -#ifdef CONFIG_CHIP_FEATURE_SYNC_DSP_CLOCK - /* * Synchronise DSP */ @@ -410,6 +410,17 @@ poll_RB_CLK_DIV_STAT_ARM: bl pll_init /* we pass NVRAM addr in r10; do not corrupt r10 in this function */ mov lr, ip /* restore link */ +#endif + +#ifndef CONFIG_CHIP_FEATURE_SYNC_DSP_CLOCK + + /* + * SDRAM and board specific bits setup prior to relocation. + */ + mov ip, lr /* perserve link reg across call */ + bl sdram_init /* we pass NVRAM addr in r10; do not corrupt r10 in this function */ + mov lr, ip /* restore link */ + #endif /* -- cgit v1.2.3