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authorNicolas Schodet2012-04-05 15:14:20 +0200
committerNicolas Schodet2012-05-09 10:41:10 +0200
commitfa87405fb517806231ed85234c1c11e8a2ff3cbc (patch)
treeb2c9d1deb9f9483ab2aa1cf18f410251963478c9 /cleopatre/u-boot-1.1.6/cpu/spc300
parente518168f475783dea4a5e926de27d9f27d2308de (diff)
cleo/u-boot: compute flash SPI speed
Diffstat (limited to 'cleopatre/u-boot-1.1.6/cpu/spc300')
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/start.S6
1 files changed, 5 insertions, 1 deletions
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
index d4a1d25434..1427fc7848 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
@@ -30,6 +30,10 @@
#include <asm/arch/nvram.h>
#define ETH_PHY_RESET_WAIT_TIME 600000 /* (((12000 * 147500000) / 1000000) / 3) */
+
+#define SPI_FREQ_VAL ((CONFIG_CHIP_MAX_MASTER_CLOCK + CFG_SPI_FREQ * 2 - 1) \
+ / (CFG_SPI_FREQ * 2) - 1)
+
/*
*************************************************************************
*
@@ -342,7 +346,7 @@ cpu_init_crit:
* Speed up SPI and ARM
*/
ldr r0, =SPI_FREQ
- ldr r1, =0x00000003 /* divide CLK_AHB (after PLL) by 8 (<20MHz @147MHz)*/
+ ldr r1, =SPI_FREQ_VAL
str r1, [r0]
ldr r0, =REGBANK_BASE