summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--cleopatre/u-boot-1.1.6/board/sdk300/flash.c5
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/start.S6
2 files changed, 9 insertions, 2 deletions
diff --git a/cleopatre/u-boot-1.1.6/board/sdk300/flash.c b/cleopatre/u-boot-1.1.6/board/sdk300/flash.c
index 78563dc7c6..571d8246e6 100644
--- a/cleopatre/u-boot-1.1.6/board/sdk300/flash.c
+++ b/cleopatre/u-boot-1.1.6/board/sdk300/flash.c
@@ -81,6 +81,9 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
#define SPI_CTL_MASK_REG ( *( (volatile unsigned int *)(CFG_FLASH_SPI_BASE + 0x34) ) )
#define SPI_CTL_STATUS_REG ( *( (volatile unsigned int *)(CFG_FLASH_SPI_BASE + 0x38) ) )
+#define SPI_CTL_FREQ_REG_VAL ((CONFIG_CHIP_MAX_MASTER_CLOCK + CFG_SPI_FREQ * 2 - 1) \
+ / (CFG_SPI_FREQ * 2) - 1)
+
/* status bits */
enum
{
@@ -238,7 +241,7 @@ void init_spi_controller(void)
SPI_CTL_MASTER_SLAVE_REG = 0x01; /* Master */
SPI_CTL_CONTROL_CONFIG_REG = 0x00; /* 3 wires Master */
- SPI_CTL_FREQ_REG = 0x03; /* 18.375 Mhz (MARIA_MASTER_CLOCK/8 @147MHz) */
+ SPI_CTL_FREQ_REG = SPI_CTL_FREQ_REG_VAL;
SPI_CTL_CS_LATENCY = 0x04; /* 4 cycles clock AHB */
SPI_CTL_CONF_TX = 0x00010008; /* send one byte (i.e. one word of length of 8 bits) */
SPI_CTL_CONF_RX = 0x00010008; /* receive one byte */
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
index d4a1d25434..1427fc7848 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
@@ -30,6 +30,10 @@
#include <asm/arch/nvram.h>
#define ETH_PHY_RESET_WAIT_TIME 600000 /* (((12000 * 147500000) / 1000000) / 3) */
+
+#define SPI_FREQ_VAL ((CONFIG_CHIP_MAX_MASTER_CLOCK + CFG_SPI_FREQ * 2 - 1) \
+ / (CFG_SPI_FREQ * 2) - 1)
+
/*
*************************************************************************
*
@@ -342,7 +346,7 @@ cpu_init_crit:
* Speed up SPI and ARM
*/
ldr r0, =SPI_FREQ
- ldr r1, =0x00000003 /* divide CLK_AHB (after PLL) by 8 (<20MHz @147MHz)*/
+ ldr r1, =SPI_FREQ_VAL
str r1, [r0]
ldr r0, =REGBANK_BASE