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authorsave2009-08-11 15:56:56 +0000
committersave2009-08-11 15:56:56 +0000
commitb4b5d3846b66aaf267b150717217e3241e348486 (patch)
tree28ae3e4ed1e2986d2722537c6d7056cd005acdf2 /cleopatre/u-boot-1.1.6/cpu/spc300/start.S
parent080467fb905ef37c36c58d1d1fb98992e833537d (diff)
[CLEO][U-BOOT]Corrections after spk300g simulation
- Default NVRAM address (relative and not absolute) - PLL tables are now in word and not byte to respect SPI Direct read restrictions git-svn-id: svn+ssh://pessac/svn/cesar/trunk@5208 017c9cb6-072f-447c-8318-d5b54f68fe89
Diffstat (limited to 'cleopatre/u-boot-1.1.6/cpu/spc300/start.S')
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/start.S18
1 files changed, 18 insertions, 0 deletions
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
index 15d2826953..95e1b9b2b6 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
@@ -370,6 +370,24 @@ poll_RB_CLK_DIV_STAT_ARM:
ldr r2, [r10, #32] /* load SREFR content from NVRAM */
str r2, [r1, #SREFR] /* store configuration to config reg */
+ /* Find Freq parameters from NVRAM (struct address is in r10) */
+ ldr r2, [r10, #8] /* load pkg_cfg */
+ and r2, r2, #0x0c
+ lsr r2, r2, #2 /* r1 = freq */
+ cmp r2, #3 /* freq = 150MHz ? */
+ bne .NotHighSpeed /* no : don't touch pipe and latch */
+
+ /* Increase Read Pipe when freq > 143MHz */
+ ldr r2, [r1, #SCTLR] /* r2 = SCTLR */
+ orr r2, r2, #(0x03 << SCTLR_read_pipe_BitAddressOffset)
+ str r2, [r1, #SCTLR] /* SCTLR -> set read pipe to 3 */
+
+ /* Set SDRAM latch when freq > 143MHZ */
+ ldr r3, =MARIA_REGBANK_BASE
+ mov r2, #1
+ str r2, [r3, #RB_SDRAM_RETURN_LAT]
+
+.NotHighSpeed:
/* reinitialize SDRAM for changes to take effect */
ldr r2, [r1, #SCTLR] /* r2 = SCTLR */
orr r2, r2, #0x01