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authorsave2009-08-11 15:56:56 +0000
committersave2009-08-11 15:56:56 +0000
commitb4b5d3846b66aaf267b150717217e3241e348486 (patch)
tree28ae3e4ed1e2986d2722537c6d7056cd005acdf2 /cleopatre
parent080467fb905ef37c36c58d1d1fb98992e833537d (diff)
[CLEO][U-BOOT]Corrections after spk300g simulation
- Default NVRAM address (relative and not absolute) - PLL tables are now in word and not byte to respect SPI Direct read restrictions git-svn-id: svn+ssh://pessac/svn/cesar/trunk@5208 017c9cb6-072f-447c-8318-d5b54f68fe89
Diffstat (limited to 'cleopatre')
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300-fcm3/nvram.S15
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300-fcm3/pll_init.S93
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/eth_init.S11
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/nvram.S15
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/pll_init.S95
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/serial.c6
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/start.S18
7 files changed, 145 insertions, 108 deletions
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300-fcm3/nvram.S b/cleopatre/u-boot-1.1.6/cpu/spc300-fcm3/nvram.S
index 02409b69b9..146cb25643 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300-fcm3/nvram.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300-fcm3/nvram.S
@@ -43,7 +43,7 @@
*************************************************************************
*/
detect_nvram:
- ldr r10, =nvram_dft /* if nvram is not found, we will have this value in r10 */
+ adr r10, nvram_dft /* if nvram is not found, we will have this value in r10 */
ldr r1, =-1 /* init value for loop counter */
ldr r4, =PHYS_FLASH_SPI_1 /* Offset of the SPI Direct access address */
.Lsect:
@@ -53,12 +53,12 @@ detect_nvram:
mov r0, r1, lsl #16 /* r0= r1<<16 = r1*0x10000 */
add r0, r0, r4 /* Add SPI Direct base address */
ldr r2, [r0, #0] /* load r2 with the first 4 bytes from the sector beginning */
- ldr r3, =nvram_magic /* r3 = nvram_magic (previously defined : char *nvram_magic = "NVRAM\0\0\0";) */
+ adr r3, nvram_magic /* r3 = nvram_magic (previously defined : char *nvram_magic = "NVRAM\0\0\0";) */
ldr r3, [r3, #0] /* r3 <- first 4 bytes of magic word */
cmp r2, r3
bne .Lsect /* nvram not found in this sector */
ldr r2, [r0, #4] /* load r2 with the last 4 bytes from the sector beginning */
- ldr r3, =nvram_magic
+ adr r3, nvram_magic
ldr r3, [r3, #4] /* r3 <- last 4 bytes of magic word */
cmp r2, r3
bne .Lsect /* nvram not found in this sector */
@@ -93,7 +93,13 @@ nvram_dft:
.word 0x00140000 /* img_0_offset */
.word 0x00000001 /* nb_images */
.ascii NVRAM_DEFAULT_WORD /* product_name */
+ .ascii NVRAM_DEFAULT_WORD /* */
+ .ascii NVRAM_DEFAULT_WORD /* */
+ .ascii NVRAM_DEFAULT_WORD /* */
.ascii NVRAM_DEFAULT_WORD /* product_partnb*/
+ .ascii NVRAM_DEFAULT_WORD /* */
+ .ascii NVRAM_DEFAULT_WORD /* */
+ .ascii NVRAM_DEFAULT_WORD /* */
.ascii NVRAM_DEFAULT_WORD /* product_desc */
.ascii NVRAM_DEFAULT_WORD /* */
.ascii NVRAM_DEFAULT_WORD /* */
@@ -103,6 +109,9 @@ nvram_dft:
.ascii NVRAM_DEFAULT_WORD /* */
.ascii NVRAM_DEFAULT_WORD /* */
.ascii NVRAM_DEFAULT_WORD /* serial_number */
+ .ascii NVRAM_DEFAULT_WORD /* */
+ .ascii NVRAM_DEFAULT_WORD /* */
+ .ascii NVRAM_DEFAULT_WORD /* */
.word 0x00000000 /* eth_phy_addr */
.word 0x22334455 /* eth_address */
.word 0x00000011 /* */
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300-fcm3/pll_init.S b/cleopatre/u-boot-1.1.6/cpu/spc300-fcm3/pll_init.S
index 9c18172bb6..36bc1fbc70 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300-fcm3/pll_init.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300-fcm3/pll_init.S
@@ -69,11 +69,10 @@ pll_init:
* (NVRAM struct adress was passed to this fnc in r10) */
ldr r1, [r10, #8] /* load pkg_cfg field into r1 */
and r2, r1, #0x03 /* r2 = Xclk */
- and r3, r1, #0x0c
- lsr r3, r3, #2 /* r3 = Freq */
- ldr r1, =4
- mul r4, r2, r1 /* r4 = Xclk*4 */
- add r3, r3, r4 /* r3 = Xclk*4 + Freq; and this will be the index into our matrix */
+ and r3, r1, #0x0c /* r3 = Freq*4 */
+ lsl r4, r2, #4 /* r4 = Xclk*16 */
+ lsl r2, r2, #2 /* r2 = Xclk*4 */
+ add r3, r3, r4 /* r3 = Xclk*16 + Freq*4; and this will be the index into our matrix */
/* System PLL */
/* config : fbdiv, prediv, lbws, sscg_enable, sscg_fcw, sscg_fmw, sscg_mdw */
@@ -83,11 +82,11 @@ pll_init:
str r1, [r0, #RB_SPLL_EN] /* RB_SPLL_EN = 0 */
adr r4, .LpoolSYSfbdiv /* r4 points to the begining of the array */
- ldr r1, [r4, r3] /* r1 = array[Xclk*4 + Freq]; we take the element of the array indexed with Xclk */
+ ldr r1, [r4, r3] /* r1 = array[Xclk*16 + Freq*4]; we take the element of the array indexed with Xclk */
str r1, [r0, #RB_SPLL_FBDIV]
adr r4, .LpoolSYSprediv /* r4 points to the begining of the array */
- ldr r1, [r4, r3] /* r1 = array[Xclk*4 + Freq]; we take the element of the array indexed with Xclk */
+ ldr r1, [r4, r3] /* r1 = array[Xclk*16 + Freq*4]; we take the element of the array indexed with Xclk */
str r1, [r0, #RB_SPLL_PREDIV]
ldr r1, = PLL_LBWS_ON
@@ -105,11 +104,11 @@ pll_init:
ldr r0, =REGBANK_BASE
adr r4, .LpoolPERIPHfbdiv /* r4 points to the begining of the array */
- ldr r1, [r4, r2] /* r1 = array[Xclk]; we take the element of the array indexed with Xclk */
+ ldr r1, [r4, r2] /* r1 = array[Xclk*4]; we take the element of the array indexed with Xclk */
str r1, [r0, #RB_PPLL_FBDIV]
adr r4, .LpoolPERIPHprediv /* r4 points to the begining of the array */
- ldr r1, [r4, r2] /* r1 = array[Xclk]; we take the element of the array indexed with Xclk */
+ ldr r1, [r4, r2] /* r1 = array[Xclk*4]; we take the element of the array indexed with Xclk */
str r1, [r0, #RB_PPLL_PREDIV]
ldr r1, = PLL_LBWS_OFF
@@ -121,11 +120,11 @@ pll_init:
ldr r0, =REGBANK_BASE
adr r4, .LpoolDSPfbdiv /* r4 points to the begining of the array */
- ldr r1, [r4, r2] /* r1 = array[Xclk]; we take the element of the array indexed with Xclk */
+ ldr r1, [r4, r2] /* r1 = array[Xclk*4]; we take the element of the array indexed with Xclk */
str r1, [r0, #RB_DPLL_FBDIV]
adr r4, .LpoolDSPprediv /* r4 points to the begining of the array */
- ldr r1, [r4, r2] /* r1 = array[Xclk]; we take the element of the array indexed with Xclk */
+ ldr r1, [r4, r2] /* r1 = array[Xclk*4]; we take the element of the array indexed with Xclk */
str r1, [r0, #RB_DPLL_PREDIV]
ldr r1, = PLL_LBWS_OFF
@@ -198,60 +197,60 @@ pll_init:
*/
.LpoolSYSfbdiv:
/* Xclk = 0 (18.75 MHz) */
- .byte 0x40 /* Freq = 0 (100 MHz) */
- .byte 0x50 /* Freq = 1 (125 MHz) */
- .byte 0x55 /* Freq = 2 (133 MHz) */
- .byte 0x20 /* Freq = 3 (150 MHz) */
+ .word 0x00000040 /* Freq = 0 (100 MHz) */
+ .word 0x00000050 /* Freq = 1 (125 MHz) */
+ .word 0x00000055 /* Freq = 2 (133 MHz) */
+ .word 0x00000020 /* Freq = 3 (150 MHz) */
/* Xclk = 1 (25 MHz) */
- .byte 0x10 /* Freq = 0 (100 MHz) */
- .byte 0x14 /* Freq = 1 (125 MHz) */
- .byte 0x40 /* Freq = 2 (133 MHz) */
- .byte 0x18 /* Freq = 3 (150 MHz) */
+ .word 0x00000010 /* Freq = 0 (100 MHz) */
+ .word 0x00000014 /* Freq = 1 (125 MHz) */
+ .word 0x00000040 /* Freq = 2 (133 MHz) */
+ .word 0x00000018 /* Freq = 3 (150 MHz) */
/* Xclk = 2 (37.5 MHz) */
- .byte 0x20 /* Freq = 0 (100 MHz) */
- .byte 0x28 /* Freq = 1 (125 MHz) */
- .byte 0x00 /* Freq = 2 (133 MHz) */
- .byte 0x10 /* Freq = 3 (150 MHz) */
+ .word 0x00000020 /* Freq = 0 (100 MHz) */
+ .word 0x00000028 /* Freq = 1 (125 MHz) */
+ .word 0x00000000 /* Freq = 2 (133 MHz) */
+ .word 0x00000010 /* Freq = 3 (150 MHz) */
.LpoolSYSprediv:
/* Xclk = 0 (18.75 MHz) */
- .byte 0x03 /* Freq = 0 (100 MHz) */
- .byte 0x03 /* Freq = 1 (125 MHz) */
- .byte 0x03 /* Freq = 2 (133 MHz) */
- .byte 0x01 /* Freq = 3 (150 MHz) */
+ .word 0x00000003 /* Freq = 0 (100 MHz) */
+ .word 0x00000003 /* Freq = 1 (125 MHz) */
+ .word 0x00000003 /* Freq = 2 (133 MHz) */
+ .word 0x00000001 /* Freq = 3 (150 MHz) */
/* Xclk = 1 (25 MHz) */
- .byte 0x01 /* Freq = 0 (100 MHz) */
- .byte 0x01 /* Freq = 1 (125 MHz) */
- .byte 0x03 /* Freq = 2 (133 MHz) */
- .byte 0x01 /* Freq = 3 (150 MHz) */
+ .word 0x00000001 /* Freq = 0 (100 MHz) */
+ .word 0x00000001 /* Freq = 1 (125 MHz) */
+ .word 0x00000003 /* Freq = 2 (133 MHz) */
+ .word 0x00000001 /* Freq = 3 (150 MHz) */
/* Xclk = 2 (37.5 MHz) */
- .byte 0x03 /* Freq = 0 (100 MHz) */
- .byte 0x03 /* Freq = 1 (125 MHz) */
- .byte 0x09 /* Freq = 2 (133 MHz) */
- .byte 0x01 /* Freq = 3 (150 MHz) */
+ .word 0x00000003 /* Freq = 0 (100 MHz) */
+ .word 0x00000003 /* Freq = 1 (125 MHz) */
+ .word 0x00000009 /* Freq = 2 (133 MHz) */
+ .word 0x00000001 /* Freq = 3 (150 MHz) */
/*
* Peripheral PLL
*/
.LpoolPERIPHfbdiv:
- .byte 0x28 /* Xclk = 0 (18.75 MHz) */
- .byte 0x0a /* Xclk = 1 (25 MHz) */
- .byte 0x14 /* Xclk = 2 (37.5 MHz) */
+ .word 0x00000028 /* Xclk = 0 (18.75 MHz) */
+ .word 0x0000000a /* Xclk = 1 (25 MHz) */
+ .word 0x00000014 /* Xclk = 2 (37.5 MHz) */
.LpoolPERIPHprediv:
- .byte 0x03 /* Xclk = 0 (18.75 MHz) */
- .byte 0x01 /* Xclk = 1 (25 MHz) */
- .byte 0x03 /* Xclk = 2 (37.5 MHz) */
+ .word 0x00000003 /* Xclk = 0 (18.75 MHz) */
+ .word 0x00000001 /* Xclk = 1 (25 MHz) */
+ .word 0x00000003 /* Xclk = 2 (37.5 MHz) */
/*
* DSP PLL
*/
.LpoolDSPfbdiv:
- .byte 0x10 /* Xclk = 0 (18.75 MHz) */
- .byte 0x0c /* Xclk = 1 (25 MHz) */
- .byte 0x08 /* Xclk = 2 (37.5 MHz) */
+ .word 0x00000010 /* Xclk = 0 (18.75 MHz) */
+ .word 0x0000000c /* Xclk = 1 (25 MHz) */
+ .word 0x00000008 /* Xclk = 2 (37.5 MHz) */
.LpoolDSPprediv:
- .byte 0x01 /* Xclk = 0 (18.75 MHz) */
- .byte 0x01 /* Xclk = 1 (25 MHz) */
- .byte 0x01 /* Xclk = 2 (37.5 MHz) */
+ .word 0x00000001 /* Xclk = 0 (18.75 MHz) */
+ .word 0x00000001 /* Xclk = 1 (25 MHz) */
+ .word 0x00000001 /* Xclk = 2 (37.5 MHz) */
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/eth_init.S b/cleopatre/u-boot-1.1.6/cpu/spc300/eth_init.S
index 84f8a4ee92..707a76b193 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/eth_init.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/eth_init.S
@@ -60,16 +60,16 @@ ethernet_config:
* Switch off all Ethernet clock commands
*/
cmdoff RB_CLK_CMD_ETH_TX_125
- checkreg RB_CLK_CMD_ETH_TX_125, CLK_IS_OFF
+ checkreg RB_CLK_STAT_ETH_TX_125, CLK_IS_OFF
cmdoff RB_CLK_CMD_ETH_TX_EXT
- checkreg RB_CLK_CMD_ETH_TX_EXT, CLK_IS_OFF
+ checkreg RB_CLK_STAT_ETH_TX_EXT, CLK_IS_OFF
cmdoff RB_CLK_CMD_ETH_RX_EXT
- checkreg RB_CLK_CMD_ETH_RX_EXT, CLK_IS_OFF
+ checkreg RB_CLK_STAT_ETH_RX_EXT, CLK_IS_OFF
cmdoff RB_CLK_CMD_ETH_RMII
- checkreg RB_CLK_CMD_ETH_RMII, CLK_IS_OFF
+ checkreg RB_CLK_STAT_ETH_RMII, CLK_IS_OFF
/*
* Find Ethernet Mode from NVRAM
@@ -156,5 +156,6 @@ ethernet_config:
cmdon RB_CLK_CMD_OUT25
checkreg RB_CLK_STAT_OUT25, CLK_IS_ON
- mov pc, lr /* back to my caller */
+ /* back to my caller */
+ mov pc, lr
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/nvram.S b/cleopatre/u-boot-1.1.6/cpu/spc300/nvram.S
index 8c5d6a2f6a..1a2c0254e0 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/nvram.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/nvram.S
@@ -45,7 +45,7 @@
*************************************************************************
*/
detect_nvram:
- ldr r10, =nvram_dft /* if nvram is not found, we will have this value in r10 */
+ adr r10, nvram_dft /* if nvram is not found, we will have this value in r10 */
ldr r1, =-1 /* init value for loop counter */
ldr r4, =PHYS_FLASH_SPI_1 /* Offset of the SPI Direct access address */
.Lsect:
@@ -55,12 +55,12 @@ detect_nvram:
mov r0, r1, lsl #16 /* r0= r1<<16 = r1*0x10000 */
add r0, r0, r4 /* Add SPI Direct base address */
ldr r2, [r0, #0] /* load r2 with the first 4 bytes from the sector beginning */
- ldr r3, =nvram_magic /* r3 = nvram_magic (previously defined : char *nvram_magic = "NVRAM\0\0\0";) */
+ adr r3, nvram_magic /* r3 = nvram_magic (previously defined : char *nvram_magic = "NVRAM\0\0\0";) */
ldr r3, [r3, #0] /* r3 <- first 4 bytes of magic word */
cmp r2, r3
bne .Lsect /* nvram not found in this sector */
ldr r2, [r0, #4] /* load r2 with the last 4 bytes from the sector beginning */
- ldr r3, =nvram_magic
+ adr r3, nvram_magic
ldr r3, [r3, #4] /* r3 <- last 4 bytes of magic word */
cmp r2, r3
bne .Lsect /* nvram not found in this sector */
@@ -114,7 +114,13 @@ nvram_dft:
.word 0x00140000 /* img_0_offset */
.word 0x00000001 /* nb_images */
.ascii NVRAM_DEFAULT_WORD /* product_name */
+ .ascii NVRAM_DEFAULT_WORD /* */
+ .ascii NVRAM_DEFAULT_WORD /* */
+ .ascii NVRAM_DEFAULT_WORD /* */
.ascii NVRAM_DEFAULT_WORD /* product_partnb*/
+ .ascii NVRAM_DEFAULT_WORD /* */
+ .ascii NVRAM_DEFAULT_WORD /* */
+ .ascii NVRAM_DEFAULT_WORD /* */
.ascii NVRAM_DEFAULT_WORD /* product_desc */
.ascii NVRAM_DEFAULT_WORD /* */
.ascii NVRAM_DEFAULT_WORD /* */
@@ -124,6 +130,9 @@ nvram_dft:
.ascii NVRAM_DEFAULT_WORD /* */
.ascii NVRAM_DEFAULT_WORD /* */
.ascii NVRAM_DEFAULT_WORD /* serial_number */
+ .ascii NVRAM_DEFAULT_WORD /* */
+ .ascii NVRAM_DEFAULT_WORD /* */
+ .ascii NVRAM_DEFAULT_WORD /* */
.word 0x00000000 /* eth_phy_addr */
.word 0x22334455 /* eth_address */
.word 0x00000011 /* */
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/pll_init.S b/cleopatre/u-boot-1.1.6/cpu/spc300/pll_init.S
index 3d8aa76804..17dafe2553 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/pll_init.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/pll_init.S
@@ -69,11 +69,10 @@ pll_init:
* (NVRAM struct adress was passed to this fnc in r10) */
ldr r1, [r10, #8] /* load pkg_cfg field into r1 */
and r2, r1, #0x03 /* r2 = Xclk */
- and r3, r1, #0x0c
- lsr r3, r3, #2 /* r3 = Freq */
- ldr r1, =4
- mul r4, r2, r1 /* r4 = Xclk*4 */
- add r3, r3, r4 /* r3 = Xclk*4 + Freq; and this will be the index into our matrix */
+ and r3, r1, #0x0c /* r3 = Freq*4 */
+ lsl r4, r2, #4 /* r4 = Xclk*16 */
+ lsl r2, r2, #2 /* r2 = Xclk*4 */
+ add r3, r3, r4 /* r3 = Xclk*16 + Freq*4; and this will be the index into our matrix */
/* System PLL */
/* config : fbdiv, prediv, lbws, sscg_enable, sscg_fcw, sscg_fmw, sscg_mdw */
@@ -83,11 +82,11 @@ pll_init:
str r1, [r0, #RB_SPLL_EN] /* RB_SPLL_EN = 0 */
adr r4, .LpoolSYSfbdiv /* r4 points to the begining of the array */
- ldr r1, [r4, r3] /* r1 = array[Xclk*4 + Freq]; we take the element of the array indexed with Xclk */
+ ldr r1, [r4, r3] /* r1 = array[Xclk*16 + Freq*4]; we take the element of the array indexed with Xclk */
str r1, [r0, #RB_SPLL_FBDIV]
adr r4, .LpoolSYSprediv /* r4 points to the begining of the array */
- ldr r1, [r4, r3] /* r1 = array[Xclk*4 + Freq]; we take the element of the array indexed with Xclk */
+ ldr r1, [r4, r3] /* r1 = array[Xclk*16 + Freq*4]; we take the element of the array indexed with Xclk */
str r1, [r0, #RB_SPLL_PREDIV]
ldr r1, = PLL_LBWS_ON
@@ -105,11 +104,11 @@ pll_init:
ldr r0, =REGBANK_BASE
adr r4, .LpoolPERIPHfbdiv /* r4 points to the begining of the array */
- ldr r1, [r4, r2] /* r1 = array[Xclk]; we take the element of the array indexed with Xclk */
+ ldr r1, [r4, r2] /* r1 = array[Xclk*4]; we take the element of the array indexed with Xclk */
str r1, [r0, #RB_PPLL_FBDIV]
adr r4, .LpoolPERIPHprediv /* r4 points to the begining of the array */
- ldr r1, [r4, r2] /* r1 = array[Xclk]; we take the element of the array indexed with Xclk */
+ ldr r1, [r4, r2] /* r1 = array[Xclk*4]; we take the element of the array indexed with Xclk */
str r1, [r0, #RB_PPLL_PREDIV]
ldr r1, = PLL_LBWS_OFF
@@ -121,11 +120,11 @@ pll_init:
ldr r0, =REGBANK_BASE
adr r4, .LpoolDSPfbdiv /* r4 points to the begining of the array */
- ldr r1, [r4, r2] /* r1 = array[Xclk]; we take the element of the array indexed with Xclk */
+ ldr r1, [r4, r2] /* r1 = array[Xclk*4]; we take the element of the array indexed with Xclk */
str r1, [r0, #RB_DPLL_FBDIV]
adr r4, .LpoolDSPprediv /* r4 points to the begining of the array */
- ldr r1, [r4, r2] /* r1 = array[Xclk]; we take the element of the array indexed with Xclk */
+ ldr r1, [r4, r2] /* r1 = array[Xclk*4]; we take the element of the array indexed with Xclk */
str r1, [r0, #RB_DPLL_PREDIV]
ldr r1, = PLL_LBWS_OFF
@@ -187,6 +186,8 @@ pll_init:
cmp r1, #PLL_IS_PLL
bne .LpollDPLLstat
+ /* back to my caller */
+ mov pc, lr
/**************************************************************
*
@@ -198,60 +199,60 @@ pll_init:
*/
.LpoolSYSfbdiv:
/* Xclk = 0 (18.75 MHz) */
- .byte 0x40 /* Freq = 0 (100 MHz) */
- .byte 0x50 /* Freq = 1 (125 MHz) */
- .byte 0x55 /* Freq = 2 (133 MHz) */
- .byte 0x3F /* Freq = 3 (150 MHz) */
+ .word 0x00000040 /* Freq = 0 (100 MHz) */
+ .word 0x00000050 /* Freq = 1 (125 MHz) */
+ .word 0x00000055 /* Freq = 2 (133 MHz) */
+ .word 0x0000003F /* Freq = 3 (150 MHz) */
/* Xclk = 1 (25 MHz) */
- .byte 0x10 /* Freq = 0 (100 MHz) */
- .byte 0x14 /* Freq = 1 (125 MHz) */
- .byte 0x40 /* Freq = 2 (133 MHz) */
- .byte 0x2F /* Freq = 3 (150 MHz) */
+ .word 0x00000010 /* Freq = 0 (100 MHz) */
+ .word 0x00000014 /* Freq = 1 (125 MHz) */
+ .word 0x00000040 /* Freq = 2 (133 MHz) */
+ .word 0x0000002F /* Freq = 3 (150 MHz) */
/* Xclk = 2 (37.5 MHz) */
- .byte 0x20 /* Freq = 0 (100 MHz) */
- .byte 0x28 /* Freq = 1 (125 MHz) */
- .byte 0x00 /* Freq = 2 (133 MHz) */
- .byte 0x3F /* Freq = 3 (150 MHz) */
+ .word 0x00000020 /* Freq = 0 (100 MHz) */
+ .word 0x00000028 /* Freq = 1 (125 MHz) */
+ .word 0x00000000 /* Freq = 2 (133 MHz) */
+ .word 0x0000003F /* Freq = 3 (150 MHz) */
.LpoolSYSprediv:
/* Xclk = 0 (18.75 MHz) */
- .byte 0x03 /* Freq = 0 (100 MHz) */
- .byte 0x03 /* Freq = 1 (125 MHz) */
- .byte 0x03 /* Freq = 2 (133 MHz) */
- .byte 0x02 /* Freq = 3 (150 MHz) */
+ .word 0x00000003 /* Freq = 0 (100 MHz) */
+ .word 0x00000003 /* Freq = 1 (125 MHz) */
+ .word 0x00000003 /* Freq = 2 (133 MHz) */
+ .word 0x00000002 /* Freq = 3 (150 MHz) */
/* Xclk = 1 (25 MHz) */
- .byte 0x01 /* Freq = 0 (100 MHz) */
- .byte 0x01 /* Freq = 1 (125 MHz) */
- .byte 0x03 /* Freq = 2 (133 MHz) */
- .byte 0x02 /* Freq = 3 (150 MHz) */
+ .word 0x00000001 /* Freq = 0 (100 MHz) */
+ .word 0x00000001 /* Freq = 1 (125 MHz) */
+ .word 0x00000003 /* Freq = 2 (133 MHz) */
+ .word 0x00000002 /* Freq = 3 (150 MHz) */
/* Xclk = 2 (37.5 MHz) */
- .byte 0x03 /* Freq = 0 (100 MHz) */
- .byte 0x03 /* Freq = 1 (125 MHz) */
- .byte 0x09 /* Freq = 2 (133 MHz) */
- .byte 0x04 /* Freq = 3 (150 MHz) */
+ .word 0x00000003 /* Freq = 0 (100 MHz) */
+ .word 0x00000003 /* Freq = 1 (125 MHz) */
+ .word 0x00000009 /* Freq = 2 (133 MHz) */
+ .word 0x00000004 /* Freq = 3 (150 MHz) */
/*
* Peripheral PLL
*/
.LpoolPERIPHfbdiv:
- .byte 0x28 /* Xclk = 0 (18.75 MHz) */
- .byte 0x0a /* Xclk = 1 (25 MHz) */
- .byte 0x14 /* Xclk = 2 (37.5 MHz) */
+ .word 0x00000028 /* Xclk = 0 (18.75 MHz) */
+ .word 0x0000000a /* Xclk = 1 (25 MHz) */
+ .word 0x00000014 /* Xclk = 2 (37.5 MHz) */
.LpoolPERIPHprediv:
- .byte 0x03 /* Xclk = 0 (18.75 MHz) */
- .byte 0x01 /* Xclk = 1 (25 MHz) */
- .byte 0x03 /* Xclk = 2 (37.5 MHz) */
+ .word 0x00000003 /* Xclk = 0 (18.75 MHz) */
+ .word 0x00000001 /* Xclk = 1 (25 MHz) */
+ .word 0x00000003 /* Xclk = 2 (37.5 MHz) */
/*
* DSP PLL
*/
.LpoolDSPfbdiv:
- .byte 0x10 /* Xclk = 0 (18.75 MHz) */
- .byte 0x0c /* Xclk = 1 (25 MHz) */
- .byte 0x08 /* Xclk = 2 (37.5 MHz) */
+ .word 0x00000010 /* Xclk = 0 (18.75 MHz) */
+ .word 0x0000000c /* Xclk = 1 (25 MHz) */
+ .word 0x00000008 /* Xclk = 2 (37.5 MHz) */
.LpoolDSPprediv:
- .byte 0x01 /* Xclk = 0 (18.75 MHz) */
- .byte 0x01 /* Xclk = 1 (25 MHz) */
- .byte 0x01 /* Xclk = 2 (37.5 MHz) */
+ .word 0x00000001 /* Xclk = 0 (18.75 MHz) */
+ .word 0x00000001 /* Xclk = 1 (25 MHz) */
+ .word 0x00000001 /* Xclk = 2 (37.5 MHz) */
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/serial.c b/cleopatre/u-boot-1.1.6/cpu/spc300/serial.c
index 811fd52d8b..0e79732540 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/serial.c
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/serial.c
@@ -28,13 +28,13 @@
#error must define CONFIG_USART0
#endif
-ulong get_master_clock(gd_t* gd)
+int get_master_clock(gd_t* gd)
{
bd_t *bd = gd->bd;
spc300_nvram_t *nvram = (spc300_nvram_t*)bd->bi_nvram_addr;
ulong masterclk;
- switch((nvram->pkg_cfg & 0x03)>>2)
+ switch((nvram->pkg_cfg & 0x0C)>>2)
{
case 0:
masterclk = 100000000;
@@ -67,7 +67,7 @@ void serial_setbrg (void)
if ((baudrate = gd->baudrate) <= 0)
baudrate = CONFIG_BAUDRATE;
- baud_divisor = (get_master_clock(gd) + 8*baudrate) / (16 * baudrate);
+ baud_divisor = (get_master_clock((gd_t*)gd) + 8*baudrate) / (16 * baudrate);
writel(readl(UART_LCR_1) | 0x80, UART_LCR_1);
writel(baud_divisor & 0x00ff, UART_DLL_1);
writel((baud_divisor & 0xff00) >> 8, UART_DLH_1);
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
index 15d2826953..95e1b9b2b6 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
@@ -370,6 +370,24 @@ poll_RB_CLK_DIV_STAT_ARM:
ldr r2, [r10, #32] /* load SREFR content from NVRAM */
str r2, [r1, #SREFR] /* store configuration to config reg */
+ /* Find Freq parameters from NVRAM (struct address is in r10) */
+ ldr r2, [r10, #8] /* load pkg_cfg */
+ and r2, r2, #0x0c
+ lsr r2, r2, #2 /* r1 = freq */
+ cmp r2, #3 /* freq = 150MHz ? */
+ bne .NotHighSpeed /* no : don't touch pipe and latch */
+
+ /* Increase Read Pipe when freq > 143MHz */
+ ldr r2, [r1, #SCTLR] /* r2 = SCTLR */
+ orr r2, r2, #(0x03 << SCTLR_read_pipe_BitAddressOffset)
+ str r2, [r1, #SCTLR] /* SCTLR -> set read pipe to 3 */
+
+ /* Set SDRAM latch when freq > 143MHZ */
+ ldr r3, =MARIA_REGBANK_BASE
+ mov r2, #1
+ str r2, [r3, #RB_SDRAM_RETURN_LAT]
+
+.NotHighSpeed:
/* reinitialize SDRAM for changes to take effect */
ldr r2, [r1, #SCTLR] /* r2 = SCTLR */
orr r2, r2, #0x01