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authorCyril Jourdan2012-08-08 11:12:36 +0200
committerCyril Jourdan2012-09-20 09:42:56 +0200
commite701858bceda0cb76d58f947b0fe68cb6323c96e (patch)
tree3247cb17c4283a2ec88b30bb45997c225f22542f /cleopatre/u-boot-1.1.6/cpu/spc300/pll_init.S
parent0b7839300e7022376c9237d2edab4e4f0ee5ec61 (diff)
{cleo/u-boot, common}: use common/include/asm/arch/ips, refs #3119
Diffstat (limited to 'cleopatre/u-boot-1.1.6/cpu/spc300/pll_init.S')
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/pll_init.S78
1 files changed, 39 insertions, 39 deletions
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/pll_init.S b/cleopatre/u-boot-1.1.6/cpu/spc300/pll_init.S
index 767b886855..5f52389a99 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/pll_init.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/pll_init.S
@@ -52,19 +52,19 @@ pll_init:
* Switch OFF PLLs (before doing configuration)
*/
/* System PLL */
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
ldr r1, =PLL_CMD_OFF
- str r1, [r0, #RB_SPLL_PD]
+ str r1, [r0, #RB_SPLL_PD_OFFSET]
/* Peripheral PLL */
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
ldr r1, =PLL_CMD_OFF
- str r1, [r0, #RB_PPLL_PD]
+ str r1, [r0, #RB_PPLL_PD_OFFSET]
/* DSP PLL */
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
ldr r1, =PLL_CMD_OFF
- str r1, [r0, #RB_DPLL_PD]
+ str r1, [r0, #RB_DPLL_PD_OFFSET]
/*
* Configure PLLs (while switched off)
@@ -85,85 +85,85 @@ pll_init:
/* System PLL */
/* config : fbdiv, prediv, lbws, sscg_enable, sscg_fcw, sscg_fmw, sscg_mdw */
/* PLL_CLK_600MHz */
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
ldr r1, = 0
- str r1, [r0, #RB_SPLL_EN] /* RB_SPLL_EN = 0 */
+ str r1, [r0, #RB_SPLL_EN_OFFSET] /* RB_SPLL_EN = 0 */
adr r4, .LpoolSYSfbdiv /* r4 points to the begining of the array */
ldr r1, [r4, r3] /* r1 = array[Xclk*16 + Freq*4]; we take the element of the array indexed with Xclk */
- str r1, [r0, #RB_SPLL_FBDIV]
+ str r1, [r0, #RB_SPLL_FBDIV_OFFSET]
adr r4, .LpoolSYSprediv /* r4 points to the begining of the array */
ldr r1, [r4, r3] /* r1 = array[Xclk*16 + Freq*4]; we take the element of the array indexed with Xclk */
- str r1, [r0, #RB_SPLL_PREDIV]
+ str r1, [r0, #RB_SPLL_PREDIV_OFFSET]
ldr r1, = PLL_LBWS_ON
- str r1, [r0, #RB_SPLL_LBWS] /* RB_SPLL_LBWS = 1 */
+ str r1, [r0, #RB_SPLL_LBWS_OFFSET] /* RB_SPLL_LBWS = 1 */
ldr r1, = 1 /* turn on spread spectrum */
- str r1, [r0, #RB_SPLL_EN] /* RB_SPLL_EN = 1 */
+ str r1, [r0, #RB_SPLL_EN_OFFSET] /* RB_SPLL_EN = 1 */
adr r4, .LSpreadSpectrumFCW /* turn on spread spectrum */
ldr r1, [r4, r5]
- str r1, [r0, #RB_SPLL_FCW] /* RB_SPLL_FCW = See table... */
+ str r1, [r0, #RB_SPLL_FCW_OFFSET] /* RB_SPLL_FCW = See table... */
adr r4, .LSpreadSpectrumFMW
ldr r1, [r4, r5]
- str r1, [r0, #RB_SPLL_FMW] /* RB_SPLL_FMW = See table... */
+ str r1, [r0, #RB_SPLL_FMW_OFFSET] /* RB_SPLL_FMW = See table... */
adr r4, .LSpreadSpectrumMDW
ldr r1, [r4, r5]
- str r1, [r0, #RB_SPLL_MDW] /* RB_SPLL_MDW = See table... */
+ str r1, [r0, #RB_SPLL_MDW_OFFSET] /* RB_SPLL_MDW = See table... */
/* Peripheral PLL */
/* config : fbdiv, prediv, lbws, sscg_enable, sscg_fcw, sscg_fmw, sscg_mdw */
/* PLL_CLK_600MHz */
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
adr r4, .LpoolPERIPHfbdiv /* r4 points to the begining of the array */
ldr r1, [r4, r2] /* r1 = array[Xclk*4]; we take the element of the array indexed with Xclk */
- str r1, [r0, #RB_PPLL_FBDIV]
+ str r1, [r0, #RB_PPLL_FBDIV_OFFSET]
adr r4, .LpoolPERIPHprediv /* r4 points to the begining of the array */
ldr r1, [r4, r2] /* r1 = array[Xclk*4]; we take the element of the array indexed with Xclk */
- str r1, [r0, #RB_PPLL_PREDIV]
+ str r1, [r0, #RB_PPLL_PREDIV_OFFSET]
ldr r1, = PLL_LBWS_OFF
- str r1, [r0, #RB_PPLL_LBWS] /* RB_PPLL_LBWS = 0 */
+ str r1, [r0, #RB_PPLL_LBWS_OFFSET] /* RB_PPLL_LBWS = 0 */
/* DSP PLL */
/* config : fbdiv, prediv, lbws, sscg_enable, sscg_fcw, sscg_fmw, sscg_mdw */
/* PLL_CLK_600MHz */
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
adr r4, .LpoolDSPfbdiv /* r4 points to the begining of the array */
ldr r1, [r4, r2] /* r1 = array[Xclk*4]; we take the element of the array indexed with Xclk */
- str r1, [r0, #RB_DPLL_FBDIV]
+ str r1, [r0, #RB_DPLL_FBDIV_OFFSET]
adr r4, .LpoolDSPprediv /* r4 points to the begining of the array */
ldr r1, [r4, r2] /* r1 = array[Xclk*4]; we take the element of the array indexed with Xclk */
- str r1, [r0, #RB_DPLL_PREDIV]
+ str r1, [r0, #RB_DPLL_PREDIV_OFFSET]
ldr r1, = PLL_LBWS_OFF
- str r1, [r0, #RB_DPLL_LBWS] /* RB_DPLL_LBWS = 0 */
+ str r1, [r0, #RB_DPLL_LBWS_OFFSET] /* RB_DPLL_LBWS = 0 */
/* System PLL */
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
/* Release spread spectrum reset */
ldr r1, = 1
- str r1, [r0, #RB_SPLL_SSCGNRST]
+ str r1, [r0, #RB_SPLL_SSCGNRST_OFFSET]
/*
* Switch ON PLLs and wait 200uS (or more)
* until they stabilize
*/
ldr r1, =PLL_CMD_ON
- str r1, [r0, #RB_SPLL_PD]
+ str r1, [r0, #RB_SPLL_PD_OFFSET]
/* Peripheral PLL */
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
ldr r1, =PLL_CMD_ON
- str r1, [r0, #RB_PPLL_PD]
+ str r1, [r0, #RB_PPLL_PD_OFFSET]
/* DSP PLL */
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
ldr r1, =PLL_CMD_ON
- str r1, [r0, #RB_DPLL_PD]
+ str r1, [r0, #RB_DPLL_PD_OFFSET]
/* active wait */
ldr r0, =PLL_WAIT_TIME
@@ -176,29 +176,29 @@ pll_init:
* Switch to PLL clock
*/
/* System PLL */
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
ldr r1, =PLL_CMD_PLL
- str r1, [r0, #RB_SPLL_BYPASS]
+ str r1, [r0, #RB_SPLL_BYPASS_OFFSET]
.LpollSPLLstat:
- ldr r1, [r0, #RB_SPLL_BYPASS_STAT]
+ ldr r1, [r0, #RB_SPLL_BYPASS_STAT_OFFSET]
cmp r1, #PLL_IS_PLL
bne .LpollSPLLstat
/* Peripheral PLL */
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
ldr r1, =PLL_CMD_PLL
- str r1, [r0, #RB_PPLL_BYPASS]
+ str r1, [r0, #RB_PPLL_BYPASS_OFFSET]
.LpollPPLLstat:
- ldr r1, [r0, #RB_PPLL_BYPASS_STAT]
+ ldr r1, [r0, #RB_PPLL_BYPASS_STAT_OFFSET]
cmp r1, #PLL_IS_PLL
bne .LpollPPLLstat
/* DSP PLL */
- ldr r0, =REGBANK_BASE
+ ldr r0, =MARIA_REGBANK_BASE
ldr r1, =PLL_CMD_PLL
- str r1, [r0, #RB_DPLL_BYPASS]
+ str r1, [r0, #RB_DPLL_BYPASS_OFFSET]
.LpollDPLLstat:
- ldr r1, [r0, #RB_DPLL_BYPASS_STAT]
+ ldr r1, [r0, #RB_DPLL_BYPASS_STAT_OFFSET]
cmp r1, #PLL_IS_PLL
bne .LpollDPLLstat