summaryrefslogtreecommitdiff
path: root/cleopatre/linux-2.6.25.10-spc300
diff options
context:
space:
mode:
authorsave2009-11-20 10:01:20 +0000
committersave2009-11-20 10:01:20 +0000
commit618d1fa29ca1b8c04f7510e678ee51cd7d8babbd (patch)
treeae46b11df592493b995939876eeb6a5cdee613f8 /cleopatre/linux-2.6.25.10-spc300
parentb285a40a0a824cbbdcd96706c0c07f8583682f2c (diff)
cleo/linux/driver/ethernet: implement dma burst and flow control, closes #625
The DMA burst mode wasn't activated so each access to the bus and SDRAM controller was for only 32bits. Now, we have activated busrt mode so, we can make a INCR 16. We also have activated flow control for a better transfer synchronisation. git-svn-id: svn+ssh://pessac/svn/cesar/trunk@6435 017c9cb6-072f-447c-8318-d5b54f68fe89
Diffstat (limited to 'cleopatre/linux-2.6.25.10-spc300')
-rw-r--r--cleopatre/linux-2.6.25.10-spc300/drivers/net/arm/synop3504.c4
-rw-r--r--cleopatre/linux-2.6.25.10-spc300/drivers/net/arm/synop3504_hw.c8
-rw-r--r--cleopatre/linux-2.6.25.10-spc300/drivers/net/arm/synop3504_reg.h33
3 files changed, 41 insertions, 4 deletions
diff --git a/cleopatre/linux-2.6.25.10-spc300/drivers/net/arm/synop3504.c b/cleopatre/linux-2.6.25.10-spc300/drivers/net/arm/synop3504.c
index a6e719914e..26bf7646c8 100644
--- a/cleopatre/linux-2.6.25.10-spc300/drivers/net/arm/synop3504.c
+++ b/cleopatre/linux-2.6.25.10-spc300/drivers/net/arm/synop3504.c
@@ -27,8 +27,8 @@
*/
#define DRV_NAME "Synop3504"
-#define DRV_VERSION "2.3"
-#define DRV_RELDATE "nov 13, 2009"
+#define DRV_VERSION "2.4"
+#define DRV_RELDATE "nov 17, 2009"
//#define TRACE_FRAME 1
//#define TRACE(...) printk(DRV_NAME": " __VA_ARGS__)
diff --git a/cleopatre/linux-2.6.25.10-spc300/drivers/net/arm/synop3504_hw.c b/cleopatre/linux-2.6.25.10-spc300/drivers/net/arm/synop3504_hw.c
index ac165a5291..1d52afcaa5 100644
--- a/cleopatre/linux-2.6.25.10-spc300/drivers/net/arm/synop3504_hw.c
+++ b/cleopatre/linux-2.6.25.10-spc300/drivers/net/arm/synop3504_hw.c
@@ -183,8 +183,10 @@ void SynopsysAttach(Synopsys *synop, uint32_t macbase, uint32_t dmabase, uint32_
*/
void SynopsysInit(Synopsys *synop, uint32_t txaddr, uint32_t rxaddr)
{
- SynopsysWriteDmaReg(synop, DmaBusMode, DmaResetOff);
- SynopsysWriteDmaReg(synop, DmaControl, DmaStoreAndForwardTx | DmaStoreAndForwardRx);
+ SynopsysWriteDmaReg(synop, DmaBusMode, DmaSeparatePBLEnable | DmaRxBurstLength32 |
+ DmaFixedBurstEnable | DmaBurstLength32 | DmaResetOff);
+ SynopsysWriteDmaReg(synop, DmaControl, DmaStoreAndForwardTx | DmaRxThreshCtrl32 |
+ DmaEnHwFlowCtrl | DmaRxFlowCtrlAct3K | DmaRxFlowCtrlDeact1K);
SynopsysWriteDmaReg(synop, DmaInterrupt, 0); //All DMA Interrupts disabled
SynopsysWriteDmaReg(synop, DmaTxBaseAddr, txaddr);
SynopsysWriteDmaReg(synop, DmaRxBaseAddr, rxaddr);
@@ -213,6 +215,8 @@ void SynopsysInit(Synopsys *synop, uint32_t txaddr, uint32_t rxaddr)
GmacSelectMii|GmacLoopbackOff|GmacFESpeed10|GmacFullDuplex|
GmacTxEnable|GmacRxEnable);
}
+ SynopsysWriteMacReg(synop, GmacFlowControl, GmacFlowCtrlTxEn | GmacFlowCtrlRxEn | GmacFlowCtrlThresh144 | GmacFlowCtrlUnicast |
+ ((0x1000 << GmacFlowCtrlTimePauseShift) & GmacFlowCtrlTimePauseMask));
TRACE(" GmacIntMask=%x\n",SynopsysReadMacReg(synop, GmacIntMask));
TRACE(" MmcIntMaskTx=%x\n",SynopsysReadMacReg(synop, MmcIntrMaskTx));
TRACE(" MmcIntMaskRx=%x\n",SynopsysReadMacReg(synop, MmcIntrMaskRx));
diff --git a/cleopatre/linux-2.6.25.10-spc300/drivers/net/arm/synop3504_reg.h b/cleopatre/linux-2.6.25.10-spc300/drivers/net/arm/synop3504_reg.h
index 5aabecc3aa..33d88916a6 100644
--- a/cleopatre/linux-2.6.25.10-spc300/drivers/net/arm/synop3504_reg.h
+++ b/cleopatre/linux-2.6.25.10-spc300/drivers/net/arm/synop3504_reg.h
@@ -305,6 +305,22 @@ enum GmacFrameFilterReg
GmacPromiscuousModeOff = 0x00000000, //Receive filtered packets only
};
+/** GmacFlowControl registers field */
+enum GmacFlowControlReg
+{
+ GmacFlowCtrlTimePauseShift=16,
+ GmacFlowCtrlTimePauseMask= 0xFFFF0000, //Pause time for transit control frames
+ GmacFlowCtrlDisZQuanta = 0x00000080, //Disable automatic Zero-Quanta pause control frame generation
+ GmacFlowCtrlThresh256 = 0x00000030, //Pause time minus 256 slot times
+ GmacFlowCtrlThresh144 = 0x00000020, //Pause time minus 144 slot times
+ GmacFlowCtrlThresh28 = 0x00000010, //Pause time minus 28 slot times
+ GmacFlowCtrlThresh4 = 0x00000000, //Pause time minus 4 slot times
+ GmacFlowCtrlUnicast = 0x00000008, //Enable Flow Control on Unicast frames
+ GmacFlowCtrlRxEn = 0x00000004, //Enable Rx Flow Control
+ GmacFlowCtrlTxEn = 0x00000002, //Enable Tx Flow Control
+ GmacFlowCtrlBackPress = 0x00000001, //Activate back-pressure
+};
+
/** GmacGmiiAddr registers field */
enum GmacGmiiAddrReg
{
@@ -336,6 +352,16 @@ enum GmacGmiiDataReg
/** DmaBusMode registers field */
enum DmaBusModeReg
{
+ DmaSeparatePBLEnable = 0x00800000, //Use a separate Burst Length for TX and RX
+ DmaSeparatePBLDisable= 0x00000000,
+
+ DmaRxBurstLength32 = 0x00400000, //Programmable DMA RX burst length = 32
+ DmaRxBurstLength16 = 0x00200000, //RX burst length = 16
+ DmaRxBurstLength8 = 0x00100000, //RX burst length = 8
+ DmaRxBurstLength4 = 0x00080000, //RX burst length = 4
+ DmaRxBurstLength2 = 0x00040000, //RX burst length = 2
+ DmaRxBurstLength1 = 0x00020000, //RX burst length = 1
+
DmaFixedBurstEnable = 0x00010000, //Fixed Burst SINGLE, INCR4, INCR8 or INCR16
DmaFixedBurstDisable = 0x00000000, // SINGLE, INCR
@@ -404,6 +430,13 @@ enum DmaControlReg
DmaFwdErrorFrames = 0x00000080, //Forward error frames
DmaFwdUnderSzFrames = 0x00000040, //Forward undersize frames
+
+ DmaRxThreshCtrl = 0x00000018, //Controls thre Threh of MTL rx Fifo
+ DmaRxThreshCtrl128 = 0x00000018, //Controls thre Threh of MTL rx Fifo 128
+ DmaRxThreshCtrl96 = 0x00000010, //Controls thre Threh of MTL rx Fifo 96
+ DmaRxThreshCtrl32 = 0x00000008, //Controls thre Threh of MTL rx Fifo 32
+ DmaRxThreshCtrl64 = 0x00000000, //Controls thre Threh of MTL rx Fifo 64
+
DmaTxSecondFrame = 0x00000004, //Operate on second frame
DmaRxStart = 0x00000002, //Start/Stop reception
};