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path: root/cleopatre/linux-2.6.25.10-spc300/drivers/net/arm/synop3504_reg.h
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Diffstat (limited to 'cleopatre/linux-2.6.25.10-spc300/drivers/net/arm/synop3504_reg.h')
-rw-r--r--cleopatre/linux-2.6.25.10-spc300/drivers/net/arm/synop3504_reg.h33
1 files changed, 33 insertions, 0 deletions
diff --git a/cleopatre/linux-2.6.25.10-spc300/drivers/net/arm/synop3504_reg.h b/cleopatre/linux-2.6.25.10-spc300/drivers/net/arm/synop3504_reg.h
index 5aabecc3aa..33d88916a6 100644
--- a/cleopatre/linux-2.6.25.10-spc300/drivers/net/arm/synop3504_reg.h
+++ b/cleopatre/linux-2.6.25.10-spc300/drivers/net/arm/synop3504_reg.h
@@ -305,6 +305,22 @@ enum GmacFrameFilterReg
GmacPromiscuousModeOff = 0x00000000, //Receive filtered packets only
};
+/** GmacFlowControl registers field */
+enum GmacFlowControlReg
+{
+ GmacFlowCtrlTimePauseShift=16,
+ GmacFlowCtrlTimePauseMask= 0xFFFF0000, //Pause time for transit control frames
+ GmacFlowCtrlDisZQuanta = 0x00000080, //Disable automatic Zero-Quanta pause control frame generation
+ GmacFlowCtrlThresh256 = 0x00000030, //Pause time minus 256 slot times
+ GmacFlowCtrlThresh144 = 0x00000020, //Pause time minus 144 slot times
+ GmacFlowCtrlThresh28 = 0x00000010, //Pause time minus 28 slot times
+ GmacFlowCtrlThresh4 = 0x00000000, //Pause time minus 4 slot times
+ GmacFlowCtrlUnicast = 0x00000008, //Enable Flow Control on Unicast frames
+ GmacFlowCtrlRxEn = 0x00000004, //Enable Rx Flow Control
+ GmacFlowCtrlTxEn = 0x00000002, //Enable Tx Flow Control
+ GmacFlowCtrlBackPress = 0x00000001, //Activate back-pressure
+};
+
/** GmacGmiiAddr registers field */
enum GmacGmiiAddrReg
{
@@ -336,6 +352,16 @@ enum GmacGmiiDataReg
/** DmaBusMode registers field */
enum DmaBusModeReg
{
+ DmaSeparatePBLEnable = 0x00800000, //Use a separate Burst Length for TX and RX
+ DmaSeparatePBLDisable= 0x00000000,
+
+ DmaRxBurstLength32 = 0x00400000, //Programmable DMA RX burst length = 32
+ DmaRxBurstLength16 = 0x00200000, //RX burst length = 16
+ DmaRxBurstLength8 = 0x00100000, //RX burst length = 8
+ DmaRxBurstLength4 = 0x00080000, //RX burst length = 4
+ DmaRxBurstLength2 = 0x00040000, //RX burst length = 2
+ DmaRxBurstLength1 = 0x00020000, //RX burst length = 1
+
DmaFixedBurstEnable = 0x00010000, //Fixed Burst SINGLE, INCR4, INCR8 or INCR16
DmaFixedBurstDisable = 0x00000000, // SINGLE, INCR
@@ -404,6 +430,13 @@ enum DmaControlReg
DmaFwdErrorFrames = 0x00000080, //Forward error frames
DmaFwdUnderSzFrames = 0x00000040, //Forward undersize frames
+
+ DmaRxThreshCtrl = 0x00000018, //Controls thre Threh of MTL rx Fifo
+ DmaRxThreshCtrl128 = 0x00000018, //Controls thre Threh of MTL rx Fifo 128
+ DmaRxThreshCtrl96 = 0x00000010, //Controls thre Threh of MTL rx Fifo 96
+ DmaRxThreshCtrl32 = 0x00000008, //Controls thre Threh of MTL rx Fifo 32
+ DmaRxThreshCtrl64 = 0x00000000, //Controls thre Threh of MTL rx Fifo 64
+
DmaTxSecondFrame = 0x00000004, //Operate on second frame
DmaRxStart = 0x00000002, //Start/Stop reception
};