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authorsave2009-07-27 12:49:33 +0000
committersave2009-07-27 12:49:33 +0000
commit92e41c26578d36c31490c4343d09484c08c6c85e (patch)
treed896e8bffd2ac9a149af02bba9b9a26de48ae01c
parent85a207141a68f9b6416eff211d9c0fb63005e5aa (diff)
[CLEO][U-BOOT]NVRAM base addr and detection
- Added base address for NVRAM bi field - Stopped U-Boot if NVRAM is not present - if NVRAM not present skip PIO, GPIOs, Ethernet configuration - Added mmu during start-up - Suppressed base address for SPI flash driver - FLASH_SIZE become FLASH AREA git-svn-id: svn+ssh://pessac/svn/cesar/trunk@5077 017c9cb6-072f-447c-8318-d5b54f68fe89
-rw-r--r--cleopatre/u-boot-1.1.6/board/arizona/arizona.c17
-rw-r--r--cleopatre/u-boot-1.1.6/board/arizona/flash_spi.c8
-rw-r--r--cleopatre/u-boot-1.1.6/board/spk300g/flash.c11
-rw-r--r--cleopatre/u-boot-1.1.6/board/spk300g/spk300g.c14
-rw-r--r--cleopatre/u-boot-1.1.6/common/cmd_bootm.c2
-rw-r--r--cleopatre/u-boot-1.1.6/common/cmd_mmuon.c6
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300-fcm3/nvram.S2
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300-fcm3/start.S11
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/nvram.S23
-rw-r--r--cleopatre/u-boot-1.1.6/cpu/spc300/start.S8
-rw-r--r--cleopatre/u-boot-1.1.6/include/configs/arizona.h15
-rw-r--r--cleopatre/u-boot-1.1.6/include/configs/spk300g.h5
-rw-r--r--cleopatre/u-boot-1.1.6/include/flash.h4
13 files changed, 97 insertions, 29 deletions
diff --git a/cleopatre/u-boot-1.1.6/board/arizona/arizona.c b/cleopatre/u-boot-1.1.6/board/arizona/arizona.c
index 6c53dff45a..29eb43bc69 100644
--- a/cleopatre/u-boot-1.1.6/board/arizona/arizona.c
+++ b/cleopatre/u-boot-1.1.6/board/arizona/arizona.c
@@ -126,7 +126,7 @@ int board_init (void)
register volatile unsigned int nvram_addr asm ("r10");
/* NVRAM address will be passed to C from assembly start-up in reg r10 */
- gd->bd->bi_nvram_addr = ((nvram_addr & 0x00FFFFFF) | PHYS_FLASH_SPI_1);
+ gd->bd->bi_nvram_addr = nvram_addr;
/* arch number of SPiDCOM Board */
gd->bd->bi_arch_number = MACH_TYPE_SPC300;
@@ -135,7 +135,10 @@ int board_init (void)
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
/* Enable Ctrlc */
- console_init_f ();
+ console_init_f();
+
+ /* Active MMU and Data Cache for better performances */
+ do_mmuon();
return 0;
} /* board_init */
@@ -144,6 +147,15 @@ int board_init (void)
int board_late_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
+ spc300_nvram_t *nvram = NULL;
+
+ /* Now printf is allowed we can print an eventually NVRAM error */
+ nvram = (spc300_nvram_t *)(gd->bd->bi_nvram_addr);
+ if((gd->bd->bi_nvram_addr & 0xFF000000) != PHYS_FLASH_SPI_1)
+ {
+ printf("No NVRAM Found\n");
+ while(1);
+ }
/* Set Ethernet MAC Address */
set_eth_mac_addr(gd->bd);
@@ -164,5 +176,6 @@ int dram_init (void)
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = get_sdram_size(gd->bd);
+
return 0;
} /* dram_init */
diff --git a/cleopatre/u-boot-1.1.6/board/arizona/flash_spi.c b/cleopatre/u-boot-1.1.6/board/arizona/flash_spi.c
index 289d815803..a4d539cfe1 100644
--- a/cleopatre/u-boot-1.1.6/board/arizona/flash_spi.c
+++ b/cleopatre/u-boot-1.1.6/board/arizona/flash_spi.c
@@ -645,7 +645,7 @@ outahere:
* Purpose: Read SPI flash
* Return Value: int
*/
-int flash_read_spi (volatile unsigned char *addr, volatile unsigned char *data, int lenght, int dirty_flag, int do_cmp)
+int flash_read_spi (volatile unsigned char *gl_addr, volatile unsigned char *data, int lenght, int dirty_flag, int do_cmp)
{
int rc = ERR_OK;
unsigned int tx_conf, rx_conf, rx_max_words, int_len, words_to_read;
@@ -660,6 +660,10 @@ int flash_read_spi (volatile unsigned char *addr, volatile unsigned char *data,
int rest = 0;
char get_first_time = 0;
char addr_boundary_flag = 0;
+ volatile unsigned char *addr;
+
+ /* Whatever the address, only offset is important */
+ addr = (volatile unsigned char*)(((unsigned int)(gl_addr)) & 0x00FFFFFF);
/* maximum number of byted that SPI controller
can receive in one go is size of RX FIFO - 8 bytes */
@@ -1088,7 +1092,7 @@ printf("rx_conf = %#x\n", rx_conf);
int write_buff_spi (flash_info_t * info, uchar * src, ulong dest, ulong cnt)
{
volatile unsigned char *data = (volatile unsigned char *) src;
- volatile unsigned char *addr = (volatile unsigned char *) dest;
+ volatile unsigned char *addr = (volatile unsigned char*)(((unsigned int)(dest)) & 0x00FFFFFF);
int lenght = cnt;
unsigned int kprint = 0;
int cflag, iflag;
diff --git a/cleopatre/u-boot-1.1.6/board/spk300g/flash.c b/cleopatre/u-boot-1.1.6/board/spk300g/flash.c
index 6ded3c3d6a..999a6cc798 100644
--- a/cleopatre/u-boot-1.1.6/board/spk300g/flash.c
+++ b/cleopatre/u-boot-1.1.6/board/spk300g/flash.c
@@ -270,7 +270,7 @@ ulong flash_init (void)
memset (flash_info[i].protect, 0, flash_info[i].sector_count);
if (i == 0)
- flashbase = PHYS_FLASH_1;
+ flashbase = PHYS_FLASH_SPI_1;
else
panic ("configured too many flash banks!\n");
@@ -634,7 +634,7 @@ outahere:
* Purpose: Read SPI flash
* Return Value: int
*/
-int flash_read_spi (volatile unsigned char *addr, volatile unsigned char *data, int lenght, int dirty_flag, int do_cmp)
+int flash_read_spi (volatile unsigned char *gl_addr, volatile unsigned char *data, int lenght, int dirty_flag, int do_cmp)
{
int rc = ERR_OK;
unsigned int tx_conf, rx_conf, rx_max_words, int_len, words_to_read;
@@ -649,6 +649,11 @@ int flash_read_spi (volatile unsigned char *addr, volatile unsigned char *data,
int rest = 0;
char get_first_time = 0;
char addr_boundary_flag = 0;
+ volatile unsigned char *addr;
+
+ /* Whatever the address, only offset is important */
+ addr = (volatile unsigned char*)(((unsigned int)(gl_addr)) & 0x00FFFFFF);
+
/* maximum number of byted that SPI controller
can receive in one go is size of RX FIFO - 8 bytes */
@@ -1077,7 +1082,7 @@ printf("rx_conf = %#x\n", rx_conf);
int write_buff (flash_info_t * info, uchar * src, ulong dest, ulong cnt)
{
volatile unsigned char *data = (volatile unsigned char *) src;
- volatile unsigned char *addr = (volatile unsigned char *) dest;
+ volatile unsigned char *addr = (volatile unsigned char*)(((unsigned int)(dest)) & 0x00FFFFFF);
int lenght = cnt;
unsigned int kprint = 0;
int cflag, iflag;
diff --git a/cleopatre/u-boot-1.1.6/board/spk300g/spk300g.c b/cleopatre/u-boot-1.1.6/board/spk300g/spk300g.c
index 97e242fa16..9254624a82 100644
--- a/cleopatre/u-boot-1.1.6/board/spk300g/spk300g.c
+++ b/cleopatre/u-boot-1.1.6/board/spk300g/spk300g.c
@@ -126,7 +126,7 @@ int board_init (void)
register volatile unsigned int nvram_addr asm ("r10");
/* NVRAM address will be passed to C from assembly start-up in reg r10 */
- gd->bd->bi_nvram_addr = ((nvram_addr & 0x00FFFFFF) | PHYS_FLASH_1);
+ gd->bd->bi_nvram_addr = nvram_addr;
/* arch number of SPiDCOM Board */
gd->bd->bi_arch_number = MACH_TYPE_SPC300;
@@ -137,6 +137,9 @@ int board_init (void)
/* Enable Ctrlc */
console_init_f ();
+ /* Active MMU and Data Cache for better performances */
+ do_mmuon();
+
return 0;
} /* board_init */
@@ -144,6 +147,15 @@ int board_init (void)
int board_late_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
+ spc300_nvram_t *nvram = NULL;
+
+ /* Now printf is allowed we can print an eventually NVRAM error */
+ nvram = (spc300_nvram_t *)(gd->bd->bi_nvram_addr);
+ if((gd->bd->bi_nvram_addr & 0xFF000000) != PHYS_FLASH_SPI_1)
+ {
+ printf("No NVRAM Found\n");
+ while(1);
+ }
/* Set Ethernet MAC Address */
set_eth_mac_addr(gd->bd);
diff --git a/cleopatre/u-boot-1.1.6/common/cmd_bootm.c b/cleopatre/u-boot-1.1.6/common/cmd_bootm.c
index a61d774839..a17d3fa8fb 100644
--- a/cleopatre/u-boot-1.1.6/common/cmd_bootm.c
+++ b/cleopatre/u-boot-1.1.6/common/cmd_bootm.c
@@ -85,7 +85,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define IS_IN_SPI_RANGE(x) ( \
( PHYS_FLASH_SPI_1 <= (x) ) && \
- ( (x) <= ( ( PHYS_FLASH_SPI_1 + PHYS_FLASH_SPI_SIZE) ) ) \
+ ( (x) <= ( ( PHYS_FLASH_SPI_1 + FLASH_SPI_AREA) ) ) \
)
#define SPI_FLASH_TO_RAM_ADDR ( (unsigned char *)0x40100000 )
diff --git a/cleopatre/u-boot-1.1.6/common/cmd_mmuon.c b/cleopatre/u-boot-1.1.6/common/cmd_mmuon.c
index c95e60a177..17c5772216 100644
--- a/cleopatre/u-boot-1.1.6/common/cmd_mmuon.c
+++ b/cleopatre/u-boot-1.1.6/common/cmd_mmuon.c
@@ -88,7 +88,7 @@ typedef struct {
/* REGION TABLES */
/* VADDRESS, PAGESIZE, NUMPAGES, AP, CB, PADDRESS, &PT */
Region spiRegion
- = {0x00000000, 1024, 8, RWRW, WT, 0x00000000, &masterPT};
+ = {0x30000000, 1024, 8, RWRW, WT, 0x30000000, &masterPT};
Region pageTableRegion
= {0x40000000, 1024, 1, RWRW, WT, 0x40000000, &masterPT};
@@ -394,6 +394,8 @@ void readFAR(void)
/* putting it all together */
int do_mmuon (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
+ /* WARNING this command is used during SPC300 board_init before uart
+ * was configured, so printf can't be used */
unsigned int enable, change;
icache_disable();
@@ -429,7 +431,7 @@ int do_mmuon (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
controlSet(enable, change); /* enable cache and MMU */
- printf ("MMU and caches turned on.\n");
+// printf ("MMU and caches turned on.\n");
//memset ((char*)0x40100000, 0xff, 20);
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300-fcm3/nvram.S b/cleopatre/u-boot-1.1.6/cpu/spc300-fcm3/nvram.S
index b18d9d622c..02409b69b9 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300-fcm3/nvram.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300-fcm3/nvram.S
@@ -45,11 +45,13 @@
detect_nvram:
ldr r10, =nvram_dft /* if nvram is not found, we will have this value in r10 */
ldr r1, =-1 /* init value for loop counter */
+ ldr r4, =PHYS_FLASH_SPI_1 /* Offset of the SPI Direct access address */
.Lsect:
add r1, r1, #1
cmp r1, #LAST_SECTOR
bge .Lreturn /* we did not found it */
mov r0, r1, lsl #16 /* r0= r1<<16 = r1*0x10000 */
+ add r0, r0, r4 /* Add SPI Direct base address */
ldr r2, [r0, #0] /* load r2 with the first 4 bytes from the sector beginning */
ldr r3, =nvram_magic /* r3 = nvram_magic (previously defined : char *nvram_magic = "NVRAM\0\0\0";) */
ldr r3, [r3, #0] /* r3 <- first 4 bytes of magic word */
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300-fcm3/start.S b/cleopatre/u-boot-1.1.6/cpu/spc300-fcm3/start.S
index 7aafa237a2..104202f177 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300-fcm3/start.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300-fcm3/start.S
@@ -257,7 +257,7 @@ wait_mpu_child0:
remap_end:
bl cpu_init_crit
first_init_end:
- /* As we don't call cpu_init_crit we need to find NVRAM address */
+ /* We need to find NVRAM address */
mov ip, lr /* perserve link reg across call */
bl detect_nvram /* r10 will hold the NVRAM address */
mov lr, ip /* restore link */
@@ -266,14 +266,13 @@ first_init_end:
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
-#ifdef CONFIG_SKIP_LOWLEVEL_INIT
- /* As we don't call cpu_init_crit we need to find NVRAM address */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ bl cpu_init_crit
+#endif
+ /* We need to find NVRAM address */
mov ip, lr /* perserve link reg across call */
bl detect_nvram /* r10 will hold the NVRAM address */
mov lr, ip /* restore link */
-#else
- bl cpu_init_crit
-#endif
#endif
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/nvram.S b/cleopatre/u-boot-1.1.6/cpu/spc300/nvram.S
index b18d9d622c..8c5d6a2f6a 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/nvram.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/nvram.S
@@ -33,6 +33,8 @@
.align 2 @ Align to word boundary; "2" means the number of bits that must be zero
.globl detect_nvram
.type detect_nvram, %function
+ .globl check_nvram
+ .type check_nvram, %function
/*
@@ -45,11 +47,13 @@
detect_nvram:
ldr r10, =nvram_dft /* if nvram is not found, we will have this value in r10 */
ldr r1, =-1 /* init value for loop counter */
+ ldr r4, =PHYS_FLASH_SPI_1 /* Offset of the SPI Direct access address */
.Lsect:
add r1, r1, #1
cmp r1, #LAST_SECTOR
bge .Lreturn /* we did not found it */
mov r0, r1, lsl #16 /* r0= r1<<16 = r1*0x10000 */
+ add r0, r0, r4 /* Add SPI Direct base address */
ldr r2, [r0, #0] /* load r2 with the first 4 bytes from the sector beginning */
ldr r3, =nvram_magic /* r3 = nvram_magic (previously defined : char *nvram_magic = "NVRAM\0\0\0";) */
ldr r3, [r3, #0] /* r3 <- first 4 bytes of magic word */
@@ -73,6 +77,25 @@ detect_nvram:
/*
*************************************************************************
*
+ * NVRAM check if address is in SPI area
+ *
+ *************************************************************************
+ */
+check_nvram:
+ mov r0, #-1
+ mov r2, r10
+ ldr r3, =0xFF000000
+ and r2, r10, r3 /* load Mapping area of NVRAM address */
+ ldr r3, =PHYS_FLASH_SPI_1
+ cmp r2, r3 /* check is NVRAM is in SPI area */
+ bne .Lwrongnvram /* no : return -1 under r0 */
+ mov r0, #0 /* yes: return 0 under r0 */
+.Lwrongnvram:
+ mov pc, lr /* back to my caller */
+
+/*
+ *************************************************************************
+ *
* NVRAM default values
*
*************************************************************************
diff --git a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
index 23a600532f..15d2826953 100644
--- a/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
+++ b/cleopatre/u-boot-1.1.6/cpu/spc300/start.S
@@ -253,6 +253,13 @@ in_sdram:
ldr r1, =0x00000001
str r1, [r0, #RB_BUS_SYS_REMAPPED]
+ /*
+ * Check if a correct NVRAM was found
+ * NVRAM address was under r10
+ */
+ bl check_nvram /* we pass NVRAM addr in r10 and wait result under r0 */
+ cmp r0, #0
+ bne bl_no_nvram
/*
* Configure GPIOs and PIO
@@ -276,6 +283,7 @@ in_sdram:
bic r1, r1, #RST_INTF /* clear bit 1 of RB_RST_GROUP, sw_rst_intf -> 0 */
str r1, [r0, #RB_RST_GROUP]
+bl_no_nvram:
/* EXT reset */
ldr r0, =REGBANK_BASE
ldr r1, [r0, #RB_RST_MODULE]
diff --git a/cleopatre/u-boot-1.1.6/include/configs/arizona.h b/cleopatre/u-boot-1.1.6/include/configs/arizona.h
index 5bcacbcd31..d1d1318a31 100644
--- a/cleopatre/u-boot-1.1.6/include/configs/arizona.h
+++ b/cleopatre/u-boot-1.1.6/include/configs/arizona.h
@@ -79,10 +79,9 @@
#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTARGS "console=ttyS0,115200"
+#define CONFIG_BOOTARGS "mem=28M console=ttyS0,115200 ignore_loglevel"
-//#define CONFIG_BOOTCOMMAND "spidboot"
-#define CONFIG_BOOTCOMMAND ""
+#define CONFIG_BOOTCOMMAND "spidboot"
#define CONFIG_COMMANDS \
( (CONFIG_CMD_DFL | \
@@ -127,8 +126,8 @@
#undef CFG_ENV_IS_EMBEDDED
#define CFG_ENV_IS_NOWHERE 1
-#define PHYS_FLASH_SPI_1 0x00000000
-#define PHYS_FLASH_SPI_SIZE 0x800000 /* 8 megs main flash */
+#define PHYS_FLASH_SPI_1 0x30000000
+#define FLASH_SPI_AREA 0x0FFFFFFF
#define CFG_FLASH_SPI_BASE 0xF0000000
#define CFG_MAX_FLASH_SPI_BANKS 1
#define CFG_FLASH_SPI_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */
@@ -165,10 +164,10 @@
#endif
#define CONFIG_ETHADDR 00:50:c2:38:00:0B
-#define CONFIG_SERVERIP 192.168.002.069
-#define CONFIG_IPADDR 192.168.002.199
+#define CONFIG_SERVERIP 192.168.003.069
+#define CONFIG_IPADDR 192.168.003.104
#define CONFIG_NETMASK 255.255.255.000
-#define CONFIG_GATEWAYIP 192.168.002.069
+#define CONFIG_GATEWAYIP 192.168.003.069
#define CONFIG_HOSTNAME spc300
#define CONFIG_BOOTFILE "linux-kernel-2.6.25.10-arm"
diff --git a/cleopatre/u-boot-1.1.6/include/configs/spk300g.h b/cleopatre/u-boot-1.1.6/include/configs/spk300g.h
index a204375dc5..f5ac9edeab 100644
--- a/cleopatre/u-boot-1.1.6/include/configs/spk300g.h
+++ b/cleopatre/u-boot-1.1.6/include/configs/spk300g.h
@@ -106,6 +106,7 @@
( (CONFIG_CMD_DFL | \
CFG_CMD_PING | \
CFG_CMD_MMUON | \
+ CFG_CMD_SPIDUPD | \
CFG_CMD_SPIDBOOT | \
CFG_CMD_CACHE | \
CFG_CMD_NET) & \
@@ -167,8 +168,8 @@
/* SPI Flash configuration */
#define CFG_MAX_FLASH_BANKS 1
-#define PHYS_FLASH_1 0x30000000
-#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
+#define PHYS_FLASH_SPI_1 0x30000000
+#define FLASH_SPI_AREA 0x0FFFFFFF
#define CFG_MAX_FLASH_SECT 256
/* Timeout for Flash Erase */
#define CFG_FLASH_SPI_ERASE_TOUT (20*CFG_HZ)
diff --git a/cleopatre/u-boot-1.1.6/include/flash.h b/cleopatre/u-boot-1.1.6/include/flash.h
index 0b90367884..d2d7c952c2 100644
--- a/cleopatre/u-boot-1.1.6/include/flash.h
+++ b/cleopatre/u-boot-1.1.6/include/flash.h
@@ -77,8 +77,8 @@ typedef struct {
/* macro to determine which flash holds this addr - NOR or SPI */
#define IS_IN_SPI_RANGE(x) ( \
- ( PHYS_FLASH_1 <= ( (unsigned int)(x) ) ) && \
- ( ( (unsigned int)(x) ) <= ( ( PHYS_FLASH_1 + PHYS_FLASH_SIZE) ) ) \
+ ( PHYS_FLASH_SPI_1 <= ( (unsigned int)(x) ) ) && \
+ ( ( (unsigned int)(x) ) <= ( ( PHYS_FLASH_SPI_1 + FLASH_SPI_AREA) ) ) \
)
/* Prototypes */