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/*
 * cpu/spc300-fcm3/start.S
 *
 * Copyright (C) 2009 SPiDCOM Technologies
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */


#include <config.h>
#include <version.h>
#include <asm/hardware.h>

/*
 *************************************************************************
 *
 * Jump vector table as in table 3.1 in [1]
 *
 *************************************************************************
 */


.globl _start
_start:
	b	reset
	ldr	pc, _undefined_instruction
	ldr	pc, _software_interrupt
	ldr	pc, _prefetch_abort
	ldr	pc, _data_abort
	ldr	pc, _not_used
	ldr	pc, _irq
	ldr	pc, _fiq

_undefined_instruction:
	.word undefined_instruction
_software_interrupt:
	.word software_interrupt
_prefetch_abort:
	.word prefetch_abort
_data_abort:
	.word 
_not_used:
	.word not_used
_irq:
	.word irq
_fiq:
	.word fiq

	.balignl 16,0xdeadbeef


/*
 *************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * setup Memory and board specific bits prior to relocation.
 * relocate armboot to ram
 * setup stack
 *
 *************************************************************************
 */

_TEXT_BASE:
	.word	TEXT_BASE

.globl _armboot_start
_armboot_start:
	.word _start

/*
 * These are defined in the board-specific linker script.
 */
.globl _bss_start
_bss_start:
	.word __bss_start

.globl _bss_end
_bss_end:
	.word _end

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
	.word	0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
	.word 0x0badc0de
#endif


/*
 * the actual reset code
 */

reset:
	/*
	 * set the cpu to SVC32 mode
	 */
	mrs	r0,cpsr
	bic	r0,r0,#0x1f
	orr	r0,r0,#0xd3
	msr	cpsr,r0

#ifdef CONFIG_EXEC_FROM_SDRAM
	/*
	 * We give the possibility to load U-Boot anywhere into the 
	 * SDRAM and to execute it without flash.
	 * This allow a first time flashing operation when flash is blank.
	 * To boot from SDRAM, change r10 value to something different from 0 :
	 * r10 = 0  : boot from Flash
	 * r10 != 0 : boot from SDRAM
	 */
	mov     r10,#0
	nop
	nop
	nop

	cmp	r10,#0
	blne	first_init_end

#ifdef CONFIG_EXEC_FROM_SPI
	b       first_init_end
#endif /* CONFIG_EXEC_FROM_SPI */

	/* 
	 * FPGA reset 
	 */
	ldr     r0, =FCM3_FPGA_MPIO1_BASE
	ldr     r1, =0x00000001
	str     r1, [r0, #0x50]
	ldr     r0, =FCM3_FPGA_MPIO1_BASE
	ldr     r1, =0x00000002
	str     r1, [r0, #0x00]			/* enable PIO1 */
	ldr     r0, =FCM3_FPGA_MPIO1_BASE
	ldr     r1, =0x00000002
	str     r1, [r0, #0x10]			/* PIO1 output */
	ldr     r0, =FCM3_FPGA_MPIO1_BASE
	ldr     r1, =0x00000000
	str     r1, [r0, #0x2c]			/* write 0 in PIO1 */

	/*
	 * FCM3 interrupt controler 
	 */
 	ldr     r0, =FCM3_IT_CTRL_BASE
	ldr     r1, =0x0000000f
	str     r1, [r0, #0x00]			/* int0 = nFiq prio=15 */
 	ldr     r0, =FCM3_IT_CTRL_BASE
	ldr     r1, =0x00000007
	str     r1, [r0, #0x04]			/* int1 = nIrq prio=7 */
	ldr     r0, =FCM3_GIC_BASE
	ldr     r1, =0xffffffff
	str     r1, [r0, #0x28]			/* disable all INTs GIC_IDCR0 */
	ldr     r0, =FCM3_GIC_BASE
	ldr     r1, =0xffffffff
	str     r1, [r0, #0x2c]			/* disable all INTs GIC_IDCR1 */
	ldr     r0, =FCM3_GIC_BASE
	ldr     r1, =0xffffffff
	str     r1, [r0, #0x30]			/* clear all INTs GIC_ICCR0 */
	ldr     r0, =FCM3_GIC_BASE
	ldr     r1, =0xffffffff
	str     r1, [r0, #0x34]			/* clear all INTs GIC_ICCR1 */
	ldr     r0, =FCM3_GIC_BASE
	ldr     r1, =0x00000003
	str     r1, [r0, #0x20]			/* enable int0 and int1 */

	/*
	 * map the ITCM to FCM3_ITCM_BASE
	 */
	mov		r0, #FCM3_ITCM_BASE
	add		r0, r0, #15
	mcr		p15, 0, r0, c9, c1, 1

	/* 
	 * copy the remap code into the ITCM
	*/
	adr	r0, remap_start
	ldr	r1, =FCM3_ITCM_BASE
	ldr r2, remap_start
/*	ldr r3, remap_end
	sub r2, r3, r2*/			/* r2 = size of remap code */
	add r2, r0, #0x1000			/* r2 = end of remap code address */

remap_copy_loop:
	ldmia	r0!, {r3-r9, r11}		/* copy from source address [r0], do not clobber r10 (holds NVRAM addr)    */
	stmia	r1!, {r3-r9, r11}		/* copy to   target address [r1]    */
	cmp	r0, r2			/* until source end addreee [r2]    */
	ble	remap_copy_loop

/*	bkpt	0 */

	adr		lr, remap_end 		/* compute the remap_end address after the flash remap */
	adr		r0, _start
	sub		lr, lr, r0
	ldr		r0, =MARIA_EBI_FLASH_BASE
	add		lr, lr, r0			/* lr = addr(remap_end) - addr(_start) + MARIA_EBI_FLASH_BASE */
	ldr		pc, =FCM3_ITCM_BASE			/* execute remap code into ITCM */
remap_start:	
	/*
	 * FCM3 MPU address decoders
   	 */
	ldr     r0, =FCM3_MPU_CHILD3_BASE
	ldr     r1, =0x0000011f
	str     r1, [r0, #0x00]			/* child 3 MPU_SBA_DEF0 -> open 4GB space */
	ldr     r0, =FCM3_MPU_CHILD3_BASE
	ldr     r1, =0x00000000
	str     r1, [r0, #0x04]			/* child 3 MPU_SBA_DEF1 -> disable */
	ldr     r0, =FCM3_MPU_CHILD3_BASE
	ldr     r1, =0x00000000
	str     r1, [r0, #0x08]			/* child 3 MPU_SBA_DEF2 -> disable */
	ldr     r0, =FCM3_MPU_MAIN_BASE
	ldr     r1, =0x0000011f
	str     r1, [r0, #0x0c]			/* main MPU_SBA_DEF3 -> open 4GB space */
	ldr     r0, =FCM3_MPU_MAIN_BASE
	ldr     r1, =0x00000000
	str     r1, [r0, #0x08]			/* main MPU_SBA_DEF2 -> disable BS2 */
	ldr     r0, =FCM3_MPU_CHILD0_BASE
	ldr     r1, =0x0000011f
	str     r1, [r0, #0x00]			/* child 0 -> open 4GB space */
	mov		r0, #1000
wait_mpu_child0:
	sub		r0, r0, #1
	cmp		r0, #0
	bne		wait_mpu_child0

	ldr     r0, =FCM3_MPU_MAIN_BASE
	ldr     r1, =(MARIA_EBI_FLASH_BASE | 0x0107)
	str     r1, [r0, #0x04]
	ldr     r0, =FCM3_MPU_CHILD1_BASE
	ldr     r1, =(MARIA_EBI_FLASH_BASE | 0x0107)
	str     r1, [r0, #0x00]
	ldr     r0, =FCM3_MPU_MAIN_BASE
	ldr     r1, =(MARIA_BASE | 0x0104)
	str     r1, [r0, #0x00]			/* main MPU_SBA_DEF0 -> move BS1 to a Maria unused address space */
	ldr     r0, =MARIA_MPU_CHILD0_BASE
	ldr     r1, =(MARIA_BASE | 0x0104)
	str     r1, [r0, #0x00]			/* child 0 -> idem */
	mov		pc, lr

remap_end:
	bl	cpu_init_crit	
first_init_end:	
        /* As we don't call cpu_init_crit we need to find NVRAM address */
        mov	ip, lr              /* perserve link reg across call */
        bl      detect_nvram        /* r10 will hold the NVRAM address */
        mov	lr, ip              /* restore link */
#else
	/*
	 * we do sys-critical inits only at reboot,
	 * not when booting from ram!
	 */
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
        /* As we don't call cpu_init_crit we need to find NVRAM address */
        mov	ip, lr              /* perserve link reg across call */
        bl      detect_nvram        /* r10 will hold the NVRAM address */
        mov	lr, ip              /* restore link */
#else
	bl	cpu_init_crit
#endif
#endif

#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate:				/* relocate U-Boot to RAM	    */
	adr	r0, _start		/* r0 <- current position of code   */
	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
	cmp     r0, r1                  /* don't reloc during debug         */
	beq     stack_setup

	ldr	r2, _armboot_start
	ldr	r3, _bss_start
	sub	r2, r3, r2		/* r2 <- size of armboot            */
	add	r2, r0, r2		/* r2 <- source end address         */

copy_loop:
	ldmia	r0!, {r3-r9, r11}		/* copy from source address [r0], do not clobber r10 (holds NVRAM addr)    */
	stmia	r1!, {r3-r9, r11}		/* copy to   target address [r1]    */
	cmp	r0, r2			/* until source end addreee [r2]    */
	ble	copy_loop
#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */

	/* Set up the stack						    */
stack_setup:
	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
	sub	r0, r0, #CFG_MALLOC_LEN	/* malloc area                      */
	sub	r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
#ifdef CONFIG_USE_IRQ
	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
	sub	sp, r0, #12		/* leave 3 words for abort-stack    */

clear_bss:
	ldr	r0, _bss_start		/* find start of bss segment        */
	ldr	r1, _bss_end		/* stop here                        */
	mov 	r2, #0x00000000		/* clear                            */

clbss_l:str	r2, [r0]		/* clear loop...                    */
	add	r0, r0, #4
	cmp	r0, r1
	ble	clbss_l

	ldr	pc, _start_armboot

_start_armboot:
	.word start_armboot


/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */
cpu_init_crit:
	/*
	 * flush v4 I/D caches
	 */
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */

	/*
	 * disable MMU stuff and caches
	 */
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
	mcr	p15, 0, r0, c1, c0, 0

        /*
         * Add wait states to the EBI flash accesses
         */
        ldr     r0, =MARIA_EBI_BASE
        ldr     r1, =0x00000004
        str     r1, [r0, #0x00]                 /* EBI_CSR0 byte enable 8bits */
        ldr     r0, =MARIA_EBI_BASE
        ldr     r1, =0x0000501F
        str     r1, [r0, #0x20]                 /* EBI_RWR0 read wait states */
        ldr     r0, =MARIA_EBI_BASE
        ldr     r1, =0x00003304
        str     r1, [r0, #0x40]                 /* EBI_WWR0 write wait states */

#ifndef CONFIG_EXEC_FROM_SPI
	/*
	 * lock the PLL
	 */
	ldr     r0, =MARIA_PLL_CLOCK_BASE
	ldr     r1, =0xa34c0000
	str     r1, [r0, #0x2c]			/* CM_LFOSCR disable low freq osc */
	ldr     r0, =MARIA_PLL_CLOCK_BASE
#ifdef MARIA_CORE_90MHZ
	ldr     r1, =0x7ab2082c			/* CM_PDPR  12MHz->180MHz, S=1, M=45, P=3 */
#else
	ldr     r1, =0x7ab20b31			/* CM_PDPR  12MHz->50, S=4, M=50, P=3 */
#endif
	str     r1, [r0, #0x10]	
	ldr     r0, =MARIA_PLL_CLOCK_BASE
	ldr     r1, =0x59c10154
	str     r1, [r0, #0x0c]			/* CM_PSTR  pll startup time ?? */
	ldr     r0, =MARIA_PLL_CLOCK_BASE
#ifdef MARIA_CORE_90MHZ
	ldr     r1, =0xdb5a0003 		/* CM_DIVR  ArmClk= FSCLK/2 (90MHz), SClk= ArmClk/2 (45MHz) */
	str     r1, [r0, #0x18]
	ldr     r1, =0x00000000 		/* CM_DIVBR  MHExtClk= SClk/1 -> 45MHz */
#else
	ldr     r1, =0xdb5a0002 		/* CM_DIVR  ArmClk= FSCLK/2 (25MHz), SClk= ArmClk/1 (25MHz) */
	str     r1, [r0, #0x18]
	ldr     r1, =0x00000000 		/* CM_DIVBR MHExtClk= SClk/1 (25MHz) */
#endif
	str     r1, [r0, #0x1c]
	ldr     r0, =MARIA_PLL_CLOCK_BASE
	ldr     r1, =0x03b9001e
	str     r1, [r0, #0x04]			/* CM_PMCR enable MHEXTCLK */
	ldr     r0, =MARIA_PLL_CLOCK_BASE
	ldr     r1, =0x80a40000
	str     r1, [r0, #0x08]			/* CM_WFIR wfi instruction does not impact clocks */
	ldr     r0, =MARIA_PLL_CLOCK_BASE
	ldr     r1, =0xd0c90001
	str     r1, [r0, #0x20]			/* CM_SELR, switch to high speed mode */

	/*
	 * release the FPGA reset
	 */
	ldr     r0, =MARIA_FPGA_MPIO1_BASE
	ldr     r1, =0x00000002
	str     r1, [r0, #0x2c]			/* reset MPIO1 */
	mov		r0, #1000
wait_fpga_reset:
	sub	r0, r0, #1
	cmp	r0, #0
	bne	wait_fpga_reset
#endif /* CONFIG_EXEC_FROM_SPI */

	/*
	 * Go setup Memory and board specific bits prior to relocation.
	 */
	mov	ip, lr		/* perserve link reg across call */
	bl	lowlevel_init	/* go setup pll,mux,memory */
	mov	lr, ip		/* restore link */

        /*
	 * SDRAM reinitialization
	 */
	mov	ip, lr		/* perserve link reg across call */
	bl	sdram_init	/* go reinitialize SDRAM with NVRAM params */
	mov	lr, ip		/* restore link */

        mov	pc, lr		/* back to my caller */


/*
 *************************************************************************
 *
 * Interrupt handling
 *
 *************************************************************************
 */

@
@ IRQ stack frame.
@
#define S_FRAME_SIZE	72

#define S_OLD_R0	68
#define S_PSR		64
#define S_PC		60
#define S_LR		56
#define S_SP		52

#define S_IP		48
#define S_FP		44
#define S_R10		40
#define S_R9		36
#define S_R8		32
#define S_R7		28
#define S_R6		24
#define S_R5		20
#define S_R4		16
#define S_R3		12
#define S_R2		8
#define S_R1		4
#define S_R0		0

#define MODE_SVC 0x13
#define I_BIT	 0x80

/*
 * use bad_save_user_regs for abort/prefetch/undef/swi ...
 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 */

	.macro	bad_save_user_regs
	@ carve out a frame on current user stack
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12

	ldr	r2, _armboot_start
	sub	r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
	sub	r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
	@ get values for "aborted" pc and cpsr (into parm regs)
	ldmia	r2, {r2 - r3}
	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
	add	r5, sp, #S_SP
	mov	r1, lr
	stmia	r5, {r0 - r3}	@ save sp_SVC, lr_SVC, pc, cpsr
	mov	r0, sp		@ save current stack into r0 (param register)
	.endm

	.macro	irq_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
	add	r8, sp, #S_PC
	stmdb	r8, {sp, lr}^		@ Calling SP, LR
	str	lr, [r8, #0]		@ Save calling PC
	mrs	r6, spsr
	str	r6, [r8, #4]		@ Save CPSR
	str	r0, [r8, #8]		@ Save OLD_R0
	mov	r0, sp
	.endm

	.macro	irq_restore_user_regs
	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
	mov	r0, r0
	ldr	lr, [sp, #S_PC]			@ Get PC
	add	sp, sp, #S_FRAME_SIZE
	subs	pc, lr, #4		@ return & move spsr_svc into cpsr
	.endm

	.macro get_bad_stack
	ldr	r13, _armboot_start		@ setup our mode stack
	sub	r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
	sub	r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack

	str	lr, [r13]	@ save caller lr in position 0 of saved stack
	mrs	lr, spsr	@ get the spsr
	str	lr, [r13, #4]	@ save spsr in position 1 of saved stack
	mov	r13, #MODE_SVC	@ prepare SVC-Mode
	@ msr	spsr_c, r13
	msr	spsr, r13	@ switch modes, make sure moves will execute
	mov	lr, pc		@ capture return pc
	movs	pc, lr		@ jump to next instruction & switch modes.
	.endm

	.macro get_irq_stack			@ setup IRQ stack
	ldr	sp, IRQ_STACK_START
	.endm

	.macro get_fiq_stack			@ setup FIQ stack
	ldr	sp, FIQ_STACK_START
	.endm

/*
 * exception handlers
 */
	.align  5
undefined_instruction:
	get_bad_stack
	bad_save_user_regs
	bl	do_undefined_instruction

	.align	5
software_interrupt:
	get_bad_stack
	bad_save_user_regs
	bl	do_software_interrupt

	.align	5
prefetch_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_prefetch_abort

	.align	5
data_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_data_abort

	.align	5
not_used:
	get_bad_stack
	bad_save_user_regs
	bl	do_not_used

#ifdef CONFIG_USE_IRQ

	.align	5
irq:
	get_irq_stack
	irq_save_user_regs
	bl 	do_irq
	irq_restore_user_regs

	.align	5
fiq:
	get_fiq_stack
	/* someone ought to write a more effiction fiq_save_user_regs */
	irq_save_user_regs
	bl 	do_fiq
	irq_restore_user_regs

#else

	.align	5
irq:
	get_bad_stack
	bad_save_user_regs
	bl	do_irq

	.align	5
fiq:
	get_bad_stack
	bad_save_user_regs
	bl	do_fiq

#endif