summaryrefslogtreecommitdiff
path: root/2004/n/fpga/src/portserie/fifo/fifo.npl
blob: 81fdd87b8e85b07ef375aa5a179d0b9c8ab3c619 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
JDF G
// Created by Project Navigator ver 1.0
PROJECT fifo
DESIGN fifo
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s200
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
STIMULUS bch_afifo.vhd
SOURCE fifodriver.vhd
SOURCE ..\..\modele\nono_const.vhd
STIMULUS bch_sfifo.vhd
SOURCE sfifo.xco
STIMULUS bch_fifodriver.vhd
[Normal]
p_CompxlibTargetSimulator=xstvhd, spartan2, Design.t_compLibraries, 1078952453, ModelSim SE
[STATUS-ALL]
fifodriver.ngcFile=WARNINGS,1079734309
fifodriver.ngdFile=WARNINGS,1079734329
fifodriver.postMapVHDLSimModel=WARNINGS,1079734429
sfifo.ngcFile=ERRORS,0
[STRATEGY-LIST]
Normal=True