summaryrefslogtreecommitdiff
path: root/2004/n/fpga/src/portserie/fifo/bch_fifodriver.vhd
blob: 94fa9a2ebe32deb56040a7eeee2d5340edbef8ab (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
-- TestBench Template 

  LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.numeric_std.ALL;

  ENTITY bch_fd IS
  END bch_fd;

  ARCHITECTURE behavior OF bch_fd IS 

  -- Component Declaration
	COMPONENT fifodriver
	PORT(
	clk: in std_logic;
	rst: in std_logic;
	readreq: in std_logic;
	writereq: in std_logic;
	din: IN std_logic_VECTOR(7 downto 0);
	dout: OUT std_logic_VECTOR(7 downto 0);
	dready: out std_logic;
	full: OUT std_logic;
	empty: OUT std_logic;
	data_count: OUT std_logic_VECTOR(1 downto 0)
	);
	END COMPONENT;

signal clk:std_logic:='0';
signal rst:std_logic;
signal readreq:std_logic:='0';
signal writereq:std_logic:='0';
signal 	din: std_logic_VECTOR(7 downto 0):="01010101";
signal	dout: std_logic_VECTOR(7 downto 0);
signal	dready: std_logic;
signal	full: std_logic;
signal	empty: std_logic;
signal	data_count: std_logic_VECTOR(1 downto 0);




  BEGIN

uut: fifodriver PORT MAP(
		clk => clk,
		rst => rst,
		readreq => readreq,
		writereq => writereq,
		din => din,
		dout => dout,
		dready => dready,
		full => full,
		empty => empty,
		data_count => data_count
	);


	din <= std_logic_vector(unsigned(din) + 1) after 400 ns;
	rst<='1' , '0' after 510 ns;
	clk <= not clk after 25 ns;
	writereq <= not writereq after 700 ns;
	readreq <= not readreq after 900 ns;
	



  END;